CC2430ZDK

Not Recommended for New Designs CC2430 A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee® Applications • • • • • • • • 2.4 GHz IEEE 802.15.4 systems ZigBee® systems Home/building automation Industrial Control and Monitoring Low power wireless sensor networks PC peripherals Set-top boxes and remote controls Consumer Electronics Product Description The CC2430 comes in three different flash versions: CC2430F32/64/128, with 32/64/128 KB of flash memory respectively. The CC2430 is a true System-on-Chip (SoC) solution specifically tailored for IEEE 802.15.4 and ZigBee® applications. It enables ZigBee® nodes to be built with very low total bill-ofmaterial costs. The CC2430 combines the excellent performance of the leading CC2420 RF transceiver with an industry-standard enhanced 8051 MCU, 32/64/128 KB flash memory, 8 KB RAM and many other powerful features. Combined with the industry leading ZigBee® protocol stack (Z-Stack™) from Texas Instruments, the CC2430 provides the market’s most competitive ZigBee® solution. The CC2430 is highly suited for systems where ultra low power consumption is required. This is ensured by various operating modes. Short transition times between operating modes further ensure low power consumption. Key Features • • RF/Layout o 2.4 GHz IEEE 802.15.4 compliant RF transceiver (industry leading CC2420 radio core) o Excellent receiver sensitivity and robustness to interferers o Very few external components o Only a single crystal needed for mesh network systems o RoHS compliant 7x7mm QLP48 package • Low Power o Low current consumption (RX: 27 mA, TX: 27 mA, microcontroller running at 32 MHz) o Only 0.5 µA current consumption in powerdown mode, where external interrupts or the RTC can wake up the system o 0.3 µA current consumption in stand-by mode, where external interrupts can wake up the system o Very fast transition times from low-power modes to active mode enables ultra low average power consumption in low dutycycle systems o Wide supply voltage range (2.0V - 3.6V) Microcontroller o High performance and low power 8051 microcontroller core o 32, 64 or 128 KB in-system programmable flash o 8 KB RAM, 4 KB with data retention in all power modes o Powerful DMA functionality o Watchdog timer o One IEEE 802.15.4 MAC timer, one general 16-bit timer and two 8-bit timers o Hardware debug support • Peripherals CSMA/CA hardware support. Digital RSSI / LQI support Battery monitor and temperature sensor 12-bit ADC with up to eight inputs and configurable resolution o AES security coprocessor o Two powerful USARTs with support for several serial protocols o 21 general I/O pins, two with 20mA sink/source capability o o o o • Development tools o Powerful and flexible development tools available CC2430 Data Sheet (rev. 2.1) SWRS036F Page 1 of 211 Not Recommended for New Designs CC2430 Table Of Contents 1 2 3 4 ABBREVIATIONS................................................................................................................................ 5 REFERENCES....................................................................................................................................... 7 REGISTER CONVENTIONS .............................................................................................................. 8 FEATURES EMPHASIZED ................................................................................................................ 9 4.1 HIGH-PERFORMANCE AND LOW-POWER 8051-COMPATIBLE MICROCONTROLLER ............................... 9 4.2 UP TO 128 KB NON-VOLATILE PROGRAM MEMORY AND 2 X 4 KB DATA MEMORY ............................ 9 4.3 HARDWARE AES ENCRYPTION/DECRYPTION ....................................................................................... 9 4.4 PERIPHERAL FEATURES ......................................................................................................................... 9 4.5 LOW POWER.......................................................................................................................................... 9 4.6 IEEE 802.15.4 MAC HARDWARE SUPPORT ........................................................................................... 9 4.7 INTEGRATED 2.4GHZ DSSS DIGITAL RADIO ........................................................................................ 9 5 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 10 6 OPERATING CONDITIONS............................................................................................................. 10 7 ELECTRICAL SPECIFICATIONS .................................................................................................. 11 7.1 GENERAL CHARACTERISTICS .............................................................................................................. 12 7.2 RF RECEIVE SECTION ......................................................................................................................... 13 7.3 RF TRANSMIT SECTION ....................................................................................................................... 13 7.4 32 MHZ CRYSTAL OSCILLATOR .......................................................................................................... 14 7.5 32.768 KHZ CRYSTAL OSCILLATOR .................................................................................................... 14 7.6 32 KHZ RC OSCILLATOR..................................................................................................................... 15 7.7 16 MHZ RC OSCILLATOR ................................................................................................................... 15 7.8 FREQUENCY SYNTHESIZER CHARACTERISTICS ................................................................................... 16 7.9 ANALOG TEMPERATURE SENSOR ........................................................................................................ 16 7.10 ADC ................................................................................................................................................... 16 7.11 CONTROL AC CHARACTERISTICS........................................................................................................ 18 7.12 SPI AC CHARACTERISTICS ................................................................................................................. 19 7.13 DEBUG INTERFACE AC CHARACTERISTICS ......................................................................................... 20 7.14 PORT OUTPUTS AC CHARACTERISTICS ............................................................................................... 21 7.15 TIMER INPUTS AC CHARACTERISTICS................................................................................................. 21 7.16 DC CHARACTERISTICS ........................................................................................................................ 21 8 PIN AND I/O PORT CONFIGURATION ........................................................................................ 22 9 CIRCUIT DESCRIPTION ................................................................................................................. 24 9.1 CPU AND PERIPHERALS ...................................................................................................................... 25 9.2 RADIO ................................................................................................................................................. 26 10 APPLICATION CIRCUIT ................................................................................................................. 27 10.1 INPUT / OUTPUT MATCHING ................................................................................................................. 27 10.2 BIAS RESISTORS .................................................................................................................................. 27 10.3 CRYSTAL ............................................................................................................................................. 27 10.4 VOLTAGE REGULATORS ...................................................................................................................... 27 10.5 DEBUG INTERFACE .............................................................................................................................. 27 10.6 POWER SUPPLY DECOUPLING AND FILTERING...................................................................................... 28 11 8051 CPU .............................................................................................................................................. 30 11.1 8051 CPU INTRODUCTION .................................................................................................................. 30 11.2 MEMORY ............................................................................................................................................. 30 11.3 CPU REGISTERS .................................................................................................................................. 42 11.4 INSTRUCTION SET SUMMARY .............................................................................................................. 44 11.5 INTERRUPTS ........................................................................................................................................ 49 12 DEBUG INTERFACE......................................................................................................................... 60 12.1 DEBUG MODE ..................................................................................................................................... 60 12.2 DEBUG COMMUNICATION ................................................................................................................... 60 12.3 DEBUG COMMANDS ............................................................................................................................ 60 12.4 DEBUG LOCK BIT ................................................................................................................................ 60 12.5 DEBUG INTERFACE AND POWER MODES ............................................................................................. 64 13 PERIPHERALS ................................................................................................................................... 65 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 2 of 211 Not Recommended for New Designs CC2430 13.1 POWER MANAGEMENT AND CLOCKS ................................................................................................... 65 13.2 RESET ................................................................................................................................................. 71 13.3 FLASH CONTROLLER ........................................................................................................................... 71 13.4 I/O PORTS ............................................................................................................................................ 77 13.5 DMA CONTROLLER ............................................................................................................................ 88 13.6 16-BIT TIMER, TIMER1 ........................................................................................................................ 99 13.7 MAC TIMER (TIMER2)...................................................................................................................... 110 13.8 8-BIT TIMERS, TIMER 3 AND TIMER 4 ................................................................................................ 117 13.9 SLEEP TIMER ..................................................................................................................................... 126 13.10 ADC ................................................................................................................................................. 128 13.11 RANDOM NUMBER GENERATOR ....................................................................................................... 134 13.12 AES COPROCESSOR .......................................................................................................................... 136 13.13 WATCHDOG TIMER ........................................................................................................................... 141 13.14 USART............................................................................................................................................. 143 14 RADIO ................................................................................................................................................ 153 14.1 IEEE 802.15.4 MODULATION FORMAT ............................................................................................. 154 14.2 COMMAND STROBES ......................................................................................................................... 155 14.3 RF REGISTERS................................................................................................................................... 155 14.4 INTERRUPTS ...................................................................................................................................... 155 14.5 FIFO ACCESS .................................................................................................................................... 157 14.6 DMA ................................................................................................................................................ 157 14.7 RECEIVE MODE.................................................................................................................................. 158 14.8 RXFIFO OVERFLOW ......................................................................................................................... 158 14.9 TRANSMIT MODE ............................................................................................................................... 159 14.10 GENERAL CONTROL AND STATUS ...................................................................................................... 160 14.11 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION ..................................................... 160 14.12 FRAME FORMAT ................................................................................................................................ 161 14.13 SYNCHRONIZATION HEADER ............................................................................................................. 161 14.14 LENGTH FIELD ................................................................................................................................... 162 14.15 MAC PROTOCOL DATA UNIT ............................................................................................................. 162 14.16 FRAME CHECK SEQUENCE ................................................................................................................. 162 14.17 RF DATA BUFFERING ........................................................................................................................ 163 14.18 ADDRESS RECOGNITION .................................................................................................................... 164 14.19 ACKNOWLEDGE FRAMES .................................................................................................................. 165 14.20 RADIO CONTROL STATE MACHINE ..................................................................................................... 166 14.21 MAC SECURITY OPERATIONS (ENCRYPTION AND AUTHENTICATION).............................................. 168 14.22 LINEAR IF AND AGC SETTINGS ........................................................................................................ 168 14.23 RSSI / ENERGY DETECTION .............................................................................................................. 168 14.24 LINK QUALITY INDICATION .............................................................................................................. 168 14.25 CLEAR CHANNEL ASSESSMENT......................................................................................................... 169 14.26 FREQUENCY AND CHANNEL PROGRAMMING ..................................................................................... 169 14.27 VCO AND PLL SELF-CALIBRATION .................................................................................................. 169 14.28 OUTPUT POWER PROGRAMMING ....................................................................................................... 170 14.29 INPUT / OUTPUT MATCHING .............................................................................................................. 170 14.30 TRANSMITTER TEST MODES ............................................................................................................. 171 14.31 SYSTEM CONSIDERATIONS AND GUIDELINES .................................................................................... 173 14.32 PCB LAYOUT RECOMMENDATION .................................................................................................... 175 14.33 ANTENNA CONSIDERATIONS ............................................................................................................. 175 14.34 CSMA/CA STROBE PROCESSOR ....................................................................................................... 176 14.35 RADIO REGISTERS ............................................................................................................................. 183 15 VOLTAGE REGULATORS............................................................................................................. 202 15.1 VOLTAGE REGULATORS POWER-ON.................................................................................................. 202 16 EVALUATION SOFTWARE........................................................................................................... 202 17 REGISTER OVERVIEW ................................................................................................................. 203 18 PACKAGE DESCRIPTION (QLP 48) ............................................................................................ 206 18.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 48).................................................................... 207 18.2 PACKAGE THERMAL PROPERTIES ....................................................................................................... 207 18.3 SOLDERING INFORMATION ................................................................................................................ 207 18.4 TRAY SPECIFICATION ........................................................................................................................ 207 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 3 of 211 Not Recommended for New Designs CC2430 18.5 CARRIER TAPE AND REEL SPECIFICATION .......................................................................................... 207 19 ORDERING INFORMATION......................................................................................................... 209 20 GENERAL INFORMATION ........................................................................................................... 210 20.1 DOCUMENT HISTORY ........................................................................................................................ 210 21 ADDRESS INFORMATION ............................................................................................................ 210 22 TI WORLDWIDE TECHNICAL SUPPORT ................................................................................. 210 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 4 of 211 Not Recommended for New Designs 1 CC2430 Abbreviations ADC Analog to Digital Converter I/O Input / Output AES Advanced Encryption Standard I/Q In-phase / Quadrature-phase AGC Automatic Gain Control IEEE ARIB Association of Radio Industries and Businesses Institute of Electrical and Electronics Engineers IF Intermediate Frequency BCD Binary Coded Decimal INL Integral Nonlinearity BER Bit Error Rate IOC I/O Controller BOD Brown Out Detector IRQ Interrupt Request BOM Bill of Materials ISM Industrial, Scientific and Medical CBC Cipher Block Chaining ITU-T CBC-MAC Cipher Block Chaining Message Authentication Code International Telecommunication Union – Telecommunication Standardization Sector CCA Clear Channel Assessment IV Initialization Vector CCM Counter mode + CBC-MAC JEDEC Joint Electron Device Engineering Council CFB Cipher Feedback KB 1024 bytes CFR Code of Federal Regulations kbps kilo bits per second CMOS Complementary Metal Oxide Semiconductor LC Inductor-capacitor CMRR Common Mode Ratio Recjection LFSR Linear Feedback Shift Register LNA Low-Noise Amplifier LO Local Oscillator CPU Central Processing Unit CRC Cyclic Redundancy Check CSMA-CA Carrier Sense Multiple Access with Collision Avoidance LQI Link Quality Indication LSB Least Significant Bit / Byte CSP CSMA/CA Strobe Processor LSB Least Significant Byte CTR Counter mode (encryption) MAC Medium Access Control CW Continuous Wave MAC Message Authentication Code DAC Digital to Analog Converter MCU Microcontroller Unit DC Direct Current MFR MAC Footer DMA Direct Memory Access MHR MAC Header DNL Differential Nonlineraity MIC Message Integrity Code DSM Delta Sigma Modulator MISO Master In Slave Out DSSS Direct Sequence Spread Spectrum MOSI Master Out Slave In ECB Electronic Code Book (encryption) MPDU MAC Protocol Data Unit EM Evaluation Module MSB Most Significant Byte ENOB Effective Number of bits MSDU MAC Service Data Unit ESD Electro Static Discharge MUX Multiplexer ESR Equivalent Series Resistance NA Not Available ETSI European Telecommunications Standards Institute NC Not Connected EVM Error Vector Magnitude FCC Federal Communications Commission FCF Frame Control Field FCS Frame Check Sequence FFCTRL FIFO and Frame Control FIFO First In First Out HF High Frequency HSSD High Speed Serial Data OFB Output Feedback (encryption) O-QPSK Offset - Quadrature Phase Shift Keying PA Power Amplifier PCB Printed Circuit Board PER Packet Error Rate PHR PHY Header PHY Physical Layer PLL Phase Locked Loop CC2430 Data Sheet (rev. 2.1) SWRS036F Page 5 of 211 Not Recommended for New Designs CC2430 PM{0-3} Power Mode 0-3 SPI Serial Peripheral Interface PMC Power Management Controller SRAM Static Random Access Memory POR Power On Reset ST Sleep Timer PSDU PHY Service Data Unit T/R Tape and reel PWM Pulse Width Modulator T/R Transmit / Receive QLP Quad Leadless Package TBD To Be Decided / To Be Defined RAM Random Access Memory THD Total Harmonic Distortion RBW Resolution Bandwidth TI Texas Instruments RC Resistor-Capacitor TX Transmit RCOSC RC Oscillator UART RF Radio Frequency Universal Asynchronous Receiver/Transmitter RoHS Restriction on Hazardous Substances USART Universal Synchronous/Asynchronous Receiver/Transmitter RSSI Receive Signal Strength Indicator VCO Voltage Controlled Oscillator RTC Real-Time Clock VGA Variable Gain Amplifier RX Receive WDT Watchdog Timer SCK Serial Clock XOSC Crystal Oscillator SFD Start of Frame Delimiter SFR Special Function Register SHR Synchronization Header SINAD Signal-to-noise and distortion ratio CC2430 Data Sheet (rev. 2.1) SWRS036F Page 6 of 211 Not Recommended for New Designs 2 [1] CC2430 References IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf [2] NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NIST website. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf CC2430 Data Sheet (rev. 2.1) SWRS036F Page 7 of 211 Not Recommended for New Designs 3 CC2430 Register conventions Each SFR register is described in a separate table. The table heading is given in the following format: REGISTER NAME (SFR Address) - Register Description. Each RF register is described in a separate table. The table heading is given in the following format: REGISTER NAME (XDATA Address) In the register descriptions, each register bit is shown with a symbol indicating the access mode of the register bit. The register values are always given in binary notation unless prefixed by ‘0x’ which indicates hexadecimal notation. Table 1: Register bit conventions Symbol Access Mode R/W Read/write R Read only R0 Read as 0 R1 Read as 1 W Write only W0 Write as 0 W1 Write as 1 H0 Hardware clear H1 Hardware set CC2430 Data Sheet (rev. 2.1) SWRS036F Page 8 of 211 Not Recommended for New Designs 4 CC2430 Features Emphasized 4.1 High-Performance and Low-Power 8051-Compatible Microcontroller • Optimized 8051 core, which typically gives 8x the performance of a standard 8051 • Dual data pointers • In-circuit interactive debugging is supported for the IAR Embedded Workbench through a simple two-wire serial interface 4.2 Up to 128 KB Non-volatile Program Memory and 2 x 4 KB Data Memory • 32/64/128 KB of non-volatile flash memory in-system programmable through a simple two-wire interface or by the 8051 core • • Worst-case flash memory endurance: 1000 write/erase cycles Programmable read and write lock of portions of Flash memory for software security 4.5 Low Power • Four flexible power modes for reduced power consumption • System can wake up on external interrupt or real-time counter event • Low-power fully static CMOS design • System clock source can be 16 MHz RC oscillator or 32 MHz crystal oscillator. The 32 MHz oscillator is used when radio is active • Optional clock source for ultra-low power operation can be either low-power RC oscillator or an optional 32.768 kHz crystal oscillator 4.6 IEEE 802.15.4 MAC hardware support • Automatic preamble generator • Synchronization word insertion/detection • CRC-16 computation and checking over the MAC payload • Clear Channel Assessment • 4096 bytes of internal SRAM with data retention in all power modes • Energy detection / digital RSSI • • Link Quality Indication Additional 4096 bytes of internal SRAM with data retention in power modes 0 and 1 • CSMA/CA Coprocessor 4.7 Integrated 2.4GHz DSSS Digital Radio 4.3 Hardware AES Encryption/Decryption • • AES supported in hardware coprocessor 2.4 GHz IEEE 802.15.4 compliant RF transceiver (based on industry leading CC2420 radio core). Peripheral Features • • Powerful DMA Controller Excellent receiver sensitivity robustness to interferers • Power On Reset/Brown-Out Detection • 250 kbps data rate, 2 MChip/s chip rate • Eight channel ADC with configurable resolution • • Programmable watchdog timer • Real time clock with 32.768 kHz crystal oscillator • Four timers: one general 16-bit timer, two general 8-bit timers, one MAC timer Reference designs comply with worldwide radio frequency regulations covered by ETSI EN 300 328 and EN 300 440 class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan). Transmit on 2480MHz under FCC is supported by duty-cycling, or by reducing output power. • Two programmable USARTs for master/slave SPI or UART operation • 21 configurable general-purpose digital I/O-pins • True random number generator 4.4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 9 of 211 and Not Recommended for New Designs 5 CC2430 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Table 2: Absolute Maximum Ratings Parameter Min Max Units Supply voltage –0.3 3.9 V Voltage on any digital pin –0.3 VDD+0.3, max 3.9 V Voltage on the 1.8V pins (pin no. 22, 25-40 and 42) –0.3 2.0 V 10 dBm 150 °C Device not programmed 260 °C According to IPC/JEDEC J-STD-020C 100 to have a sufficiently large sample space. E.g. at least 1000 packets should be used to measure the sensitivity. The data transmitted over air must be spread according to [1] and the description on page 154. Pre-generated packets may be used, although [1] requires that the PER is averaged over random PSDU data. The CC2430 receive FIFO may be used to buffer data received during PER measurements, since it is able to buffer up to 128 bytes. The MDMCTRL1H.CORR_THR control register should be set to 20, as described in the Demodulator, Symbol Synchronizer and Data Decision section. The simplest way of making a PER measurement will be to use another CC2430 as the reference transmitter. However, this makes it difficult to measure the exact receiver performance. Using a signal generator, this may either be set up as O-QPSK with half-sine shaping or as MSK. If using O-QPSK, the phases must be selected according to [1]. If using MSK, the CC2430 Data Sheet (rev. 2.1) SWRS036F Page 174 of 211 Not Recommended for New Designs CC2430 Radio : PCB Layout Recommendation chip sequence must be modified such that the modulated MSK signal has the same phase shifts as the O-QPSK sequence previously defined. page 154. It can be seen from comparing the phase shifts of the O-QPSK signal with the frequency of a MSK signal that the MSK chip sequence is generated as: For a desired symbol sequence s0, s1, … , sn-1 of length n symbols, the desired chip sequence c0, c1, c2, …, c32n-1 of length 32n is found using table lookup from Table 44 on (c0 xnor c1), (c1 xor c2), (c2 xnor c3), … , (c32n-1 xor c32n) where c32n may be arbitrarily selected. 14.32 PCB Layout Recommendation In the Texas Instruments reference design, the top layer is used for signal routing, and the open areas are filled with metallization connected to ground using several vias. The area under the chip is used for grounding and must be well connected to the ground plane with several vias. The ground pins should be connected to ground as close as possible to the package pin using individual vias. The de-coupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by separate vias. Supply power filtering is very important. The external components should be as small as possible (0402 is recommended) and surface mount devices must be used. If using any external high-speed digital devices, caution should be used when placing these in order to avoid interference with the RF circuitry. A Development Kit, CC2430DK, with a fully assembled Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to obtain the best performance. The schematic, BOM and layout Gerber files for the reference designs are all available from the TI website. 14.33 Antenna Considerations CC2430 can be used together with various types of antennas. A differential antenna like a dipole would be the easiest to interface not needing a balun (balanced to un-balanced transformation network). The length of the λ/2-dipole antenna is given by: L = 14250 / f where f is in MHz, giving the length in cm. An antenna for 2450 MHz should be 5.8 cm. Each arm is therefore 2.9 cm. Other commonly used antennas for shortrange communication are monopole, helical and loop antennas. The single-ended monopole and helical would require a balun network between the differential output and the antenna. Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength (λ/4). They are very easy to design and can be implemented simply as a “piece of wire” or even integrated into the PCB. The length of the λ/4-monopole antenna is given by: where f is in MHz, giving the length in cm. An antenna for 2450 MHz should be 2.9 cm. Non-resonant monopole antennas shorter than λ/4 can also be used, but at the expense of range. In size and cost critical applications such an antenna may very well be integrated into the PCB. Enclosing the antenna in high dielectric constant material reduces the overall size of the antenna. Many vendors offer such antennas intended for PCB mounting. Helical antennas can be thought of as a combination of a monopole and a loop antenna. They are a good compromise in size critical applications. Helical antennas tend to be more difficult to optimize than the simple monopole. Loop antennas are easy to integrate into the PCB, but are less effective due to difficult impedance matching because of their very low radiation resistance. For low power applications the differential antenna is recommended giving the best range and because of its simplicity. L = 7125 / f CC2430 Data Sheet (rev. 2.1) SWRS036F Page 175 of 211 Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor The antenna should be connected as close as possible to the IC. If the antenna is located away from the RF pins the antenna should be matched to the feeding transmission line (50Ω). 14.34 CSMA/CA Strobe Processor The Command Strobe/CSMA-CA Processor (CSP) provides the control interface between the CPU and the Radio module in the CC2430. Strobe instruction is also used only to control the CSP. The Immediate Command Strobe instructions are described in section 14.34.7. The CSP interfaces with the CPU through the SFR register RFST and the RF registers CSPX, CSPY, CSPZ, CSPT and CSPCTRL. The CSP produces interrupt requests to the CPU. In addition the CSP interfaces with the MAC Timer by observing MAC Timer overflow events. Program execution mode means that the CSP executes a sequence of instructions, from a program memory or instruction memory, thus constituting a short user-defined program. The available instructions are from a set of 14 instructions. The instruction set is defined in section 14.34.8. The required program is first loaded into the CSP by the CPU, and then the CPU instructs the CSP to start executing the program. The CSP allows the CPU to issue command strobes to the radio thus controlling the operation of the radio. The CSP has two modes of operation as follows, which are described below. • • Immediate Command Strobe execution. Program execution Immediate Command Strobes are written as an Immediate Command Strobe instruction to the CSP which are issued instantly to the Radio module. The Immediate Command The program execution mode together with the MAC Timer allows the CSP to automate CSMA-CA algorithms and thus act as a coprocessor for the CPU. The operation of the CSP is described in detail in the following sections. The command strobes and other instructions supported by the CSP are given in section 14.34.8 on page 179. RFST (0xE1) – RF CSMA-CA/Strobe Processor Bit Name Reset R/W Description 7:0 INSTR[7:0] 0xC0 R/W Data written to this register will be written to the CSP instruction memory. Reading this register will return the CSP instruction currently being executed. 14.34.1 Instruction Memory The CSP executes single byte program instructions which are read from a 24 byte instruction memory. The instruction memory is written to sequentially through the SFR register RFST. An instruction write pointer is maintained within the CSP to hold the location within the instruction memory where the next instruction written to RFST will be stored. Following a reset the write pointer is reset to location 0. During each RFST register write, the write pointer will be incremented by 1 until the end of memory is reached when the write pointer will stop incrementing, thus writing more than 24 bytes only the last byte written will be stored in the last position. The first instruction written to RFST will be stored in location 0, the location where program execution starts. Thus a complete CSP program may contain a maximum of 24 bytes that is written to the instruction memory by writing each instruction in the desired order to the RFST register. Note that the program memory does not need to be filled, thus a CSP program may contain less than 24 bytes. The write pointer may be reset to 0 by writing the immediate command strobe instruction ISSTOP. In addition the write pointer will be reset to 0 when the command strobe SSTOP is executed in a program. Following a reset, the instruction memory is filled with SNOP (No Operation) instructions (opcode value 0xC0). While the CSP is executing a program, there shall be no attempts to write instructions to the instruction memory by writing to RFST. Failure to observe this rule can lead to incorrect program execution and corrupt instruction memory contents. However, Immediate Command Strobe instructions may be written to RFST (see section 14.34.3). CC2430 Data Sheet (rev. 2.1) SWRS036F Page 176 of 211 Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor 14.34.2 Data Registers The CSP has three data registers CSPT, CSPX, CSPY and CSPZ, which are read/write accessible for the CPU as RF registers. These registers are read or modified by some instructions, thus allowing the CPU to set parameters to be used by a CSP program or allowing the CPU to read CSP program status. The CSPT data register is not modified by any instruction. The CSPT data register is used to set a MAC Timer overflow compare value. Once program execution has started on the CSP, the content of this register is 14.34.3 IRQ_CSP_STOP: asserted when the processor has executed the last instruction in memory and when the processor stops due to a SSTOP or ISSTOP instruction or CSPT register equal zero. 14.34.5 During program execution, reading RFST will return the current instruction being executed. An exception to this is the execution of immediate command strobes, during which RFST will return C0h. • • IRQ_CSP_WT: asserted when the processor continues executing the next instruction after a WAIT W or WAITX instruction. IRQ_CSP_INT: asserted when the processor executes an INT instruction. Random Number Instruction There will be a delay in the update of the random number used by the RANDXY instruction. Therefore if an instruction, RANDXY, that uses this value is issued 14.34.6 Immediate Command Strobe instructions may be written to RFST while a program is being executed. In this case the Immediate instruction will bypass the instruction in the instruction memory, which will be completed once the Immediate instruction has been completed. Interrupt Requests The CSP has three interrupts flags which can produce the RF interrupt vector. These are the following: • Note: If the CSPT register compare function is not used, this register must be set to 0xFF before the program execution is started. Program Execution After the instruction memory has been filled, program execution is started by writing the immediate command strobe instruction ISSTART to the RFST register. The program execution will continue until either the instruction at last location has been executed, the CSPT data register contents is zero, a SSTOP instruction has been executed, an immediate ISSTOP instruction is written to RFST or until a SKIP instruction returns a location beyond the last location in the instruction memory. The CSP runs at 8 MHz clock frequency. 14.34.4 decremented by 1 each time the MAC timer overflows. When CSPT reaches zero, program execution is halted and the interrupt IRQ_CSP_STOP is asserted. The CSPT register will not be decremented if the CPU writes 0xFF to this register. immediately after a previous RANDXY instruction, the random value read may be the same in both cases. Running CSP Programs The basic flow for loading and running a program on the CSP is shown in Figure 50. When program execution stops due to end of program the current program remains in program memory. This makes it possible to run the same program again by starting execution with the ISSTART command. However, when program execution is stopped by the SSTOP or ISTOP instruction, the program memory will be cleared. It is also importat to note that a WAIT W or WEVENT instruction can not be executed between X register update and X data read by one of the following instructions: RPT, SKIP or WAITX. If this is done the CSPX register will be decremented on each MAC timer (Timer2) overflow occurrence. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 177 of 211 Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor no Write instruction to RFST All instructions written? yes Setup CSPT, CSPX, CSPY, CSPZ and CSPCTRL registers Start execution by writing ISSTART to RFST SSTOP instruction, end of program or writing ISTOP to RFST stops program Figure 50: Running a CSP program 14.34.7 Instruction Set Summary This section gives an overview of the instruction set. This is intended as a summary and definition of instruction opcodes. Refer to section 14.34.8 for a description of each instruction. Each instruction consists of one byte which is written to the RFST register to be stored in the instruction memory. they are executed immediately. If the CSP is already executing a program the current instruction will be delayed until the Immediate Strobe instruction has completed. For undefined opcodes, the behavior of the CSP is defined as a No Operation Strobe Command (SNOP). The Immediate Strobe instructions (ISxxx) are not used in a program. When these instructions are written to the RFST register, CC2430 Data Sheet (rev. 2.1) SWRS036F Page 178 of 211 Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor Table 46: Instruction Set Summary Opcode Bit number 7 SKIP C,S 0 WAIT W 1 0 0 WEVENT 1 0 1 1 1 0 0 0 Wait until MAC Timer value is greater than or equal to compare value in T2CMP WAITX 1 0 1 1 1 0 1 1 Wait for CSPX number of backoffs. When CSPX is zero there is no wait. LABEL 1 0 1 1 1 0 1 0 Label next instruction as loop start RPT 1 0 1 0 N INT 1 0 1 1 1 0 0 1 Assert interrupt INCY 1 0 1 1 1 1 0 1 Increment CSPY INCMAXY 1 0 1 1 0 DECY 1 0 1 1 1 1 1 0 Decrement CSPY DECZ 1 0 1 1 1 1 1 1 Decrement CSPZ RANDXY 1 0 1 1 1 1 0 0 Load CSPX with CSPY bit random value. Sxxx 1 1 0 STRB Command strobe instructions ISxxx 1 1 1 STRB Immediate strobe instructions 11 6 5 4 S 3 2 1 N 0 Description 11 Mnemonic Skip S instructions when condition (C xor N) is true. See Table 48 for C conditional codes C Wait for W number of MAC Timer overflows. If W is zero, wait for 32 MAC Timer overflows W Repeat from start of loop if condition (C xor N) is true. See Table 48 for C conditional codes C Increment CSPY not greater than M M Refer to Table 47 for full description of each instruction 14.34.8 Instruction Set Definition There are 14 basic instruction types. Furthermore the Command Strobe and Immediate Strobe instructions can each be divided into eleven sub-instructions giving an effective number of 34 different instructions. Table 47 describe each instruction. Note: the following definitions are used in this section PC X Y Z T ! > < | = = = = = = = = = CC2430 Data Sheet (rev. 2.1) SWRS036F CSP program counter RF register CSPX RF register CSPY RF register CSPZ RF register CSPT not greater than less than bit wise or Page 179 of 211 Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor Table 47: CSMA/CA strobe processor instruction details NMONIC OPCODE Function Operation Description DECZ 0xBF Decrement Z Z := Z - 1 The Z register is decremented by 1. Original values of 0x00 will underflow to 0x0FF. DECY 0xBE Decrement Y Y := Y - 1 The Y register is decremented by 1. Original values of 0x00 will underflow to 0x0FF. INCY 0xBD Increment Y Y := Y + 1 The Y register is incremented by 1. An original value of 0x0FF will overflow to 0x00. INCMAXY 0xB0|M12 Increment Y !> M Y := min(Y+1, M) The Y register is incremented by 1 if the result is less than M otherwise Y register is loaded with value M. An original value of Y equal 0x0FF will result in the value M. RANDXY 0xBC Load random data into X X[Y-1:0] := RNG_DOUT[Y-1:0], X[7:Y] := 0 The [Y] LSB bits of X register are loaded with random value. Note that if two RANDXY instructions are issued immediately after each other the same random value will be used in both cases. If Y equals 0 or if Y is greater than 8, then 8 LSB bits are loaded. INT 0xB9 Interrupt IRQ_CSP_INT = 1 The interrupt IRQ_CSP_INT is asserted when this instruction is executed. WAITX 0xBB Wait for X MAC Timer overflows X := X-1 when MAC timer overflow true PC := PC while number of MAC timer compare true < X PC := PC + 1 when number of MAC timer compare true = X Wait until MAC Timer overflows the numbers of times equal to register X. The contents of register X is decremented each time a MAC Timer overflow is detected. Program execution continues with the next instruction and the interrupt flag IRQ_CSP_WT is asserted when the wait condition is true. If register X is zero when this instruction starts executing, there is no wait. WAIT W 0x80|W12 Wait for W MAC Timer overflows PC := PC while number of MAC timer compare true < W PC := PC + 1 when number of MAC timer compare true = W Wait until MAC Timer overflows number of times equal to value W. If W=0 the instruction will wait for 32 overflows. Program execution continues with the next instruction and the interrupt flag IRQ_CSP_WT is asserted when the wait condition is true. WEVENT 0xB8 PC := PC while MAC timer compare false Wait MAC Timer value is greater than or equal to the compare value in T2CMP. Wait until MAC Timer compare PC := PC + 1 when MAC timer compare Program execution continues with the next instruction when the wait condition is true. true LABEL 0xBA Set loop label LABEL:= PC+1 Sets next instruction as start of loop. If the current instruction is the last instruction in the instruction memory then the current PC is set as start of loop. Only one level of loops is supported. RPT C 0xA0|N|C12 Conditional repeat PC (C PC (C If condition C is true then jump to instruction defined by last LABEL instruction, i.e. jump to start of loop. If the condition is false or if a LABEL instruction has not been executed, then execution will continue from next instruction. The condition C may be negated by setting N=1 and is described in Table 48. SKIP S,C 0x00|S|N|C12 Conditional skip instruction PC := PC + S + 1 when (C xor N) true else PC := PC + 1 12 := LABEL when xor N) true := PC + 1 when xor N) false or LABEL not set If condition C is true then skip S instructions. The condition C may be negated (N=1) and is described in Table 48 (note same conditions as RPT C instruction). Setting S=0, will cause a wait at current instruction until (C xor N) = true Refer to Table 46 for OPCODE CC2430 Data Sheet (rev. 2.1) SWRS036F Page 180 of 211 Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor NMONIC OPCODE Function Operation Description STOP 0xDF Stop program execution Stop exec, PC:=0, write pointer:=0 The SSTOP instruction stops the CSP program execution. The instruction memory is cleared, any loop start location set by the LABEL instruction is invalidated and the IRQ_CSP_STOP interrupt flag is asserted. SNOP 0xC0 No Operation PC := PC + 1 Operation continues at the next instruction. STXCALN 0xC1 Enable and calibrate freq. synth. for TX STCALN The STXCALN instruction enables and calibrate frequency synthesizer for TX. The instruction waits for the radio to acknowledge the command before executing the next instruction. NOTE: Only for test purposes (see section 14.20). SRXON 0xC2 Enable and calibrate freq. synth. for RX SRXON The SRXON instruction asserts the output FFCTL_SRXON_STRB to enable and calibrate frequency synthesizer for RX. The instruction waits for the radio to acknowledge the command before executing the next instruction. STXON 0xC3 Enable TX after calibration STXON The STXON instruction enables TX after calibration. The instruction waits for the radio to acknowledge the command before executing the next instruction. STXONCCA 0xC4 Enable calibration and TX if STXONCCA CCA indicated a clear channel STXONCCA instruction enables TX after calibration if CCA indicates a clear channel. The instruction waits for the radio to acknowledge the command before executing the next instruction. Note that this strobe should only be used when FSMTC1.RX2RX_TIME_OFF is set to 1, if not time from strobe until transmit may not be 192 µs. SROFF 0xC5 Disable RX/TX and freq. synth. SRFOFF The SRFOFF instruction asserts disables RX/TX and the frequency synthesizer. The instruction waits for the radio to acknowledge the command before executing the next instruction. SFLUSHRX 0xC6 Flush RXFIFO buffer and reset SFLUSHRX demodulator The SFLUSHRX instruction flushes the RXFIFO buffer and resets the demodulator. The instruction waits for the radio to acknowledge the command before executing the next instruction. SFLUSHTX 0xC7 Flush TXFIFO buffer The SFLUSHTX instruction flushes the TXFIFO buffer. The instruction waits for the radio to acknowledge the command before executing the next instruction. SACK 0xC8 Send acknowledge frame with SACK pending field cleared The SACK instruction sends an acknowledge frame. The instruction waits for the radio to acknowledge the command before executing the next instruction. SACPEND 0xC9 Send acknowledge frame when pending field set SACKPEND The SACKPEND instruction sends an acknowledge frame with pending field set. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISSTOP 0xFF Stop program execution Stop execution ISSTOP instruction stops the CSP program execution. The instruction memory is cleared, any loop start location set be the LABEL instruction is invalidated and the IRQ_CSP_STOP interrupt flag is asserted. ISSTART 0xFE Start program execution PC := 0, start execution The ISSTART instruction starts the CSP program execution from first instruction written to instruction memory. ISTXCALN 0xE1 Enable and calibrate freq. synth. for TX STXCALN ISTXCALN instruction immediately enables and calibrates frequency synthesizer for TX. The instruction waits for the radio to acknowledge the command before executing the next instruction. SFLUSHTX CC2430 Data Sheet (rev. 2.1) SWRS036F Page 181 of 211 Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor NMONIC OPCODE Function Operation Description ISRXON 0xE2 Enable and calibrate freq. synth. for RX SRXON The ISRXON instruction immediately enables and calibrates frequency synthesizer for RX. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISTXON 0xE3 Enable TX after calibration STXON_STRB The ISTXON instruction immediately enables TX after calibration. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISTXONCCA 0xE4 Enable calibration and TX if STXONCCA CCA indicates a clear channel The ISTXONCCA instruction immediately enables TX after calibration if CCA indicates a clear channel. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISRFOFF 0xE5 Disable RX/TX and freq. synth. FFCTL_SRFOFF_STRB = 1 The ISRFOFF instruction immediately disables RX/TX and frequency synthesizer. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISFLUSHRX 0xE6 Flush RXFIFO buffer and reset SFLUSHRX demodulator ISFLUSHRX instruction flushes the RXFIFO buffer and resets the demodulator. The instruction waits for the radio to acknowledge the command before executing the next instruction. Note that for compete flush the command must be run twice. ISFLUSHTX 0xE7 Flush TXFIFO buffer ISFLUSHTX instruction immediately flushes the TXFIFO buffer. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISACK 0xE8 Send acknowledge frame with SACK pending field cleared The ISACK instruction immediately sends an acknowledge frame. The instruction waits for the radio to receive and interpret the command before executing the next instruction. ISACKPEND 0xE9 Send acknowledge frame when pending field set The ISACKPEND instruction immediately sends an acknowledge frame with pending field set. The instruction waits for the radio to receive and interpret the command before executing the next instruction. SFLUSHTX SACPEND CC2430 Data Sheet (rev. 2.1) SWRS036F Page 182 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers Table 48: Condition code for C Condition code C Description Function 000 CCA is true CCA = 1 001 Transmiting or Receiving packet SFD = 1 010 CPU control true CSPCTRL.CPU_CTRL=1 011 End of instruction memory PC = 23 100 Register X=0 X=0 101 Register Y=0 Y=0 110 Register Z=0 Z=0 111 Not used - 14.35 Radio Registers This section describes all RF registers used for control and status for the radio. The RF registers reside in XDATA memory space. Table 49 gives an overview of register addresses while the remaining tables in this section describe each register. Refer also to section 3 for Register conventions. Table 49 : Overview of RF registers XDATA Address Register name Description 0xDF000xDF01 - Reserved 0xDF02 MDMCTRL0H Modem Control 0, high 0xDF03 MDMCTRL0L Modem Control 0, low 0xDF04 MDMCTRL1H Modem Control 1, high 0xDF05 MDMCTRL1L Modem Control 1, low 0xDF06 RSSIH RSSI and CCA Status and Control, high 0xDF07 RSSIL RSSI and CCA Status and Control, low 0xDF08 SYNCWORDH Synchronisation Word Control, high 0xDF09 SYNCWORDL Synchronisation Word Control, low 0xDF0A TXCTRLH Transmit Control, high 0xDF0B TXCTRLL Transmit Control, low 0xDF0C RXCTRL0H Receive Control 0, high 0xDF0D RXCTRL0L Receive Control 0, low 0xDF0E RXCTRL1H Receive Control 1, high 0xDF0F RXCTRL1L Receive Control 1, low 0xDF10 FSCTRLH Frequency Synthesizer Control and Status, high 0xDF11 FSCTRLL Frequency Synthesizer Control and Status, low 0xDF12 CSPX CSP X Data 0xDF13 CSPY CSP Y Data 0xDF14 CSPZ CSP Z Data 0xDF15 CSPCTRL CSP Control 0xDF16 CSPT CSP T Data 0xDF17 RFPWR RF Power Control CC2430 Data Sheet (rev. 2.1) SWRS036F Page 183 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers XDATA Address Register name Description 0xDF20 FSMTCH Finite State Machine Time Constants, high 0xDF21 FSMTCL Finite State Machine Time Constants, low 0xDF22 MANANDH Manual AND Override, high 0xDF23 MANANDL Manual AND Override, low 0xDF24 MANORH Manual OR Override, high 0xDF25 MANORL Manual OR Override, low 0xDF26 AGCCTRLH AGC Control, high 0xDF27 AGCCTRLL AGC Control, low 0xDF280xDF38 - Reserved 0xDF39 FSMSTATE Finite State Machine State Status 0xDF3A ADCTSTH ADC Test, high 0xDF3B ADCTSTL ADC Test, low 0xDF3C DACTSTH DAC Test, high 0xDF3D DACTSTL DAC Test, low 0xDF3E - Reserved 0xDF3F - Reserved 0xDF40 - Reserved 0xDF41 - Reserved 0xDF43 IEEE_ADDR0 IEEE Address 0 (LSB) 0xDF44 IEEE_ADDR1 IEEE Address 1 0xDF45 IEEE_ADDR2 IEEE Address 2 0xDF46 IEEE_ADDR3 IEEE Address 3 0xDF47 IEEE_ADDR4 IEEE Address 4 0xDF48 IEEE_ADDR5 IEEE Address 5 0xDF49 IEEE_ADDR6 IEEE Address 6 0xDF4A IEEE_ADDR7 IEEE Address 7 (MSB) 0xDF4B PANIDH PAN Identifier, high 0xDF4C PANIDL PAN Identifier, low 0xDF4D SHORTADDRH Short Address, high 0xDF4E SHORTADDRL Short Address, low 0xDF4F IOCFG0 I/O Configuration 0 0xDF50 IOCFG1 I/O Configuration 1 0xDF51 IOCFG2 I/O Configuration 2 0xDF52 IOCFG3 I/O Configuration 3 0xDF53 RXFIFOCNT RX FIFO Count CC2430 Data Sheet (rev. 2.1) SWRS036F Page 184 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers XDATA Address Register name Description 0xDF54 FSMTC1 Finite State Machine Control 0xDF550xDF5F - Reserved 0xDF60 CHVER Chip Version 0xDF61 CHIPID Chip Identification 0xDF62 RFSTATUS RF Status 0xDF63 - Reserved 0xDF64 IRQSRC RF Interrupt Source The RF registers shown in Table 50 are reserved for test purposes. The values for these registers should be obtained from SmartRF® Studio (see section 16 on page 202) and should not be changed. Table 50 : Overview of RF test registers XDATA Address Register name Reset value 0xDF28 AGCTST0H 0x36 0xDF29 AGCTST0L 0x49 0xDF2A AGCTST1H 0x08 0xDF2B AGCTST1L 0x54 0xDF2C AGCTST2H 0x09 0xDF2D AGCTST2L 0x0A 0xDF2E FSTST0H 0x10 0xDF2F FSTST0L 0x00 0xDF30 FSTST1H 0x40 0xDF31 FSTST1L 0x32 0xDF32 FSTST2H 0x20 0xDF33 FSTST2L 0x00 0xDF34 FSTST3H 0x92 0xDF35 FSTST3L 0xDD 0xDF37 RXBPFTSTH 0x00 0xDF38 RXBPFTSTL 0x00 0xDF3F TOPTST 0x10 0xDF40 RESERVEDH 0x00 0xDF41 RESERVEDL 0x00 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 185 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers MDMCTRL0H (0xDF02) Bit Name Reset R/W Function 7:6 FRAMET_FILT 00 R/W These bits are used to perform special operations on the frame type field of a received packet. These operations do not influence the packet that is written to the RXFIFO. 00 : Leave frame type as it is. 01 : Invert MSB of frame type. 10 : Set MSB of frame type to 0. 11 : Set MSB of frame type to 1. For IEEE 802.15.4 compliant operation these bits should always be set to 00. 5 RESERVED_FRAME_MODE 0 R/W Mode for accepting reserved IEEE 802.15.4 frame types when address recognition is enabled (MDMCTRL0.ADDR_DECODE = 1). 0 : Reserved frame types (100, 101, 110, 111) are rejected by address recognition. 1 : Reserved frame types (100, 101, 110, 111) are always accepted by address recognition. No further address decoding is done. When address recognition is disabled (MDMCTRL0.ADDR_DECODE = 0), all frames are received and RESERVED_FRAME_MODE is don’t care. For IEEE 802.15.4 compliant operation these bits should always be set to 00. 4 PAN_COORDINATOR 0 R/W PAN Coordinator enable. Used for filtering packets with no destination address, as specified in section 7.5.6.2 in 802.15.4 [1] 0 : Device is not a PAN Coordinator 1 : Device is a PAN Coordinator 3 ADDR_DECODE 1 R/W Hardware Address decode enable. 0 : Address decoding is disabled 1 : Address decoding is enabled 2:0 CCA_HYST[2:0] 010 R/W CCA Hysteresis in dB, values 0 through 7 dB CC2430 Data Sheet (rev. 2.1) SWRS036F Page 186 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers MDMCTRL0L (0xDF03) Bit Name Reset R/W Description 7:6 CCA_MODE[1:0] 11 R/W Clear Channel Assessment mode select. 00 : Reserved 01 : CCA=1 when RSSI < CCA_THR-CCA_HYST CCA=0 when RSSI >= CCA_THR 10 : CCA=1 when not receiving a packet 11 : CCA=1 when RSSI < CCA_THR-CCA_HYST and not receiving a packet CCA=0 when RSSI >= CCA_THR or receiving a packet 5 AUTOCRC 1 R/W In packet mode a CRC-16 (ITU-T) is calculated and is transmitted after the last data byte in TX. In RX CRC is calculated and checked for validity. 4 AUTOACK 0 R/W If AUTOACK is enabled, all packets accepted by address recognition with the acknowledge request flag set and a valid CRC are acknowledged 12 symbol periods after being received if MDMCTRL1H.SLOTTED_ACK = 0. Acknowledgment is at the beginning of the first backoff slot more than 12 symbol periods after the end of the received frame if the MDMCTRL1H.SLOTTED_ACK = 1 0 : AUTOACK disabled 1 : AUTOACK enabled 3:0 PREAMBLE_LENGTH[3:0] 0010 R/W The number of preamble bytes (2 zero-symbols) to be sent in TX mode prior to the SYNCWORD. The reset value of th 0010 is compliant with IEEE 802.15.4, since the 4 zero byte is included in the SYNCWORD. 0000 : 1 leading zero bytes (not recommended) 0001 : 2 leading zero bytes (not recommended) 0010 : 3 leading zero bytes (IEEE 802.15.4 compliant) 0011 : 4 leading zero bytes … 1111 : 16 leading zero bytes MDMCTRL1H (0xDF04) Bit Name Reset R/W Description 7 SLOTTED_ACK 0 R/W SLOTTED_ACK defines the timing of automatically transmitted acknowledgment frames. 0 : The acknowledgment frame is transmitted 12 symbol periods after the incoming frame. 1 : The acknowledgment frame is transmitted between 12 and 30 symbol periods after the incoming frame. The timing is defined such that there is an integer number of 20-symbol periods between the received and the transmitted SFDs. This may be used to transmit slotted acknowledgment frames in a beacon enabled network. 6 - 0 R/W Reserved 5 CORR_THR_SFD 1 R/W CORR_THR_SFD defines the level at which the CORR_THR correlation threshold is used to filter out received frames. 0 : Same filtering as CC2420, should be combined with a CORR_THR of 0x14 1 : More extensive filtering is performed, which will result in less false frame detections e.g. caused by noise. 4:0 CORR_THR[4:0] 0x10 R/W Demodulator correlator threshold value, required before SFD search. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 187 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers MDMCTRL1L (0xDF05) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5 DEMOD_AVG_MODE 0 R/W DC average filter behavior. 0 : Lock DC level to be removed after preamble match 1 : Continuously update DC average level. 4 MODULATION_MODE 0 R/W Set one of two RF modulation modes for RX / TX 0 : IEEE 802.15.4 compliant mode 1 : Reversed phase, non-IEEE compliant (could be used to set up a system which will not receive 802.15.4 packets) 3:2 TX_MODE[1:0] 00 R/W Set test modes for TX 00 : Normal operation, transmit TXFIFO 01 : Serial mode, use transmit data on serial interface, infinite transmission. 10 : TXFIFO looping ignore underflow in TXFIFO and read cyclic, infinite transmission. 11 : Send random data from CRC, infinite transmission. 1:0 RX_MODE[1:0] 00 R/W Set test mode of RX 00 : Normal operation, use RXFIFO 01 : Receive serial mode, output received data on pins. Infinite RX. 10 : RXFIFO looping ignore overflow in RXFIFO and write cyclic, infinite reception. 11 : Reserved RSSIH (0xDF06) Bit Name Reset R/W Description 7:0 CCA_THR[7:0] 0xE0 R/W Clear Channel Assessment threshold value, signed number in 2’s complement for comparison with the RSSI. The unit is 1 dB, offset is TBD [depends on the absolute gain of the RX chain, including external components and should be measured]. The CCA signal goes high when the received signal is below this value. The reset value is in the range of -70 dBm. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 188 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers RSSIL (0xDF07) Bit Name Reset R/W Description 7:0 RSSI_VAL[7:0] 0x80 R RSSI estimate on a logarithmic scale, signed number in 2’s complement. Unit is 1 dB, offset is TBD [depends on the absolute gain of the RX chain, including external components, and should be measured]. The RSSI value is averaged over 8 symbol periods. SYNCWORDH (0xDF08) Bit Name Reset R/W Description 7:0 SYNCWORD[15:8] 0xA7 R/W Synchronization word. The SYNCWORD is processed from the least significant nibble (F at reset) to the most significant nibble (A at reset). SYNCWORD is used both during modulation (where 0xF’s are replaced with 0x0’s) and during demodulation (where 0xF’s are not required for frame synchronization). In reception an implicit zero is required before the first symbol required by SYNCWORD. The reset value is compliant with IEEE 802.15.4. SYNCWORDL (0xDF09) Bit Name Reset R/W Description 7:0 SYNCWORD[7:0] 0x0F R/W Synchronization word. The SYNCWORD is processed from the least significant nibble (F at reset) to the most significant nibble (A at reset). SYNCWORD is used both during modulation (where 0xF’s are replaced with 0x0’s) and during demodulation (where 0xF’s are not required for frame synchronization). In reception an implicit zero is required before the first symbol required by SYNCWORD. The reset value is compliant with IEEE 802.15.4. TXCTRLH (0xDF0A) Bit Name Reset R/W Description 7:6 TXMIXBUF_CUR[1:0] 10 R/W TX mixer buffer bias current. 00 : 690 uA 01 : 980 uA 10 : 1.16 mA (nominal) 11 : 1.44 mA 5 TX_TURNAROUND 1 R/W Sets the wait time after STXON before transmission is started. 0 : 8 symbol periods (128 us) 1 : 12 symbol periods (192 us) 4:3 TXMIX_CAP_ARRAY[1:0] 0 R/W Selects varactor array settings in the transmit mixers. 2:1 TXMIX_CURRENT[1:0] 0 R/W Transmit mixers current: 00 : 1.72 mA 01 : 1.88 mA 10 : 2.05 mA 11 : 2.21 mA 0 PA_DIFF 1 R/W Power Amplifier (PA) output select. Selects differential or single-ended PA output. 0 : Single-ended output 1 : Differential output CC2430 Data Sheet (rev. 2.1) SWRS036F Page 189 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers TXCTRLL (0xDF0B) Bit Name Reset R/W Description 7:5 PA_CURRENT[2:0] 011 R/W Current programming of the PA 000 : -3 current adjustment 001 : -2 current adjustment 010 : -1 current adjustment 011 : Nominal setting 100 : +1 current adjustment 101 : +2 current adjustment 110 : +3 current adjustment 111 : +4 current adjustment 4:0 PA_LEVEL[4:0] 0x1F R/W Output PA level. (~0 dBm) RXCTRL0H (0xDF0C) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5:4 RXMIXBUF_CUR[1:0] 01 R/W RX mixer buffer bias current. 00 : 690 uA 01 : 980 uA (nominal) 10 : 1.16 mA 11 : 1.44 mA 3:2 HIGH_LNA_GAIN[1:0] 0 R/W Controls current in the LNA gain compensation branch in AGC High gain mode. 00 : Compensation disabled 01 : 100 µA compensation current 10 : 300 µA compensation current (Nominal) 11 : 1000 µA compensation current 1:0 MED_LNA_GAIN[1:0] 10 R/W Controls current in the LNA gain compensation branch in AGC Med gain mode. RXCTRL0L (0xDF0D) Bit Name Reset R/W Description 7:6 LOW_LNA_GAIN[1:0] 11 R/W Controls current in the LNA gain compensation branch in AGC Low gain mode 5:4 HIGH_LNA_CURRENT[1:0] 10 R/W Controls main current in the LNA in AGC High gain mode 00 : 240 µA LNA current (x2) 01 : 480 µA LNA current (x2) 10 : 640 µA LNA current (x2) 11 : 1280 µA LNA current (x2) 3:2 MED_LNA_CURRENT[1:0] 01 R/W Controls main current in the LNA in AGC Med gain mode 1:0 LOW_LNA_CURRENT[1:0] 01 R/W Controls main current in the LNA in AGC Low gain mode CC2430 Data Sheet (rev. 2.1) SWRS036F Page 190 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers RXCTRL1H (0xDF0E) Bit Name Reset R/W Description 7:6 - 0 R0 Reserved, read as 0. 5 RXBPF_LOCUR 1 R/W Controls reference bias current to RX band-pass filters: 0 : 4 uA 1 : 3 uA (Default) 4 RXBPF_MIDCUR 0 R/W Controls reference bias current to RX band-pass filters: 0 : 4 uA (Default) 1 : 3.5 uA 3 LOW_LOWGAIN 1 R/W LNA low gain mode setting in AGC low gain mode. 2 MED_LOWGAIN 0 R/W LNA low gain mode setting in AGC medium gain mode. 1 HIGH_HGM 1 R/W RX Mixers high gain mode setting in AGC high gain mode. 0 MED_HGM 0 R/W RX Mixers high gain mode setting in AGC medium gain mode. RXCTRL1L (0xDF0F) Bit Name Reset R/W Description 7:6 LNA_CAP_ARRAY[1:0] 01 R/W Selects varactor array setting in the LNA 00 : OFF 01 : 0.1 pF (x2) (Nominal) 10 : 0.2 pF (x2) 11 : 0.3 pF (x2) 5:4 RXMIX_TAIL[1:0] 01 R/W Control of the receiver mixers output current. 00 : 12 µA 01 : 16 µA (Nominal) 10 : 20 µA 11 : 24 µA 3:2 RXMIX_VCM[1:0] 01 R/W Controls VCM level in the mixer feedback loop 00 : 8 µA mixer current 01 : 12 µA mixer current (Nominal) 10 : 16 µA mixer current 11 : 20 µA mixer current 1:0 RXMIX_CURRENT[1:0] 10 R/W Controls current in the mixer 00 : 360 µA mixer current (x2) 01 : 720 µA mixer current (x2) 10 : 900 µA mixer current (x2) (Nominal) 11 : 1260 µA mixer current (x2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 191 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers FSCTRLH (0xDF10) Bit Name Reset R/W Description 7:6 LOCK_THR[1:0] 01 R/W Number of consecutive reference clock periods with successful sync windows required to indicate lock: 00 : 64 01 : 128 10 : 256 11 : 512 5 CAL_DONE 0 R Frequency synthesizer calibration done. 0 : Calibration not performed since the last time the FS was turned on. 1 : Calibration performed since the last time the FS was turned on. 4 CAL_RUNNING 0 R Calibration status, '1' when calibration in progress. 3 LOCK_LENGTH 0 R/W LOCK_WINDOW pulse width: 0: 2 CLK_PRE periods 1: 4 CLK_PRE periods 2 LOCK_STATUS 0 R PLL lock status 0 : PLL is not in lock 1 : PLL is in lock 1:0 FREQ[9:8] 01 R/W (2405 MHz) Frequency control word. Used directly in TX, in RX the LO frequency is automatically set 2 MHz below the RF frequency. 2048 + FREQ [9 : 0] ⇔ 4 = (2048 + FREQ [9 : 0]) MHz Frequency division = f RF f LO = (2048 + FREQ [9 : 0] − 2 ⋅ RXEN ) MHz FSCTRLL (0xDF11) Bit Name Reset R/W Description 7:0 FREQ[7:0] 0x65 R/W Frequency control word. Used directly in TX, in RX the LO frequency is automatically set 2 MHz below the RF frequency. (2405 MHz) 2048 + FREQ [9 : 0] ⇔ 4 = (2048 + FREQ [9 : 0]) MHz Frequency division = f RF f LO = (2048 + FREQ [9 : 0] − 2 ⋅ RXEN ) MHz CSPT (0xDF16) Bit Name Reset R/W Description 7:0 CSPT 0x00 R/W CSP T Data register. Contents is decremented each time MAC Timer overflows while CSP program is running. CSP program stops when is about to count to 0. Setting T=0xFF disables decrement function. CSPX (0xDF12) Bit Name Reset R/W Description 7:0 CSPX 0x00 R/W CSP X Data register. Used by CSP WAITX, RANDXY and conditional instructions CC2430 Data Sheet (rev. 2.1) SWRS036F Page 192 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers CSPY (0xDF13) Bit Name Reset R/W Description 7:0 CSPY 0x00 R/W CSP Y Data register. Used by CSP INCY, DECY, INCMAXY, RANDXY and conditional instructions CSPZ (0xDF14) Bit Name Reset R/W Description 7:0 CSPZ 0x00 R/W CSP Z Data register. Used by CSP DECZ and conditional instructions CSPCTRL (0xDF15) Bit Name Reset R/W Description 7:1 - 0x00 R0 Reserved, read as 0 0 CPU_CTRL 0 R/W CSP CPU control input. Used by CSP conditional instructions. RFPWR (0xDF17) Bit Name Reset R/W Description 7:5 - 0 R0 Reserved, read as 0. 4 ADI_RADIO_PD 1 R ADI_RADIO_PD is a delayed version of RREG_RADIO_PD. The delay is set by RREG_DELAY[2:0]. When ADI_RADIO_PD is 0, all analog modules in the radio are set in power down. ADI_RADIO_PD is read only. 3 RREG_RADIO_PD 1 R/W Power down of the voltage regulator to the analog part of the radio. This signal is used to enable or disable the analog radio. 0 : Power up 1 : Power down 2:0 RREG_DELAY[2:0] 100 R/W Delay value used in power-on for voltage regulator VREG_DELAY[2:0] Delay Units 000 0 µs 001 31 µs 010 63 µs 011 125 µs 100 250 µs 101 500 µs 110 1000 µs 111 2000 µs CC2430 Data Sheet (rev. 2.1) SWRS036F Page 193 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers FSMTCH (0xDF20) Bit Name Reset R/W Description 7:5 TC_RXCHAIN2RX[2:0] 011 R/W The time in 5 us steps between the time the RX chain is enabled and the demodulator and AGC is enabled. The RX chain is started when the band pass filter has been calibrated (after 6.5 symbol periods). 4:2 TC_SWITCH2TX[2:0] 110 R/W The time in advance the RXTX switch is set high, before enabling TX. Unit is µs. 1:0 TC_PAON2TX[3:2] 10 R/W The time in advance the PA is powered up before enabling TX. Unit is µs. FSMTCL (0xDF21) Bit Name Reset R/W Description 7:6 TC_PAON2TX[1:0] 10 R/W The time in advance the PA is powered up before enabling TX. Unit is µs. 5:3 TC_TXEND2SWITCH[2:0] 010 R/W The time after the last chip in the packet is sent, and the rxtx switch is disabled. Unit is µs. 2:0 TC_TXEND2PAOFF[2:0] 100 R/W The time after the last chip in the packet is sent, and the PA is set in power-down. Also the time at which the modulator is disabled. Unit is µs. MANANDH (0xDF22) Bit Name Reset R/W Description 7 VGA_RESET_N 1 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain. 6 BIAS_PD 1 R/W Reserved, read as 0 5 BALUN_CTRL 1 R/W The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch. 4 RXTX 1 R/W RXTX signal: controls whether the LO buffers (0) or PA buffers (1) should be used. 3 PRE_PD 1 R/W Powerdown of prescaler. 2 PA_N_PD 1 R/W Powerdown of PA (negative path). 1 PA_P_PD 1 R/W Powerdown of PA (positive path). When PA_N_PD=1 and PA_P_PD=1 the up conversion mixers are in powerdown. 0 DAC_LPF_PD 1 R/W Powerdown of TX DACs. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 194 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers MANANDL (0xDF23) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0 6 RXBPF_CAL_PD 1 R/W Powerdown control of complex band pass receive filter calibration oscillator. 5 CHP_PD 1 R/W Powerdown control of charge pump. 4 FS_PD 1 R/W Powerdown control of VCO, I/Q generator, LO buffers. 3 ADC_PD 1 R/W Powerdown control of the ADCs. 2 VGA_PD 1 R/W Powerdown control of the VGA. 1 RXBPF_PD 1 R/W Powerdown control of complex band pass receive filter. 0 LNAMIX_PD 1 R/W Powerdown control of LNA, down conversion mixers and front-end bias. MANORH (0xDF24) Bit Name Reset R/W Description 7 VGA_RESET_N 0 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain. 6 BIAS_PD 0 R/W Global Bias power down (1) 5 BALUN_CTRL 0 R/W The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch. 4 RXTX 0 R/W RXTX signal: controls whether the LO buffers (0) or PA buffers (1) should be used. 3 PRE_PD 0 R/W Powerdown of prescaler. 2 PA_N_PD 0 R/W Powerdown of PA (negative path). 1 PA_P_PD 0 R/W Powerdown of PA (positive path). When PA_N_PD=1 and PA_P_PD=1 the up conversion mixers are in powerdown. 0 DAC_LPF_PD 0 R/W Powerdown of TX DACs. MANORL (0xDF25) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0 6 RXBPF_CAL_PD 0 R/W Powerdown control of complex band pass receive filter calibration oscillator. 5 CHP_PD 0 R/W Powerdown control of charge pump. 4 FS_PD 0 R/W Powerdown control of VCO, I/Q generator, LO buffers. 3 ADC_PD 0 R/W Powerdown control of the ADCs. 2 VGA_PD 0 R/W Powerdown control of the VGA. 1 RXBPF_PD 0 R/W Powerdown control of complex band pass receive filter. 0 LNAMIX_PD 0 R/W Powerdown control of LNA, down conversion mixers and front-end bias. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 195 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers AGCCTRLH (0xDF26) Bit Name Reset R/W Description 7 VGA_GAIN_OE 0 R/W Use the VGA_GAIN value during RX instead of the AGC value. 6:0 VGA_GAIN[6:0] 0x7F R/W When written, VGA manual gain override value; when read, the currently used VGA gain setting. AGCCTRLL (0xDF27) Bit Name Reset R/W Description 7:4 - 0 R0 Reserved, read as 0. 3:2 LNAMIX_GAINMODE_O [1:0] 00 R/W LNA / Mixer Gain mode override setting LNAMIX_GAINMODE[1:0] 00 R Status bit, defining the currently selected gain mode selected by the AGC or overridden by the LNAMIX_GAINMODE_O setting. Note that this value is updated by HW and may have changed between reset and when read. 1:0 00 : Gain mode is set by AGC algorithm 01 : Gain mode is always low-gain 10 : Gain mode is always med-gain 11 : Gain mode is always high-gain FSMSTATE (0xDF39) Bit Name Reset R/W Description 7:6 - 0 R0 Reserved, read as 0. 5:0 FSM_FFCTRL_STATE[5:0 ] - R Gives the current state of the FIFO and Frame Control (FFCTRL) finite state machine. ADCTSTH (0xDF3A) Bit Name Reset R/W Function 7 ADC_CLOCK_DISABLE 0 R/W ADC Clock Disable 0 : Clock enabled when ADC enabled 1 : Clock disabled, even if ADC is enabled 6:0 ADC_I[6:0] - R Returns the current ADC I-branch value. ADCTSTL (0xDF3B) Bit Name Reset R/W Function 7 - 0 R0 Reserved, read as 0. 6:0 ADC_Q[6:0] - R Returns the current ADC Q-branch value. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 196 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers DACTSTH (0xDF3C) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6:4 DAC_SRC[2:0] 000 R/W The TX DACs data source is selected by DAC_SRC according to: 000 : Normal operation (from modulator). 001 : The DAC_I_O and DAC_Q_O override values below.010 : From ADC, most significant bits 011 : I/Q after digital down mix and channel filtering. 100 : Full-spectrum White Noise (from CRC) 101 : From ADC, least significant bits 110 : RSSI / Cordic Magnitude Output 111 : HSSD module. This feature will often require the DACs to be manually turned on in MANOVR and PAMTST.ATESTMOD_MODE=4. 3:0 DAC_I_O[5:2] 000 R/W I-branch DAC override value. DACTSTL (0xDF3D) Bit Name Reset R/W Description 7:6 DAC_I_O[1:0] 00 R/W I-branch DAC override value. 5:0 DAC_Q_O[5:0] 0x00 R/W Q-branch DAC override value. IEEE_ADDR0 (0xDF43) Bit Name Reset R/W Description 7:0 IEEE_ADDR0[7:0] 0x00 R/W IEEE ADDR byte 0 (LSB) IEEE_ADDR1 (0xDF44) Bit Name Reset R/W Description 7:0 IEEE_ADDR1[7:0] 0x00 R/W IEEE ADDR byte 1 IEEE_ADDR2 (0xDF45) Bit Name Reset R/W Description 7:0 IEEE_ADDR2[7:0] 0x00 R/W IEEE ADDR byte 2 IEEE_ADDR3 (0xDF46) Bit Name Reset R/W Description 7:0 IEEE_ADDR3[7:0] 0x00 R/W IEEE ADDR byte 3 IEEE_ADDR4 (0xDF47) Bit Name Reset R/W Description 7:0 IEEE_ADDR4[7:0] 0x00 R/W IEEE ADDR byte 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 197 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers IEEE_ADDR5 (0xDF48) Bit Name Reset R/W Description 7:0 IEEE_ADDR5[7:0] 0x00 R/W IEEE ADDR byte 5 IEEE_ADDR6 (0xDF49) Bit Name Reset R/W Description 7:0 IEEE_ADDR6[7:0] 0x00 R/W IEEE ADDR byte 6 IEEE_ADDR7 (0xDF4A) Bit Name Reset R/W Description 7:0 IEEE_ADDR7[7:0] 0x00 R/W IEEE ADDR byte 7 (MSB) PANIDH (0xDF4B) Bit Name Reset R/W Description 7:0 PANIDH[7:0] 0x00 R/W PAN identifier high byte PANIDL (0xDF4C) Bit Name Reset R/W Description 7:0 PANIDL[7:0] 0x00 R/W PAN identifier low byte SHORTADDRH (0xDF4D) Bit Name Reset R/W Description 7:0 SHORTADDRH[7:0] 0x00 R/W Short address high byte SHORTADDRL (0xDF4E) Bit Name Reset R/W Description 7:0 SHORTADDRL[7:0] 0x00 R/W Short address low byte IOCFG0 (0xDF4F) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6:0 FIFOP_THR[6:0] 0x40 R/W Sets the number of bytes in RXFIFO that is required for FIFOP to go high. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 198 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers IOCFG1 (0xDF50) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6 OE_CCA 0 R/W CCA is output on P1.7 when this bit is 1 5 IO_CCA_POL 0 R/W Polarity of the IO_CCA signal. This bit is xor’ed with the internal CCA signal. 4:0 IO_CCA_SEL 00000 R/W Multiplexer setting for the CCA signal. Must be 0x00 in order to output the CCA status. IOCFG2 (0xDF51) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6 OE_SFD 0 R/W SFD is output on P1.6 when this bit is 1 5 IO_SFD_POL 0 R/W Polarity of the IO_SFD signal. This bit is xor’ed with the internal SFD signal. 4:0 IO_SFD_SEL 00000 R/W Multiplexer setting for the SFD signal. Must be 0x00 in order to output the SFD status IOCFG3 (0xDF52) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5:4 HSSD_SRC 00 R/W Configures the HSSD interface. Only the first 4 settings (compared to CC2420) are used. 00 : Off 01 : Output AGC status (gain setting/peak detector status/accumulator value) 10 : Output ADC I and Q values 11 : Output I/Q after digital down mix and channel filtering 3 OE_FIFOP 0 R/W FIFOP is output on P1.5 when this bit is 1. 2 IO_FIFOP_POL 0 R/W Polarity of the IO_FIFOP signal. This bit is xor’ed with the internal FIFOP signal 1 OE_FIFO 0 R/W FIFO is output on P1.4 when this bit is 1 0 IO_FIFO_POL 0 R/W Polarity of the IO_FIFO signal. This bit is xor’ed with the internal FIFO signal RXFIFOCNT (0xDF53) Bit Name Reset R/W Description 7:0 RXFIFOCNT[7:0] 0x00 R Number of bytes in the RX FIFO CC2430 Data Sheet (rev. 2.1) SWRS036F Page 199 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers FSMTC1 (0xDF54) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5 ABORTRX_ON_SRXON 1 R/W Abort RX when SRXON strobe is issued 0 : Packet reception is not aborted when SRXON is issued 1 : Packet reception is aborted when SRXON is issued 4 RX_INTERRUPTED 0 R RX interrupted by strobe command This bit is cleared when the next strobe is detected. 0 : Strobe command detected 1 : Packet reception was interrupted by strobe command 3 AUTO_TX2RX_OFF 0 R/W Automatically go to RX after TX. Applies to both data packets and ACK packets. 0 : Automatic RX after TX 1 : No automatic RX after TX 2 RX2RX_TIME_OFF 0 R/W Turns off the 12 symbol timeout after packet reception has ended. Active high. 1 PENDING_OR 0 R/W This bit is OR’ed with the pending bit from FFCTRL before it goes to the modulator. 0 ACCEPT_ACKPKT 1 R/W Accept ACK packet control. 0 : Reject all ACK packets 1 : ACK packets are received CHVER (0xDF60) Bit Name Reset R/W Description 7:0 VERSION[7:0] 0x03 R Chip revision number. The relationship between the value in VERSION[7:0] and the die revision is as follows: 0x03 : Die revision D The current number in VERSION[7:0] may not be consistent with past or future die revisions of this product CHIPID (0xDF61) Bit Name Reset R/W Description 7:0 CHIPID[7:0] 0x85 R Chip identification number. Always read as 0x85. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 200 of 211 Not Recommended for New Designs CC2430 Radio : Radio Registers RFSTATUS (0xDF62) Bit Name Reset R/W Description 7:5 - 000 R0 Reserved, read as 0. 4 TX_ACTIVE 0 R TX active indicates transmission in progress 0 : TX inactive 1 : TX active 3 FIFO 0 R RXFIFO data available 0 : No data available in RXFIFO 1 : One or more bytes available in RXFIFO 2 FIFOP 0 R RXFIFO threshold flag 0 : Number of bytes in RXFIFO is less or equal threshold set by IOCFG0.FIFOP_THR 1 : Number of bytes in RXFIFO is greater than threshold set by IOCFG0.FIFOP_THR Note that if frame filtering/address recognition is enabled this bit is set only when the frame has passed filtering. This bit is also set when a complete frame has been received. 1 SFD 0 R Start of Frame Delimiter status 0 : SFD inactive 1 : SFD active 0 CCA R Clear Channel Assessment IRQSRC (0xDF64) Bit Name Reset R/W Description 7:1 - 0000000 R0 Reserved, read as 0. 0 TXACK 0 R/W TX Acknowledge interrupt enable. 0 : RFIF interrupt is not set for acknowledge frames 1 : RFIF interrupt is set for acknowledge frames CC2430 Data Sheet (rev. 2.1) SWRS036F Page 201 of 211 Not Recommended for New Designs CC2430 15 Voltage Regulators The CC2430 includes two low drop-out voltage regulators. These are used to provide a 1.8 V power supply to the CC2430 analog and digital power supplies. Note: It is recommended that the voltage regulators are not used to provide power to external circuits. This is because of limited power sourcing capability and due to noise considerations. External circuitry can be powered if they can be used when internal power consumption is low and can be set I PD mode when internal power consumption I high. The analog voltage regulator input pin AVDD_RREG is to be connected to the unregulated 2.0 to 3.6 V power supply. The regulated 1.8 V voltage output to the analog parts, is available on the RREG_OUT pin. The digital regulator input pin AVDD_DREG is also to be connected to the unregulated 2.0 to 3.6 V power supply. The output of the digital regulator is connected internally within the CC2430 to the digital power supply. The voltage regulators require external components as described in section 10 on page 27. 15.1 Voltage Regulators Power-on The analog voltage regulator is disabled by setting the RF register bit RFPWR.RREG_RADIO_PD to 1. When the analog voltage regulator is powered-on by clearing the RFPWR.RREG_RADIO_PD bit, there will be a delay before the regulator is enabled. This delay is programmable through the RFPWR RF register. The interrupt flag RFIF.IRQ_RREG_PD is set when the delay has expired. The delayed power-on can also be observed by polling the RF register bit RFPWR.ADI_RADIO_PD. The digital voltage regulator is disabled when the CC2430 is placed in power modes PM2 or PM3 (see section 13.1). When the voltage regulators are disabled, register and RAM contents will be retained while the unregulated 2.0 to 3.6 power supply is present. 16 Evaluation Software Texas Instruments provides users of CC2430 with a software program, SmartRF® Studio, which may be used for radio performance and functionality evaluation. SmartRF® Studio runs on Microsoft Windows 95/98 and Microsoft Windows NT/2000/XP. SmartRF® Studio can be downloaded from the Texas Instruments web page: http://www.ti.com/lpw CC2430 Data Sheet (rev. 2.1) SWRS036F Page 202 of 211 Not Recommended for New Designs CC2430 17 Register overview ACC (0xE0) – Accumulator ................................................................................................................... 43 ADCCFG (0xF2) – ADC Input Configuration ........................................................................................83 ADCCON1 (0xB4) – ADC Control 1....................................................................................................131 ADCCON2 (0xB5) – ADC Control 2....................................................................................................132 ADCCON3 (0xB6) – ADC Control 3....................................................................................................133 ADCH (0xBB) – ADC Data High .........................................................................................................131 ADCL (0xBA) – ADC Data Low...........................................................................................................130 ADCTSTH (0xDF3A)...........................................................................................................................196 ADCTSTL (0xDF3B) ...........................................................................................................................196 AGCCTRLH (0xDF26) ........................................................................................................................196 AGCCTRLL (0xDF27) .........................................................................................................................196 B (0xF0) – B Register............................................................................................................................ 43 CHIPID (0xDF61) ................................................................................................................................200 CHVER (0xDF60)................................................................................................................................200 CLKCON (0xC6) – Clock Control.......................................................................................................... 70 CSPCTRL (0xDF15) ...........................................................................................................................193 CSPT (0xDF16)...................................................................................................................................192 CSPX (0xDF12) ..................................................................................................................................192 CSPY (0xDF13) ..................................................................................................................................193 CSPZ (0xDF14)...................................................................................................................................193 DACTSTH (0xDF3C)...........................................................................................................................197 DACTSTL (0xDF3D) ...........................................................................................................................197 DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte ........................................... 97 DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte ............................................ 97 DMAARM (0xD6) – DMA Channel Arm ................................................................................................96 DMAIRQ (0xD1) – DMA Interrupt Flag ................................................................................................. 98 DMAREQ (0xD7) – DMA Channel Start Request and Status............................................................... 97 DPH0 (0x83) – Data Pointer 0 High Byte.............................................................................................. 42 DPH1 (0x85) – Data Pointer 1 High Byte.............................................................................................. 42 DPL0 (0x82) – Data Pointer 0 Low Byte ............................................................................................... 42 DPL1 (0x84) – Data Pointer 1 Low Byte ............................................................................................... 42 DPS (0x92) – Data Pointer Select ........................................................................................................ 42 ENCCS (0xB3) – Encryption Control and Status ................................................................................140 ENCDI (0xB1) – Encryption Input Data...............................................................................................140 ENCDO (0xB2) – Encryption Output Data ..........................................................................................140 FADDRH (0xAD) – Flash Address High Byte ....................................................................................... 77 FADDRL (0xAC) – Flash Address Low Byte.........................................................................................77 FCTL (0xAE) – Flash Control................................................................................................................ 77 FSCTRLH (0xDF10)............................................................................................................................192 FSCTRLL (0xDF11) ............................................................................................................................192 FSMSTATE (0xDF39) .........................................................................................................................196 FSMTC1 (0xDF54)..............................................................................................................................200 FSMTCH (0xDF20) .............................................................................................................................194 FSMTCL (0xDF21)..............................................................................................................................194 FWDATA (0xAF) – Flash Write Data .................................................................................................... 77 FWT (0xAB) – Flash Write Timing ........................................................................................................ 77 IEEE_ADDR0 (0xDF43)......................................................................................................................197 IEEE_ADDR1 (0xDF44)......................................................................................................................197 IEEE_ADDR2 (0xDF45)......................................................................................................................197 IEEE_ADDR3 (0xDF46)......................................................................................................................197 IEEE_ADDR4 (0xDF47)......................................................................................................................197 IEEE_ADDR5 (0xDF48)......................................................................................................................198 IEEE_ADDR6 (0xDF49)......................................................................................................................198 IEEE_ADDR7 (0xDF4A) .....................................................................................................................198 IEN0 (0xA8) – Interrupt Enable 0.......................................................................................................... 52 IEN2 (0x9A) – Interrupt Enable 2.......................................................................................................... 53 IOCFG0 (0xDF4F)...............................................................................................................................198 IOCFG1 (0xDF50)...............................................................................................................................199 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 203 of 211 Not Recommended for New Designs CC2430 IOCFG2 (0xDF51)...............................................................................................................................199 IOCFG3 (0xDF52)...............................................................................................................................199 IP0 (0xA9) – Interrupt Priority 0 ............................................................................................................ 58 IP1 (0xB9) – Interrupt Priority 1 ............................................................................................................ 57 IRCON (0xC0) – Interrupt Flags 4 ........................................................................................................ 56 IRCON2 (0xE8) – Interrupt Flags 5....................................................................................................... 57 IRQSRC (0xDF64) ..............................................................................................................................201 MANANDH (0xDF22) ..........................................................................................................................194 MANANDL (0xDF23)...........................................................................................................................195 MANORH (0xDF24) ............................................................................................................................195 MANORL (0xDF25).............................................................................................................................195 MDMCTRL0H (0xDF02)......................................................................................................................186 MDMCTRL0L (0xDF03) ......................................................................................................................187 MDMCTRL1H (0xDF04)......................................................................................................................187 MDMCTRL1L (0xDF05) ......................................................................................................................188 MEMCTR (0xC7) – Memory Arbiter Control .........................................................................................41 MPAGE (0x93) – Memory Page Select ................................................................................................ 40 P0 (0x80) – Port 0 ................................................................................................................................. 82 P0DIR (0xFD) – Port 0 Direction........................................................................................................... 84 P0IFG (0x89) – Port 0 Interrupt Status Flag ......................................................................................... 86 P0INP (0x8F) – Port 0 Input Mode........................................................................................................ 85 P0SEL (0xF3) – Port 0 Function Select ................................................................................................ 83 P1 (0x90) – Port 1 ................................................................................................................................. 82 P1DIR (0xFE) – Port 1 Direction........................................................................................................... 84 P1IEN (0x8D) – Port 1 Interrupt Mask .................................................................................................. 87 P1IFG (0x8A) – Port 1 Interrupt Status Flag......................................................................................... 86 P1INP (0xF6) – Port 1 Input Mode........................................................................................................ 85 P1SEL (0xF4) – Port 1 Function Select ................................................................................................ 83 P2 (0xA0) – Port 2................................................................................................................................. 83 P2DIR (0xFF) – Port 2 Direction ........................................................................................................... 85 P2IFG (0x8B) – Port 2 Interrupt Status Flag......................................................................................... 86 P2INP (0xF7) – Port 2 Input Mode........................................................................................................ 85 P2SEL (0xF5) – Port 2 Function Select ................................................................................................ 84 PANIDH (0xDF4B) ..............................................................................................................................198 PANIDL (0xDF4C)...............................................................................................................................198 PCON (0x87) – Power Mode Control.................................................................................................... 67 PERCFG (0xF1) – Peripheral Control................................................................................................... 83 PICTL (0x8C) – Port Interrupt Control .................................................................................................. 87 PSW (0xD0) – Program Status Word ................................................................................................... 43 RFD (0xD9) – RF Data........................................................................................................................157 RFIF (0xE9) – RF Interrupt Flags .......................................................................................................156 RFIM (0x91) – RF Interrupt Mask .......................................................................................................157 RFPWR (0xDF17) ...............................................................................................................................193 RFSTATUS (0xDF62) .........................................................................................................................201 RNDH (0xBD) – Random Number Generator Data High Byte ...........................................................135 RNDL (0xBC) – Random Number Generator Data Low Byte.............................................................135 RSSIH (0xDF06) .................................................................................................................................188 RXCTRL0H (0xDF0C).........................................................................................................................190 RXCTRL0L (0xDF0D) .........................................................................................................................190 RXCTRL1H (0xDF0E).........................................................................................................................191 RXCTRL1L (0xDF0F)..........................................................................................................................191 RXFIFOCNT (0xDF53)........................................................................................................................199 S0CON (0x98) – Interrupt Flags 2 ........................................................................................................ 55 S1CON (0x9B) – Interrupt Flags 3........................................................................................................ 55 SHORTADDRH (0xDF4D) ..................................................................................................................198 SHORTADDRL (0xDF4E) ...................................................................................................................198 SLEEP (0xBE) – Sleep Mode Control................................................................................................... 67 SP (0x81) – Stack Pointer..................................................................................................................... 44 ST0 (0x95) – Sleep Timer 0 ................................................................................................................127 ST1 (0x96) – Sleep Timer 1 ................................................................................................................126 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 204 of 211 Not Recommended for New Designs CC2430 ST2 (0x97) – Sleep Timer 2 ................................................................................................................126 SYNCWORDH (0xDF08) ....................................................................................................................189 SYNCWORDL (0xDF09).....................................................................................................................189 T1CC0H (0xDB) – Timer 1 Channel 0 Capture/Compare Value High................................................107 T1CC0L (0xDA) – Timer 1 Channel 0 Capture/Compare Value Low .................................................107 T1CC1H (0xDD) – Timer 1 Channel 1 Capture/Compare Value High ...............................................108 T1CC1L (0xDC) – Timer 1 Channel 1 Capture/Compare Value Low .................................................108 T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value High ................................................109 T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value Low .................................................109 T1CCTL0 (0xE5) – Timer 1 Channel 0 Capture/Compare Control.....................................................107 T1CCTL1 (0xE6) – Timer 1 Channel 1 Capture/Compare Control.....................................................108 T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control.....................................................109 T1CNTH (0xE3) – Timer 1 Counter High............................................................................................106 T1CNTL (0xE2) – Timer 1 Counter Low .............................................................................................106 T1CTL (0xE4) – Timer 1 Control and Status ......................................................................................106 T2CAPHPH (0xA5) – Timer 2 Period High Byte .................................................................................115 T2CAPLPL (0xA4) – Timer 2 Period Low Byte ...................................................................................115 T2CMP (0x94) – Timer 2 Compare Value ..........................................................................................114 T2CNF (0xC3) – Timer 2 Configuration ..............................................................................................113 T2OF0 (0xA1) – Timer 2 Overflow Count 0 ........................................................................................115 T2OF1 (0xA2) – Timer 2 Overflow Count 1 ........................................................................................114 T2OF2 (0xA3) – Timer 2 Overflow Count 2 ........................................................................................114 T2PEROF0 (0x9C) – Timer 2 Overflow Capture/Compare 0 .............................................................116 T2PEROF1 (0x9D) – Timer 2 Overflow Capture/Compare 1 .............................................................115 T2PEROF2 (0x9E) – Timer 2 Overflow Capture/Compare 2..............................................................115 T2THD (0xA7) – Timer 2 Timer Value High Byte................................................................................114 T2TLD (0xA6) – Timer 2 Timer Value Low Byte .................................................................................114 T3CC0 (0xCD) – Timer 3 Channel 0 Compare Value ........................................................................120 T3CC1 (0xCF) – Timer 3 Channel 1 Compare Value.........................................................................121 T3CCTL0 (0xCC) – Timer 3 Channel 0 Compare Control..................................................................120 T3CCTL1 (0xCE) – Timer 3 Channel 1 Compare Control ..................................................................121 T3CNT (0xCA) – Timer 3 Counter ......................................................................................................118 T3CTL (0xCB) – Timer 3 Control ........................................................................................................119 T4CC0 (0xED) – Timer 4 Channel 0 Compare Value.........................................................................123 T4CC1 (0xEF) – Timer 4 Channel 1 Compare Value .........................................................................124 T4CCTL0 (0xEC) – Timer 4 Channel 0 Compare Control ..................................................................123 T4CCTL1 (0xEE) – Timer 4 Channel 1 Compare Control ..................................................................124 T4CNT (0xEA) – Timer 4 Counter ......................................................................................................121 T4CTL (0xEB) – Timer 4 Control ........................................................................................................122 TCON (0x88) – Interrupt Flags ............................................................................................................. 54 TIMIF (0xD8) – Timers 1/3/4 Interrupt Mask/Flag...............................................................................125 TXCTRLH (0xDF0A) ...........................................................................................................................189 TXCTRLL (0xDF0B)............................................................................................................................190 U0BAUD (0xC2) – USART 0 Baud Rate Control................................................................................149 U0CSR (0x86) – USART 0 Control and Status...................................................................................147 U0DBUF (0xC1) – USART 0 Receive/Transmit Data Buffer ..............................................................149 U0GCR (0xC5) – USART 0 Generic Control ......................................................................................149 U0UCR (0xC4) – USART 0 UART Control .........................................................................................148 U1BAUD (0xFA) – USART 1 Baud Rate Control................................................................................152 U1CSR (0xF8) – USART 1 Control and Status ..................................................................................150 U1DBUF (0xF9) – USART 1 Receive/Transmit Data Buffer...............................................................152 U1GCR (0xFC) – USART 1 Generic Control ......................................................................................152 U1UCR (0xFB) – USART 1 UART Control .........................................................................................151 WDCTL (0xC9) – Watchdog Timer Control ........................................................................................142 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 205 of 211 Not Recommended for New Designs CC2430 18 Package Description (QLP 48) All dimensions are in millimeters, angles in degrees. NOTE: The CC2430 is available in RoHS leadfree package only. Compliant with JEDEC MS-020. Table 51: Package dimensions Quad Leadless Package (QLP) QLP 48 Min Max D D1 E E1 6.9 6.65 6.9 6.65 7.0 6.75 7.0 6.75 7.1 6.85 7.1 6.85 e b L D2 E2 0.18 0.3 5.05 5.05 0.4 5.10 5.10 0.5 5.15 5.15 0.5 0.30 The overall package height is 0.85 +/- 0.05 All dimensions in mm Figure 51: Package dimensions drawing CC2430 Data Sheet (rev. 2.1) SWRS036F Page 206 of 211 Not Recommended for New Designs CC2430 18.1 Recommended PCB layout for package (QLP 48) Figure 52: Recommended PCB layout for QLP 48 package Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC2430 EM reference design 18.2 Package thermal properties Table 52: Thermal properties of QLP 48 package Thermal resistance Air velocity [m/s] 0 Rth,j-a [K/W] 25.6 18.3 Soldering information The recommendations for lead-free solder reflow in IPC/JEDEC J-STD-020C should be followed. 18.4 Tray specification Table 53: Tray specification Tray Specification Package Tray Width Tray Height Tray Length Units per Tray QLP 48 135.9mm ± 0.25mm 7.62mm ± 0.13mm 322.6mm ± 0.25mm 260 18.5 Carrier tape and reel specification Carrier tape and reel is in accordance with EIA Specification 481. CC2430 Data Sheet (rev. 2.1) SWRS036F Page 207 of 211 Not Recommended for New Designs CC2430 Table 54: Carrier tape and reel specification Tape and Reel Specification Package Tape Width Component Pitch Hole Pitch Reel Diameter Units per Reel QLP 48 16mm 12mm 4mm 13 inches 2500 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 208 of 211 Not Recommended for New Designs CC2430 19 Ordering Information Table 55: Ordering Information Ordering part number Description MOQ CC2430F128RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 260 CC2430F128RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 2,500 CC2430ZF128RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver, including royalty for using TI’s ZigBee® Software Stack, ZStack™, in an end product 260 CC2430ZF128RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver, including royalty for using TI’s ZigBee® Software Stack, ZStack™, in an end product 2,500 CC2430F64RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 64 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 260 CC2430F64RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 64 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 2,500 CC2430F32RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 32 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 260 CC2430F32RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 32 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 2,500 CC2430DK CC2430 DK Development kit. 1 ® CC2430ZDK CC2430 ZigBee DK Development kit 1 CC2430EMK CC2430 Evaluation Module Kit 1 CC2430DB CC2430 Demonstration Board 1 MOQ = Minimum Order Quantity T&R = tape and reel CC2430 Data Sheet (rev. 2.1) SWRS036F Page 209 of 211 Not Recommended for New Designs CC2430 20 General Information 20.1 Document History Table 56: Document History Revision 2.1 Date Description/Changes 2007-05-30 First data sheet for released product. Preliminary data sheets exist for engineering samples and pre-production prototype devices, but these data sheets are not complete and may be incorrect in some aspects compared with the released product. 21 Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw 22 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: TI Semiconductor KnowledgeBase Home Page: support.ti.com support.ti.com/sc/knowledgebase Product Information Centers Americas Phone: Fax: Internet/Email: +1(972) 644-5580 +1(972) 927-6377 support.ti.com/sc/pic/americas.htm Europe, Middle East and Africa Phone: Belgium (English) Finland (English) France Germany Israel (English) Italy Netherlands (English) Russia Spain Sweden (English) United Kingdom Fax: Internet: +32 (0) 27 45 54 32 +358 (0) 9 25173948 +33 (0) 1 30 70 11 64 +49 (0) 8161 80 33 11 180 949 0107 800 79 11 37 +31 (0) 546 87 95 45 +7 (0) 95 363 4824 +34 902 35 40 28 +46 (0) 8587 555 22 +44 (0) 1604 66 33 99 +49 (0) 8161 80 2045 support.ti.com/sc/pic/euro.htm CC2430 Data Sheet (rev. 2.1) SWRS036F Page 210 of 211 Not Recommended for New Designs CC2430 Japan Fax Internet/Email International Domestic International Domestic +81-3-3344-5317 0120-81-0036 support.ti.com/sc/pic/japan.htm www.tij.co.jp/pic International Domestic Australia China Hong Kon India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand +886-2-23786800 Toll-Free Number 1-800-999-084 800-820-8682 800-96-5941 +91-80-51381665 (Toll) 001-803-8861-1006 080-551-2804 1-800-80-3973 0800-446-934 1-800-765-7404 800-886-1028 0800-006800 001-800-886-0010 +886-2-2378-6808 tiasia@ti.com or ti-china@ti.com support.ti.com/sc/pic/asia.htm Asia Phone Fax Email Internet CC2430 Data Sheet (rev. 2.1) SWRS036F Page 211 of 211 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CC2430F32RTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CC2430F64RTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CC2430ZF128RTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC2430F32RTCR VQFN RTC 48 2500 350.0 350.0 43.0 CC2430F64RTCR VQFN RTC 48 2500 350.0 350.0 43.0 CC2430ZF128RTCR VQFN RTC 48 2500 350.0 350.0 43.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 TRAY Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array Max L (mm) W matrix temperature (mm) (°C) CC2430F128RTC RTC VQFNP 48 260 26 x 10 150 322.6 CC2430F32RTC RTC VQFNP 48 260 26 x 10 150 322.6 CC2430F64RTC RTC VQFNP 48 260 26 x 10 150 CC2430ZF128RTC RTC VQFNP 48 260 26 x 10 150 Pack Materials-Page 3 K0 (µm) P1 (mm) CL (mm) CW (mm) 135.9 7620 11.8 10 10.35 135.9 7620 11.8 10 10.35 322.6 135.9 7620 11.8 10 10.35 322.6 135.9 7620 11.8 10 10.35 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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