CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
Radio
• IEEE 802.15.4 compliant DSSS baseband
modem with 250 kbps data rate
• Excellent receiver sensitivity (-98 dBm)
• Programmable output power up to +5 dBm
• RF frequency range 2394-2507 MHz
• Suitable for systems targeting compliance
with worldwide radio frequency
regulations: ETSI EN 300 328 and EN
300 440 class 2 (Europe), FCC CFR47 Part
15 (US) and ARIB STD-T66 (Japan)
APPLICATIONS
• IEEE 802.15.4 systems
• ZigBee® systems
• Industrial monitoring and control
• Home and building automation
• Automatic Meter Reading
• Low-power wireless sensor networks
• Set-top boxes and remote controls
• Consumer electronics
KEY FEATURES
• State-of-the-art selectivity/co-existence
Adjacent channel rejection: 49 dB
Alternate channel rejection: 54 dB
• Excellent link budget (103dB)
400 m Line-of-sight range
• Extended temp range (-40 to +125°C)
• Wide supply range: 1.8 V – 3.8 V
• Extensive IEEE 802.15.4 MAC hardware
support to offload the microcontroller
• AES-128 security module
• CC2420 interface compatibility mode
Microcontroller Support
Digital RSSI/LQI support
Automatic clear channel assessment for
CSMA/CA
• Automatic CRC
• 768 bytes RAM for flexible buffering and
security processing
• Fully supported MAC security
• 4 wire SPI
• 6 configurable IO pins
• Interrupt generator
• Frame filtering and processing engine
• Random number generator
•
•
Low Power
RX (receiving frame, -50 dBm) 18.5 mA
TX 33.6 mA @ +5 dBm
TX 25.8 mA @ 0 dBm
0
16K+15
16K
16 bytes key
E
C bytes ciphertext
A+F+C-1
C bytes plaintext
16N+15
16 bytes counter
E+C+[NaN,3,7,15]
[0,4,8,16] bytes encrypted MIC
E+C
E+C-1
A+F
A+F-1
A
CTR
F bytes plaintext
16N+15
16N
16 bytes counter
16K+15
16K
16 bytes key
Figure 37: Advanced security instructions
26.6 CTR / UCTR
The CTR instruction will perform counter mode encryption on a configurable number C of plaintext bytes. It
outputs C ciphertext bytes. The 2 least significant bytes of the counter are incremented after each 16 byte
block of plaintext has been processed.
96
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
If the last block of plaintext is not 16 bytes long, only the required number of bits (from the MSB end) from
the encryption is used in the XOR operation.
The UCTR instruction performs counter mode decryption and is absolutely identical to the CTR instruction
because counter mode encryption and decryption are symmetrical operations.
26.7 CBC-MAC
The CBC-MAC instruction performs authentication.
Note that if M[1:0]=0 no authentication code is output. For other values of M[1:0] the number of
authentication bytes that are output is 2M[1:0]+1. If M[2]=0 the plaintext data is prefixed with the value of C
expanded to 8 bits by concatenation of a 0 at the MSB end.
26.8 CCM / UCCM
The CCM instruction uses both CBC-MAC and CTR to perform both authentication and encryption. It
supports the CCM* mode of operation as specified in IEEE 802.14.5-2006 [2].
The authentication (CBC-MAC) part calculates a Message Integrity Code (MIC) over the address range A to
A+F+C-1. The resulting MIC is encrypted with CTR mode encryption using the counter value with index 0.
The encryption (CTR) part encrypts the address range A+F to A+F+C-1 using CTR mode encryption and
counter values with index 1 and up, and thus generates C bytes of ciphertext.
The output which is the concatenation of the ciphertext and the encrypted MIC is written to memory starting
at address E.
The UCCM instruction decrypts the ciphertext in the address range A+F to A+F+C-1 using CTR mode
decryption. A MIC is then generated in the same way as for the CCM instruction, and compared to the MIC
in the input data. The result of the MIC comparison is stored in the DPUSTAT register.
26.8.1 Inputs to the CCM and UCCM Instructions
The input parameters to the CCM and UCCM instructions are described in detail in Figure 38 and Figure 39
with notes on how they related to the terminology used in the IEEE 802.15.4 specifications.
WWW.TI.COM
97
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
Figure 38: Details of the input parameters to the CCM instruction.
Figure 39: Details of the input parameters to the UCCM instruction.
26.9 Examples from IEEE802.15.4-2006
This section contains a detailed step-by-step guide to reproducing the CCM* examples given in annex C of
IEEE802.15.4-2006 [2]. The addresses that are used in these examples are chosen at random. Other
addresses can be used as well. Note that all the parameters to the instructions in the examples use hex
notation, and that section 13.3 describes the exact bit order that is required for the SPI communication.
98
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
26.9.1 Authentication Only Using CCM*
This example uses a MAC beacon frame and demonstrates how to apply authentication using the
CCM/UCCM instructions.
//Write frame data to RAM
//Start at address 0x200
MEMWR(A={02 00} D={08 d0 84 21 43 01 00 00 00 00 48 de ac 02 05 00 00 00 55 cf 00 00 51 52 53 54})
//Write key to RAM in reverse byte order
//Start at address 0x230
MEMWR(A={02 30} D={cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0})
//Write concatenation of flags, nonce and counter to RAM in reversed byte order
//Start at address 0x240
MEMWR(A={02 40} D={00 00 02 05 00 00 00 01 00 00 00 00 48 de ac 09})
//Do CCM operation with high priority
//Append the output to the frame data (by setting the output address E to 0x000)
CCM(P={01} K={23} C={00} N={24} A={200} E={000} F={1a} M={02})
The expected output from the CCM instruction is {22 3B C1 EC 84 1A B5 53}.
To verify the authentication code in the receiver, the following steps are required.
It is assumed that frame data is already present in RAM from address 0x200.
//Write key to RAM in reverse byte order
//Start at address 0x230
MEMWR(A={02 30} D={cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0})
//Write concatenation of flags, nonce and counter to RAM in reversed byte order
//Start at address 0x240
MEMWR(a={02 40} D={00 00 02 05 00 00 00 01 00 00 00 00 48 de ac 09})
//Do UCCM operation with low priority
UCCM(P={00} K={23} C={00} N={24} A={200} E={2c0} F={1a} M={02})
//Read DPUSTAT register at address 0x02C to check whether the authentication passed or not
REGRD(A={2c})
26.9.2 Encryption Only Using CCM*
This example uses a MAC data frame and demonstrates how to apply encryption/decryption of the payload
using the CCM/UCCM instructions.
//Write frame data to RAM
//Start at address 0x200
MEMWR(A={02 00} D={69 dc 84 21 43 02 00 00 00 00 48 de ac 01 00 00 00 00 48 de ac 04 05 00 00 00 61
62 63 64})
//Write key to RAM in reverse byte order
//Start at address 0x230
MEMWR(A={02 30} D={cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0})
//Write concatenation of flags, nonce and counter to RAM in reversed byte order
//Starting at address 0x240
MEMWR(A={02 40} D={00 00 04 05 00 00 00 01 00 00 00 00 48 de ac 01})
//Do CCM instruction.
CCM(P={01} K={23} C={04} N={24} A={200} E={2c0} F={1a} M={00})
The expected output from the CCM instruction is {D4 3E 02 2B}.
To decrypt the frame in the receiver, the following steps are required. It is assumed that the packed data is
already present in RAM from address 0x200.
//Write key to RAM in reverse byte order
//Start at address 0x230
MEMWR(A={02 30} D={cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0})
//Write concatenation of flags, nonce and counter to RAM in reversed byte order
//Starting at address 0x240
MEMWR(A={02 40} D={00 00 04 05 00 00 00 01 00 00 00 00 48 de ac 01})
//Decrypt the frame data and put the plaintext at address 0x2C0.
UCCM(P={01} K={23} C={04} N={24} A={200} E={2c0} F={1a} M={00})
The expected output from the CCM instruction is {61 62 63 64}.
WWW.TI.COM
99
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
26.9.3 Combination of Encryption and Authentication Using CCM*
This example uses a MAC command frame and demonstrates how to apply both encryption/decryption and
authentication using the CCM/UCCM instructions.
//Write frame data to RAM
//Start at address 0x200
MEMWR(A={02 00} D={2b dc 84 21 43 02 00 00 00 00 48 de ac ff ff 01 00 00 00 00 48 de ac 06 05 00 00
00 01 CE})
//Write key to RAM in reverse byte order
//Start at address 0x230
MEMWR(A={02 30} D={cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0})
//Write concatenation of flags, nonce and counter to RAM in reversed byte order
//Starting at address 0x240
MEMWR(A={02 40} D={00 00 06 05 00 00 00 01 00 00 00 00 48 de ac 09})
//Do CCM instruction.
//Replace the last byte in the plaintext frame with the cipehertext and encrypted MIC by setting
the output address E to 0x000.
CCM(P={01} K={23} C={01} N={24} A={200} E={000} F={1d} M={02})
The expected output from the CCM instruction is {D8 4F DE 52 90 61 F9 C6 F1}.
To decrypt the frame in the receiver, the following steps are required. It is assumed that the packed data is
already present in RAM from address 0x200.
//Write key to RAM in reverse byte order
//Start at address 0x230
MEMWR(A={02 30} D={cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0})
//Write concatenation of flags, nonce and counter to RAM in reversed byte order
//Starting at address 0x240
MEMWR(A={02 40} D={00 00 06 05 00 00 00 01 00 00 00 00 48 de ac 09})
//Decrypt the frame data and authenticate the MIC. Note that the output address E is set to 0x000.
UCCM(P={01} K={23} C={01} N={24} A={200} E={000} F={1d} M={02})
//Read DPUSTAT register at address 0x02C to check whether the authentication passed or not
REGRD(A={2c})
The expected plaintext output from the UCCM instruction is {CE}.
100
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
27 Packet Sniffing
Packet sniffing is a non-intrusive way of observing data that is either being transmitted or received by
CC2520. The packet sniffer outputs a clock and a data signal which should be sampled on the rising edges
of the clock. The two packet sniffer signals are observable as GPIO outputs. For accurate time stamping,
the SFD signal should also be output.
Because CC2520 only supports a data rate of 250kbps, the packet sniffer clock frequency is 250 kHz. The
data is output serially with the MSB of each byte first, which is opposite of the actual RF transmission, but
more convenient when processing the data. It is possible to use an SPI slave to receive the data stream.
When sniffing frames in TX mode, the data that is read from the TX FIFO by the modulator is the same data
that is output by the packet sniffer. However, if automatic CRC generation is enabled, the packet sniffer will
NOT output these 2 bytes. Instead, it will replace the CRC bytes with 0x8080. This value can never occur as
the last two bytes of a received frame (when automatic CRC checking is enabled), and thus it provides a
way for the receiver of the sniffed data to separate frames that were transmitted by the CC2520 and frames
that were received by the CC2520.
When sniffing frames in RX mode, the data that is written to the RX FIFO by the demodulator is the same
data that is output by the packet sniffer. In other words, the last two bytes are either the received CRC value
or the CRC OK/RSSI/correlation/SRCRESINDEX value that may automatically replace the CRC value,
depending on configuration settings.
Note that in order to observe the packet sniffing data on GPIO pins, the packet sniffer module must be
enabled in the MDMTEST1 register, and the correct GPIO configuration must be written to any of the GPIOn
registers.
WWW.TI.COM
101
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
28 Registers
The table below shows the memory mapping for the configuration registers in CC2520.
The FREG registers are accessible with the REGRD and REGWR instructions. Registers in address space
0x000 to 0x01F (marked with gray) are also accessible with the BSET and BCLR instructions.
The SREG registers are only accessible with the MEMRD and MEMWR instructions.
Please also refer to Figure 11: CC2520 memory map for information on the rest of the address range.
Table 20: Register overview
Address (hex)
+0x000
+0x001
+0x002
+0x003
FREG registers
0x000
FRMFILT0
FRMFILT1
SRCMATCH
0x004
SRCSHORTEN0
SRCSHORTEN1
SRCSHORTEN2
0x008
SRCEXTEN0
SRCEXTEN1
SRCEXTEN2
0x00C
FRMCTRL0
FRMCTRL1
RXENABLE0
0x010
EXCFLAG0
EXCFLAG1
EXCFLAG2
0x014
EXCMASKA0
EXCMASKA1
EXCMASKA2
0x018
EXCMASKB0
EXCMASKB1
EXCMASKB2
0x01C
EXCBINDX0
EXCBINDX1
EXCBINDY0
EXCBINDY1
0x020
GPIOCTRL0
GPIOCTRL1
GPIOCTRL2
GPIOCTRL3
0x024
GPIOCTRL4
GPIOCTRL5
GPIOPOLARITY
0x028
GPIOCTRL
DPUCON
0x02C
DPUSTAT
FREQCTRL
FREQTUNE
0x030
TXPOWER
TXCTRL
FSMSTAT0
FSMSTAT1
0x034
FIFOPCTRL
FSMCTRL
CCACTRL0
CCACTRL1
0x038
RSSI
RSSISTAT
0x03C
RXFIRST
RXFIFOCNT
TXFIFOCNT
0x040
CHIPID
VERSION
0x044
EXTCLOCK
MDMCTRL0
0x048
FREQEST
RXCTRL
0x04C
FSCTRL
FSCAL0
FSCAL1
0x050
FSCAL2
FSCAL3
AGCCTRL0
AGCCTRL1
0x054
AGCCTRL2
AGCCTRL3
ADCTEST0
ADCTEST1
0x058
ADCTEST2
MDMTEST0
MDMTEST1
0x05C
DACTEST0
DACTEST1
ATEST
DACTEST2
0x060
PTEST0
PTEST1
RESERVED
RXENABLE1
SREG registers
MDMCTRL1
0x064-0x077
0x078
0x07C
DPUBIST
ACTBIST
RAMBIST
NOTE: When accessing unmapped addresses a MEMADDR_ERROR exception will be generated. This is
valid for address space from 0x064 to 0x079 and addresses above 0x07F. Other unmapped addresses like
i.e. 0x003 will not generate a MEMADDR_ERROR.
102
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
28.1 Register Settings Update
This section contains a summary of the register settings that need to be updated from their default value.
Note that these values must be written every time CC2520 has been in LPM2 and is being brought back to
active mode.
Table 21: Registers that need update from their default value
Register name
Address
(hex)
New value
(hex)
Description
TXPOWER
030
32
Set 0 dBm output power. Use only the values listed in Table
17 in this register.
CCACTRL0
036
F8
Raises the CCA threshold from about -108dBm to about 84 dBm input level.
MDMCTRL0
046
85
Makes sync word detection less likely by requiring two zero
symbols before the sync word.
MDMCTRL1
047
14
Make it more likely to detect sync by removing the
requirement that both symbols in the SFD must have a
correlation value above the correlation threshold, and make
sync word detection less likely by raising the correlation
threshold.
RXCTRL
04A
3F
Adjust currents in RX related analog modules.
FSCTRL
04C
5A
Adjust currents in synthesizer.
FSCAL1
04F
2B
Adjust currents in VCO.
AGCCTRL1
053
11
Adjust target value for AGC control loop.
ADCTEST0
056
10
Tune ADC performance.
ADCTEST1
057
0E
Tune ADC performance.
ADCTEST2
058
03
Tune ADC performance.
28.2 Register Access Modes
The “Mode” columns in the tables below show what kind of accesses that are allowed for each bit. Table 22
shows the meaning of the different alternatives.
Table 22: Register bits access modes
Mode
Description
R
Read
W
Write
R0
Read constant zero
R1
Read constant one
W1
Only possible to write one
W0
Only possible to write zero
R*
The value read is not the actual register value, but rather the value seen by the module. This is typically used where a
configuration value may be generated automatically (through calibration, dynamic control etc.) or manually overridden with
a register value. An example structure is shown below for the AGCCTRL2 register.
WWW.TI.COM
103
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
read_data
write_data
AGCCTRL2
register
LNA_CURRENT_OE
rf_input
LNA
1
AGC
module
0
Figure 40: Example hardware structure for the R* register access mode.
104
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
28.3 Register Descriptions
The heading for each register is built up according to the following pattern:
, A , R ,
FRMFILT0, A 0x000, R 0x0D, Frame filtering
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
RESERVED
0
R/W
Reserved. Always write ‘0’
6:4
FCF_RESERVED_MASK[2:0]
000
R/W
Used for filtering on the reserved part of the frame control
field (FCF). FCF_RESERVED_MASK[2:0] is AND'ed with
FCF[9:7]. If the result is non-zero, and frame filtering is
enabled, the frame is rejected.
3:2
MAX_FRAME_VERSION[1:0]
11
R/W
Used for filtering on the frame version field of the frame
control field (FCF).
If FCF[13:12] (the frame version subfield) is higher than
MAX_FRAME_VERSION[1:0], and frame filtering is
enabled, the frame is rejected.
1
PAN_COORDINATOR
0
R/W
Should be set high when the device is a PAN coordinator,
to accept frames with no destination address (as specified
in section 7.5.6.2 in 802.15.4(b))
0 - Device is not PAN coordinator
1 - Device is PAN coordinator
0
FRAME_FILTER_EN
1
R/W
Enables frame filtering.
When this bit is set, CC2520 will perform frame filtering as
specified in section 7.5.6.2 of 802.15.4(b), third filtering
level. FRMFILT0[6:1] and FRMFILT1[7:1] together with
the local address information, define the behavior of the
filtering algorithm.
0 - Frame filtering off. (FRMFILT0[6:1], FRMFILT1[7:1]
and SRCMATCH[2:0] are don't care).
1 - Frame filtering on.
WWW.TI.COM
105
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
FRMFILT1, A 0x001, R 0x78, Frame filtering
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
ACCEPT_FT_4TO7_RESERVED
0
R/W
Defines whether reserved frames are accepted or not.
Reserved frames have frame type = (100, 101, 110, 111).
0 - Reject
1 - Accept
6
ACCEPT_FT_3_MAC_CMD
1
R/W
Defines whether MAC command frames are accepted or
not. MAC command frames have frame type = 011.
0 - Reject
1 - Accept
5
ACCEPT_FT_2_ACK
1
R/W
Defines whether acknowledgment frames are accepted or
not. Acknowledgement frames have frame type = 010.
0 - Reject
1 - Accept
4
ACCEPT_FT_1_DATA
1
R/W
Defines whether data frames are accepted or not. Data
frames have frame type = 001.
0 - Reject
1 - Accept.
3
ACCEPT_FT_0_BEACON
1
R/W
Defines whether beacon frames are accepted or not.
Beacon frames have frame type = 000
0 - Reject
1 - Accept
2:1
MODIFY_FT_FILTER[1:0]
00
R/W
These bits are used to modify the frame type field of a
received frame before frame type filtering is performed.
The modification does not influence the frame that is
written to the RX FIFO.
00 : Leave as it is
01 : Invert MSB
10 : Set MSB to ‘0’
11 : Set MSB to ‘1’
0
106
RESERVED
0
R/W
Reserved. Always write ‘0’
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
SRCMATCH, A 0x002, R 0x07, Source address matching and pending bits
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7:3
RESERVED[4:0]
0x00
R/W
Reserved. Always write ‘0’
2
PEND_DATAREQ_ONLY
1
R/W
When this bit is set, the AUTOPEND function also
requires that the received frame is a "DATA REQUEST"
MAC command frame.
1
AUTOPEND
1
R/W
Automatic acknowledgment pending flag enable.
Upon reception of a frame, the pending bit in the
(possibly) returned acknowledgment will be set
automatically, given that:
- FRMFILT0.FRAME_FILTER_EN is set.
- SRCMATCH.SRC_MATCH_EN is set.
- SRCMATCH.AUTOPEND is set.
- The received frame matches the current
SRCMATCH.PEND_DATAREQ_ONLY setting.
- The received source address matches at least one
source match table entry, which is enabled in both
SHORT_ADDR_EN and SHORT_PEND_EN or
EXT_ADDR_EN and EXT_PEND_EN.
Note: Details for SHORT_PEND_EN and
EXT_PEND_EN is found in memory map description.
0
SRC_MATCH_EN
1
R/W
Source address matching enable (This bit is “don’t care” if
FRMFILT0.FRAME_FILTER_EN = 0)
SRCSHORTEN0, A 0x004, R 0x00, Short address matching
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7:0
SHORT_ADDR_EN[7:0]
0x00
R/W
The 7:0 part of the 24-bit word SHORT_ADDR_EN that
enables / disables source address matching for each of
the 24 short address table entries.
Optional safety feature: To ensure that an entry in the
source matching table is not used while it is being
updated, set the corresponding SHORT_ADDR_EN bit to
0 while updating.
SRCSHORTEN1, A 0x005, R 0x00, Short address matching
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7:0
SHORT_ADDR_EN[15:8]
0x00
R/W
The 15:8 part of the 24-bit word SHORT_ADDR_EN
See description of SRCSHORTEN0.
SRCSHORTEN2, A 0x006, R 0x00, Short address matching
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7:0
SHORT_ADDR_EN[23:16]
0x00
R/W
The 23:16 part of the 24-bit word SHORT_ADDR_EN
See description of SRCSHORTEN0.
WWW.TI.COM
107
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
SRCEXTEN0, A 0x008, R 0x00, Extended address matching
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXT_ADDR_EN[7:0]
0x00
R/W
RO
The 7:0 part of the 24-bit word EXT_ADDR_EN that
enables / disables source address matching for each of
the 12 extended address table entries.
Write access: Extended address enable for table entry n
(0 to 7) is mapped to EXT_ADDR_EN[2n]. All
EXT_ADDR_EN[2n + 1] bits are read only and don’t care
when written to.
Read access: Extended address enable for table entry n
(0 to 7) is mapped to both EXT_ADDR_EN[2n] and
EXT_ADDR_EN[2n+1].
Optional safety feature: To ensure that an entry in the
source matching table is not used while it is being
updated, set the corresponding EXT_ADDR_EN bit to 0
while updating.
SRCEXTEN1, A 0x009, R 0x00, Extended address matching
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXT_ADDR_EN[15:8]
0x00
R/W
The 15:8 part of the 24-bit word EXT_ADDR_EN
See description of SRCEXTEN0.
SRCEXTEN2, A 0x00A, R 0x00, Extended address matching
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXT_ADDR_EN[23:16]
0x00
R/W
The 23:16 part of the 24-bit word EXT_ADDR_EN
See description of SRCEXTEN0.
108
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
FRMCTRL0, A 0x00C, R 0x40, Frame handling
Bit no.
Bit mnemonic
Reset
value
Mode
Description
7
APPEND_DATA_MODE
0
R/W
When AUTOCRC = 0:Don’t care
When AUTOCRC = 1:
0: RSSI + The crc_ok bit and the 7 bit correlation value is
appended at the end of each received frame
1: RSSI + The crc_ok bit and the 7 bit SRCRESINDEX is
appended at the end of each received frame. See Table 15 for
details.
6
AUTOCRC
1
R/W
In TX:
1: A CRC-16 (ITU-T) is generated in hardware and appended to
the transmitted frame. There is no need to write the two last bytes
to TXBUF.
0: No CRC-16 is appended to the frame. The two last bytes of the
frame must be generated manually and written to TXBUF (if not,
TX_UNDERFLOW will occur).
In RX
1: The CRC-16 is checked in hardware, and replaced in the RX
FIFO by a 16-bit status word which contains a CRC OK bit. The
status word is controllable through APPEND_DATA_MODE
0: The last two bytes of the frame (crc-16 field) are stored in the
RXFIFO. The CRC check (if any) must be done manually.
Note that this setting does not influence acknowledgment
transmission (including AUTOACK)
5
AUTOACK
0
R/W
Defines whether CC2520 automatically transmits acknowledge
frames or not. When autoack is enabled, all frames that are
accepted by address filtering, have the acknowledge request flag
set and have a valid CRC, are automatically acknowledged 12
symbol periods after being received.
0 - Autoack disabled
1 - Autoack enabled
4
ENERGY_SCAN
0
R/W
Defines whether the RSSI register contains the most recent signal
strength or the peak signal strength since the energy scan was
enabled.
0 - Most recent signal strength
1 - Peak signal strength
3:2
RX_MODE[1:0]
00
R/W
Set RX modes
00: Normal operation, use RXFIFO.
01: Reserved
10: RXFIFO looping ignore overflow in RXFIFO, infinite reception.
11: Same as normal operation except that symbol search is
disabled. Can be used for RSSI or CCA measurements when it is
undesired to find symbol.
1:0
TX_MODE[1:0]
00
R/W
Set test modes for TX
00: Normal operation, transmit TXFIFO
01: Reserved. Should not be used.
10: TXFIFO looping ignore underflow in TXFIFO and read cyclic,
infinite transmission.
11: Send pseudo random data from CRC, infinite transmission.
WWW.TI.COM
109
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
FRMCTRL1, A 0x00D, R 0x01, Frame handling
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:3
RESERVED
0x00
R0
Read as zero
2
PENDING_OR
0
R/W
Defines whether the pending data bit in outgoing acknowledgment
frames are always set to ‘1’ or controlled by the main FSM and
the address filtering.
0 - Pending data bit is controlled by main FSM and address
filtering
1 - Pending data bit is always ‘1’.
1
IGNORE_TX_UNDERF
0
R/W
Defines whether TX underflow should be ignored or not.
0 - Normal TX operation. TX underflow is detected and TX is
aborted if underflow occurs
1 - Ignore TX underflow. Transmit the number of bytes given by
the length field.
0
SET_RXENMASK_ON_TX
1
R/W
Defines whether STXON will set bit 14 in the RXENABLE register or
leave it unchanged.
0: Do not affect RXENABLE.
1: Set bit 14 in RXENABLE. Used for backwards compatibility with
CC2420.
110
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
RXENABLE0, A 0x00E, R 0x00, RX enabling
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
RXENMASK[7:0]
0x00
R/W
LSB part of the 16 bit word RXENMASK
RXENABLE enables the receiver. A non-zero value in this
register will cause the main FSM to enable the receiver when in
idle, after transmission and after acknowledgement transmission.
The following strobes can modify RXENMASK:
SRXON: Set bit 15 in RXENMASK
STXON: Set bit 14 in RXENMASK if SET_RXENMASK_ON_TX = ‘1’
SRFOFF: Clears all bits in RXENMASK
The following instructions modifies RXENMASK:
RXMASKAND : Performs a bitwise AND between RXENMASK
and the 16 bit parameter given with the instruction
RXMASKOR : Performs a bitwise OR between RXENMASK and
the 16 bit parameter given with the instruction
RXENABLE can also be written and is bit accessible. BSET and
BCLR set and clear any of the 16 bits in RXENMASK.
SRXMASKBITSET and SRXMASKBITCLR will set and clear bit
13 in RXENMASK.
There are several sources which might try to modify RXENMASK
simultaneously. To handle the case of simultaneous access to
RXENMASK from different sources the following rules apply:
- If two sources are not in conflict (they modify different parts of
the register) both their requests to modify RXENMASK will be
processed.
-Data bus has priority over all sources (BSET, BCLR, REGWR,
MEMWR)
Strobes which modify RXENMASK are prioritized as following:
1
SRFOFF
2
SXTON
3
SRXON
4
RXMASKOR
5
RXMASKAND
6
SRXMASKBITSET
7
SRXMASKBITCLR
RXENABLE1, A 0x00F, R 0x00, RX enabling
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
RXENMASK[15:8]
0x00
R/W
MSB part of the 16 bit word RXENMASK
Se description of RXENABLE0.
WWW.TI.COM
111
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
EXCFLAG0, A 0x010, R 0x00, Exception flags
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCFLAG[7:0]
0x00
R/W0
Exception pending bits for exceptions 7 to 0. Whenever an
exception occurs this bit will be set by hardware. Only software
can clear this bit. EXCFKLAG is write zero only and attempts to
write ‘1’ to any bits in EXFLAG will not result in a register change.
1: This exception has occurred and not yet cleared.
0: This exception has not yet occurred or has been cleared by
software.
Bit no
Exception
0
RF_IDLE
1
TX_FRM_DONE
2
TX_ACK_DONE
3
TX_UNDERFLOW
4
TX_OVERFLOW
5
RX_UNDERFLOW
6
RX_OVERFLOW
7
RXENABLE_ZERO
EXCFLAG1, A 0x011, R 0x00, Exception flags
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCFLAG[15:8]
0x00
R/W0
Exception pending bits for exceptions 15 to 8. See description
above.
112
Bit no
Exception
8
RX_FRM_DONE
9
RX_FRM_ACCEPTED
10
SRC_MATCH_DONE
11
SRC_MATCH_FOUND
12
FIFOP
13
SFD
14
DPU_DONE_L
15
DPU_DONE_H
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
EXCFLAG2, A 0x012, R 0x00, Exception flags
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCFLAG[23:16]
0x00
R/W0
Exception pending bits for exceptions 23 to 16. See description
above.
Bit no
Exception
16
MEMADDR_ERROR
17
USAGE_ERROR
18
OPERAND_ERROR
19
SPI_ERROR
20
RF_NO_LOCK
21
RX_FRM_ABORTED
22
RXBUFMOV_TIMEOUT
23
UNUSED
EXCMASKA0, A 0x014, R 0x00, Exception masking channel A
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCMASKA[7:0]
0x00
R/W
The 7:0 part of 24 bit word EXCMASKA
Mask exceptions for channel A. If channel A is selected as output
configuration for a pin, an exception indication will be generated on
that pin when a selected exception occurs. If the complementary
channel is selected, then an exception will be indicated when a
masked exception occurs.
For each bit:
1: Selected
0: Masked
EXCMASKA1, A 0x015, R 0x00, Exception masking channel A
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCMASKA[15:8]
0x00
R/W
The 15:8 part of 24 bit word EXCMASKA
See description of EXCMASKA0.
EXCMASKA2, A 0x016, R 0x00, Exception masking channel A
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCMASKA[23:16]
0x00
R/W
The 23:16 part of 24 bit word EXCMASKA
See description of EXCMASKA0.
WWW.TI.COM
113
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
EXCMASKB0, A 0x018, R 0x00, Exception masking channel B
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCMASKB[7:0]
0x00
R/W
The 7:0 part of 24 bit word EXCMASKB
Mask exceptions for channel B. If channel B is selected as output
configuration for a pin, an exception indication will be generated on
that pin when a selected exception occurs. If the complementary
channel is selected, then an exception will be indicated when a
masked exception occurs.
For each bit:
1: Selected
0: Masked
EXCMASKB1, A 0x019, R 0x00, Exception masking channel B
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCMASKB[15:8]
0x00
R/W
The 15:8 part of 24 bit word EXCMASKB
See description of EXCMASKB0.
EXCMASKB2, A 0x01A, R 0x00, Exception masking channel B
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
EXCMASKB[23:16]
0x00
R/W
The 23:16 part of 24 bit word EXCMASKB
See description of EXCMASKB0.
EXCBINDX0, A 0x01C, R 0x00, Exception binding channel X
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:4
RESERVED
0x0
R0
Read as zero
3:0
INSTRUCTIONX
0x0
R/W
Instruction for channel X
Instruction number to bind to exception. See documentation for
GPIO configuration for list over possible instructions that can be
bound.
EXCBINDX1, A 0x01D, R 0x12, Exception binding channel X
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
BINDX_EN
0
R/W
Defines whether exception binding for channel X is enabled or not.
0 - Binding disabled.
1 -: Binding enabled. Whenever the exception given by
EXCEPTIONX occurs the instruction given by INSTRUCTIONX is
executed.
6:5
RESERVED
00
R0
Read as zero
4:0
EXCEPTIONX
0x12
R/W
Exception for channel X
Exception number to bind to an instruction. Se table in Exception
overview for valid configurations
114
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
EXCBINDY0, A 0x01E, R 0x00, Exception binding channel Y
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:4
RESERVED
0x0
R0
Read as zero
3:0
INSTRUCTIONY
0x0
R/W
Instruction for channel Y
Instruction number to bind to exception. See documentation for
GPIO configuration for list over possible instructions that can be
bound.
EXCBINDY1, A 0x01F, R 0x12, Exception binding channel Y
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
BINDY_EN
0
R/W
Defines whether exception binding for channel Y is enabled or not.
0: Binding disabled.
1: Binding enabled. Whenever the exception given by
EXCEPTIONY occurs the instruction given by INSTRUCTIONY is
executed.
6:5
RESERVED
0
R0
Read as zero
4:0
EXCEPTIONY
0x12
R/W
Exception for channel Y
Exception number to bind to an instruction. Se table in Exception
overview for valid configurations
GPIOCTRL0, A 0x020, R 0x00, Control GPIO0
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
IN0
0
R/W
Defines whether GPIO0 is an input or output. Must be set as input
when using analog test functionality.
0 - GPIO0 is output
1 - GPIO0 is input
6:0
CTRL0
0x00
R/W
GPIO0 Configuration
When output: mux selector. See GPIO description for table over all
possible signals that can be set as output to the pin.
When input: 4 LSBs chose one of 16 instructions to be triggered
on the active edge of this GPIO input line. Values above 0x0F
have no effect.
GPIOCTRL1, A 0x021, R 0x27, Control GPIO1
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
IN1
0
R/W
Defines whether GPIO1 is an input or output. Must be set as input
when using analog test functionality.
0 - GPIO1 is output
1 - GPIO1 is input
6:0
CTRL1
0x27
R/W
GPIO1 configuration.
For details, see GPIOCTRL0 register
WWW.TI.COM
115
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
GPIOCTRL2, A 0x022, R 0x28, Control GPIO2
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
IN2
0
R/W
Defines whether GPIO2 is an input or output.
0 - GPIO2 is output
1 - GPIO2 is input
6:0
CTRL2
0x28
R/W
GPIO2 configuration
For details, see GPIOCTRL0 register
GPIOCTRL3, A 0x023, R 0x29, Control GPIO3
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
IN3
0
R/W
Defines whether GPIO3 is an input or output.
0 - GPIO3 is output
1 - GPIO3 is input
6:0
CTRL3
0x29
R/W
GPIO3 configuration.
For details, see GPIOCTRL0 register
GPIOCTRL4, A 0x024, R 0x2A, Control GPIO4
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
IN4
0
R/W
Defines whether GPIO4 is an input or output.
0 - GPIO4 is output
1 - GPIO4 is input
6:0
CTRL4
0x2A
R/W
GPIO4 configuration.
For details, see GPIOCTRL0 register
GPIOCTRL5, A 0x025, R 0x90, Control GPIO5
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
IN5
1
R/W
Defines whether GPIO5 is an input or output.
0 - GPIO5 is output
1 - GPIO5 is input
6:0
CTRL5
0x10
R/W
GPIO5 configuration
For details, see GPIOCTRL0 register
GPIOPOLARITY, A 0x026, R 0x3F, Polarity control for GPIO pins
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:6
RESERVED
00
R0
Read as zero
5:0
POLARITY
0x3F
R/W
Selects output polarity or input edge of GPIO pins.
0 - Negative polarity. Level indication is active low.
When input, falling edge is active.
1 - Positive polarity. Level indication is active high.
When input, rising edge is active.
116
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
GPIOCTRL, A 0x028, R 0x00, Other GPIO options
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
SC
0
R/W
Select extra drive strength for pads.
0 - No extra drive
1 - Extra drive
6
GPIO_ACTRL
0
R/W
5:0
GPIO_PUE
0x00
R/W
Controls analog functionality for GPIO[1:0]. When set both GPIO
pin 0 and 1 will be set to analog pads.
0 - Disable analog pads
1 - Enable analog pads
Set pull up enable individually on GPIO pads 0 through 5
Pull up is 20 kohm +/- 15%
0 - Pull up disabled
1 - Pull up enabled
DPUCON, A 0x02A, R 0x01, Timeout control for DPU
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:1
RESERVED
0x00
R0
Read as zero
0
RXTIMEOUT
1
R/W
Defines whether the RXBUFMOV instruction will time out after 32
us or immediately when the RXFIFO is empty. When the 32 us
timeout is enabled, the RXBUFMOV instruction can be run with a
higher number of bytes than the number of bytes currently stored
in RXFIFO since one byte is received every 32us.
0 - Immediate time out
1 - 32us time out
DPUSTAT, A 0x02C, R 0x00, DPU status register
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:4
RESERVED
0000
R0
Read as 0
3
AUTHSTAT_H
0
R
Authentication status, high priority Updated when a high priority
UCBCMAC or UCCM instruction completes and keep result until a
new instruction completes. Reports the result of the last run
authentication operation.
0: Authentication check failed.
1: Authentication check passed or no authentication check was
performed.
2
AUTHSTAT_L
0
R
Authentication status, low priority Updated when a low priority
UCBCMAC or UCCM instruction completes and keep result until a
new instruction completes. Reports the result of the last run
authentication operation.
0: Authentication check failed.
1: Authentication check passed or no authentication check was
performed.
1
DPUH_ACTIVE
0
R
High Priority Active
0: No high priority DPU instruction is currently active.
1: A high priority DPU instruction is currently active.
0
DPUL_ACTIVE
0
R
Low Priority Active
0: No low priority DPU instruction is currently active.
1: A low priority DPU instruction is currently active.
WWW.TI.COM
117
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
FREQCTRL, A 0x02E, R 0x0B, Controls the RF frequency
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
RESERVED
0
R0
Read as zero
6:0
FREQ[6:0]
0x0B
R/W
Frequency control word.
f RF = f LO = (2394 + FREQ [6 : 0]) MHz
(2405
MHz)
The frequency word in freq[6:0] is an offset value from 2394. The
device supports the frequency range from 2394MHz to 2507MHz.
The usable settings for freq[6:0] is consequently 0 to 113. Settings
outside this (114-127) will give a frequency of 2507MHz.
IEEE802.15.4-2006 specifies a frequency range from 2405MHz to
2480MHz with 16 channels 5 MHz apart. The channels are
numbered 11 through 26. For an IEEE802.15.4-2006 compliant
system, the only valid settings are thus
freq[6:0] = 11 + 5(channel number - 11)
FREQTUNE, A 0x02F, R 0x0F, Crystal oscillator frequency tuning
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:4
RESERVED
0x0
R0
Read as zero
3:0
XOSC32M_TUNE[3:0]
0xF
R/W
Tune crystal oscillator
The default setting “1111” will leave the XOSC not tuned.
Changing setting from default will switch in extra capacitance to
the oscillator, effectively lowering the XOSC frequency. Hence
higher setting gives higher frequency.
TXPOWER, A 0x030, R 0x06, Controls the output power
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
PA_POWER [7:0]
0x06
R/W
PA power control. Use only the values listed in in this register.
NOTE
This value should be updated to one of the values listed in Table
17 before going to TX.
FSMSTAT0, A 0x032, R 0x00, Radio status register
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
CAL_DONE
0
R
Note that this signal can not be used as a “calibration completed”
signal. It will only be high for a very brief period of time (one 32
MHz clock cycle) when the calibration module is ready to be turned
off (which does not necessarily mean that the calibration has
completed) and is thus difficult to capture with a register read over
the SPI.
This signal should not be documented in the datasheet.
Falling edges on CAL_RUNNING should be used in stead.
6
CAL_RUNNING
0
R
Frequency synth calibration status.
0 - Calibration done or not started
1 - Calibration in progress.
5:0
FSM_FFCTRL_STATE[5:0]
-
R
Gives the current state of the FIFO and Frame Control (FFCTRL)
finite state machine.
118
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
FSMSTAT1, A 0x033, R 0x00, Radio status register
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
FIFO
0
R
FIFO is high whenever there is data in the RXFIFO. Low during
RXFIFO overflow
6
FIFOP
0
R
FIFOP is set high when there are more than FIFOP_THR bytes of
data in the RXFIFO that has passed frame filtering.
FIFOP is set high when there is at least one complete frame in the
RXFIFO. FIFOP is set low again when a byte is read from the
RXFIFO and this leaves less than FIFOP_THR bytes in the FIFO.
FIFOP is high during RXFIFO overflow
5
SFD
0
R
In TX:
0: When a complete frame with SFD has been sent or no SFD has
been sent
1: SFD has been sent
In RX:
0: When a complete frame has been received or no SFD has been
received
1: SFD has been received
4
CCA
0
R
Clear channel assessment. Dependent on CCA_MODE settings.
See CCACTRL1 for details.
3
SAMPLED_CCA
0
R
Contains a sampled value of the CCA. The value is updated
whenever a SSAMPLECCA or STXONCCA strobe is issued
2
LOCK_STATUS
0
R
'1' when PLL is in lock, otherwise '0'.
1
TX_ACTIVE
0
R
Status signal, active when FFCTRL is in one of the transmit states
0
RX_ACTIVE
0
R
Status signal, active when FFCTRL is in one of the receive states
FIFOPCTRL, A 0x034, R 0x40, FIFOP threshold
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7
RESERVED
0
R0
Read as zero
6:0
FIFOP_THR[6:0]
0x40
R/W
Threshold used when generating FIFOP signal
FSMCTRL, A 0x035, R 0x01, FSM options
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:2
RESERVED
0x00
R0
Read as zero
1
SLOTTED_ACK
0
R/W
Controls timing of transmission of acknowledge frames
0: The acknowledge frame will be sent 12 symbol periods after
the end of the received frame which requests the aknowledge.
1: The acknowledge frame will be sent at the first backoff slot
boundary more than 12 symbol periods after the end of the
received frame which requests the aknowledge
0
RX2RX_TIME_OFF
1
R/W
Defines whether or not a 12 symbol time out should be used after
frame reception has ended.
0 - No time out.
1 - 12 symbol period time out.
WWW.TI.COM
119
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
CCACTRL0, A 0x036, R 0xE0, CCA threshold
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
CCA_THR[7:0]
0xE0
R/W
Clear Channel Assessment threshold value, signed 2’s
complement number for comparison with the RSSI.
The unit is 1 dB, offset is about 76dBm. The CCA signal goes
high when the received signal is below this value. The CCA signal
is available on the CCA pin and in FSMSTAT1 register.
Note that the value should never be set lower than CCA_HYST128 in order to avoid erroneous behavior of the CCA signal.
NOTE
The reset value translates to an input level of approximately -32 –
76 = -108 dBm, which is well below the sensitivity limit. That
means the CCA signal will never indicate a clear channel.
This register should be updated to 0xF8, which translates to an
input level of about -8 - 76 = -84dBm.
CCACTRL1, A 0x037, R 0x1A, Other CCA options
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:5
RESERVED
000
R0
Read as zero
4:3
CCA_MODE[1:0]
11
R/W
00 : CCA always set to ‘1’
01 : CCA = ‘1’ when RSSI < CCA_THR-CCA_HYST, CCA = ‘0’
when RSSI >= CCA_THR
10 : CCA = ‘1’ when not receiving a frame, else CCA = ‘0’
11 : CCA = ‘1’ when RSSI < CCA_THR-CCA_HYST and not
receiving a frame, CCA=0 when RSSI >= CCA_THR or receiving a
frame
2:0
CCA_HYST[2:0]
010
R/W
Sets the level of CCA hysteresis. Unsigned values given in dB.
RSSI, A 0x038, R 0x80, RSSI status register
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
RSSI_VAL[7:0]
0x80
R
RSSI estimate on a logarithmic scale, signed number on 2’s
complement.
Unit is 1 dB, offset is TBD [depends on the absolute gain of the
RX chain, including external components, and should be
measured]. The RSSI value is averaged over 8 symbol periods.
The RSSI_VALID status bit should be checked before reading
RSSI_VAL the first time.
The reset value of –128 also indicates that the RSSI value is
invalid.
RSSISTAT, A 0x039, R 0x00, RSSI valid status register
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:1
RESERVED
0000
000
R0
Read as zero
0
RSSI_VALID
0
R
RSSI value is valid. Occurs eight symbol periods after entering
RX
120
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
RXFIRST, A 0x03C, R 0x00, First byte in RXFIFO
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
DATA[7:0]
0x00
R
First byte of the RXFIFO. Note: Reading this register will not
modify the contents of the FIFO.
RXFIFOCNT, A 0x03E, R 0x00, Number of bytes in RXFIFO
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
RXFIFOCNT[7:0]
0x00
R
Number of bytes in the RXFIFO. Unsigned integer.
TXFIFOCNT, A 0x03F, R 0x00, Number of bytes in TXFIFO
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
TXFIFOCNT[7:0]
0x00
R
Number of bytes in the TXFIFO. Unsigned integer.
CHIPID, A 0x040, R 0x84, Chip ID
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
CHIPID[7:0]
0x84
R
Chip ID number. 0x84 = CC2520
VERSION, A 0x042, R 0x00, Chip version number
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
VERSION[7:0]
0x00
R
Chip version. Unsigned integer.
WWW.TI.COM
121
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
EXTCLOCK, A 0x044, R 0x20, Controls clock output
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:6
RESERVED
00
R0
Read as zero
5
EXTCLOCK_EN
1
RW
Defines whether the clock generator module for the external clock
is enabled or not. Note that a GPIO pin must be configured as
output and Clock must be selected in one of the GPIOCTRLn
registers to get the clock at the selected pin.
1 - Clock running
0 - Clock off
4:0
122
EXT_FREQ
0x00
RW
Frequency setting of external clock. Changes of frequencies are
glitch free and have 50/50 duty cycle. I.e. a change of frequency
will not have effect before a complete period of the current clock
setting is finished.
Setting
Div. factor
Frequency [MHz]
00000
32
1,00
00001
31
1,03
00010
30
1,07
00011
29
1,10
00100
28
1,14
00101
27
1,19
00110
26
1,23
00111
25
1,28
01000
24
1,33
01001
23
1,39
01010
22
1,45
01011
21
1,52
01100
20
1,60
01101
19
1,68
01110
18
1,78
01111
17
1,88
10000
16
2,00
10001
15
2,13
10010
14
2,29
10011
13
2,46
10100
12
2,67
10101
11
2,91
10110
10
3,20
10111
9
3,56
11000
8
4,00
11001
7
4,57
11010
6
5,33
11011
5
6,40
11100
4
8,00
11101
3
10,67
11110
2
16,00
11111
2
16,00
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
MDMCTRL0, A 0x046, R 0x45, Controls modem
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:6
DEM_NUM_ZEROS[1:0]
01
R/W
Sets how many zero symbols have to be detected before the sync
word when searching for sync. Note that only one is required to
have a correlation value above the correlation threshold set in
MDMCTRL1 register.
00 : reserved
01 : 1 zero symbols
10 : 2 zero symbols
11 : 3 zero symbols
NOTE
This value should be updated to “10” before attempting RX.
Testing has shown that the reset value causes too many false
frames to be received.
5
DEMOD_AVG_MODE
0
R/W
Defines the behavior or the frequency offset averaging filter.
0 - Lock average level after preamble match. Restart frequency
offset calibration when searching for the next frame.
1 - Continuously update average level.
4:1
PREAMBLE_LENGTH
[3:0]
0010
R/W
The number of preamble bytes (2 zero-symbols) to be sent in TX
mode prior to the SFD, encoded in steps of 2. The reset value of
2 is compliant with IEEE 802.15.4
0000 - 2 leading zero bytes
0001 - 3 leading zero bytes
0010 - 4 leading zero bytes
…
1111 - 17 leading zero bytes
0
TX_FILTER
1
R/W
Defines what kind of TX filter that is used. The normal TX filter is
as defined by the IEEE802.15.4 standard. Extra filtering may be
applied in order to lower the out of band emissions.
0 - Normal TX filtering
1 - Enable extra filtering
MDMCTRL1, A 0x047, R 0x2E, Controls modem
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:6
RESERVED
00
R0
Read as zero
5
CORR_THR_SFD
1
R/W
Defines requirements for SFD detection:
0 - The correlation value of one of the zero symbols of the
preamble must be above the correlation threshold.
1 - The correlation value of one zero symbol of the preamble and
both symbols in the SFD must be above the correlation threshold.
NOTE
This value should be changed to ‘0’ before attempting RX. This
will give the best trade off between good sensitivity and few false
SFD detections.
4:0
CORR_THR[4:0]
0x0E
R/W
Demodulator correlator threshold value, required before SFD
search.
Threshold value adjusts how the receiver synchronizes to data
from the radio. If threshold is set too low sync can more easily be
found on noise. If set too high the sensitivity will be reduced but
sync will not likely be found on noise.
I combination with DEM_NUM_ZEROS the system can be tuned
so sensitivity is high with less synch found on noise.
NOTE
This value should be changed to 0x14 before attempting RX.
Testing has shown that too many false frames are received if the
reset value is used.
WWW.TI.COM
123
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
FREQEST, A 0x048, R 0x00, Estimated RF frequency offset.
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:0
FREQEST[7:0]
0x00
R
Signed 2’s complement value. Contains an estimate of the
frequency offset between carrier and the receiver LO. The offset
frequency is FREQESTx7800 Hz. DEM_AVG_MODE controls when
this estimate is updated. If DEM_AVG_MODE = 0 it is updated until
sync is found. Then the frequency offset estimate is frozen until
the end of the received frame. If DEM_AVG_MODE = 1 it is updated
as long as the demodulator is enabled.
MDMTEST1, A 0x05B, R 0x08, Test register for modem
Bit
no.
Bit mnemonic
Reset
value
Mode
Description
7:4
RESERVED
0000
R0
Read as zero
3
RESERVED
1
R/W
Do not write.
2
RFC_SNIFF_EN
0
R/W
0 - Packet sniffer module disabled
1 - Packet sniffer module enabled. The received and transmitted
data can be observed on GPIO pins.
1
MODULATION_MODE
0
R/W
Set one of two RF modulation modes for RX / TX
0 - IEEE 802.15.4 compliant mode
1 - Reversed phase, non-IEEE compliant
0
124
RESERVED
0
R/W
Do not write.
WWW.TI.COM
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
The following registers in the address range 0x04A to 0x07F are for performance tuning and test purposes
and should generally not be written. The registers that require updates to give the performance described in
this datasheet are listed in Table 21: Registers that need update from their default value.
RXCTRL, A 0x04A, R 0x29, Test/tuning of RX modules
FSCTRL, A 0x04C, R 0x55, Test/tuning of synthesizer
FSCAL0, A 0x04E, R 0x24, Test/tuning of synthesizer
FSCAL1, A 0x04F, R 0x29, Test/tuning of VCO
FSCAL2, A 0x050, R 0x20, Test/tuning of VCO
FSCAL3, A 0x051, R 0x2A, Test/tuning of VCO
AGCCTRL0, A 0x052, R 0x5F, Test/tuning of AGC
AGCCTRL1, A 0x053, R 0x0E, Test/tuning of AGC
AGCCTRL2, A 0x054, R 0x00, Test/tuning of LNA
AGCCTRL3, A 0x055, R 0x2E, Test/tuning of AGC and AAF
ADCTEST0, A 0x056, R 0x66, Test/tuning of ADC
ADCTEST1, A 0x057, R 0x0A, Test/tuning of ADC
ADCTEST2, A 0x058, R 0x05, Test/tuning of ADC
MDMTEST0, A 0x05A, R 0x05, Test/tuning of modem
DACTEST0, A 0x05C, R 0x00, Test/tuning of DAC
DACTEST1, A 0x05D, R 0x00, Test/tuning of DAC
ATEST, A 0x05E, R 0x00, Controls analog test mode
DACTEST2, A 0x05F, R 0x00, Test/tuning of DAC
PTEST0, A 0x060, R 0x00, Test/tuning of power down signals
PTEST1, A 0x061, R 0x00, Test/tuning of power down signals
RESERVED, A 0x062, R 0x00, Not currently in use
DPUBIST, A 0x07A, R 0x00, Test/tuning of DPU ROM
ACTBIST, A 0x07C, R 0x00, Test/tuning of ACT ROM
RAMBIST, A 0x07E, R 0x02, Test/tuning of RAM
WWW.TI.COM
125
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
29 Datasheet Revision History
Literature
Number
Release Date
Comments
SWRS068
2007-12-20
Initial release
NOTE: Page and figure numbers refer to the respective document revision.
126
WWW.TI.COM
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CC2520RHDR
ACTIVE
VQFN
RHD
28
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
CC2520
Samples
CC2520RHDRG4
ACTIVE
VQFN
RHD
28
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
CC2520
Samples
CC2520RHDT
ACTIVE
VQFN
RHD
28
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
CC2520
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
