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CC2540T
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
CC2540T Extended Industrial Temperature Bluetooth® Smart Wireless MCU
1 Device Overview
1.1
Features
1
• True Single-Chip BLE Solution: CC2540T Can Run
Both Application and BLE Protocol Stack, Includes
Peripherals to Interface With Wide Range of
Sensors, and so forth
• Operating Temperature up to 125°C
• 6-mm × 6-mm Package
• RF
– Bluetooth® Low Energy Technology Compatible
– Excellent Link Budget (up to 97 dB), Enabling
Long-Range Applications Without External Front
End
– Accurate Digital Received Signal-Strength
Indicator (RSSI)
– Suitable for Systems Targeting Compliance With
Worldwide Radio Frequency Regulations:
• ETSI EN 300 328 and EN 300 440 Class 2
(Europe)
• FCC CFR47 Part 15 (US)
• ARIB STD-T66 (Japan)
• Layout
– Few External Components
– Reference Design Provided
– 6-mm × 6-mm VQFN40 Package
• Low Power
– Active Mode RX Down to 19.6 mA
– Active Mode TX (–6 dBm): 24 mA
– Power Mode 1 (3-μs Wake Up): 235 μA
– Power Mode 2 (Sleep Timer On): 0.9 μA
– Power Mode 3 (External Interrupts): 0.4 μA
– Wide Supply Voltage Range (2 V–3.6 V)
– Full RAM and Register Retention in All Power
Modes
• TPS62730 Compatible,
Low Power in Active Mode
– RX Down to 15.8 mA (3-V Supply)
– TX (–6 dBm): 18.6 mA (3-V Supply)
• Microcontroller
– High-Performance and Low-Power 8051
Microcontroller Core
– 256KB of In-System-Programmable Flash
– 8KB of SRAM
• Peripherals
– 12-Bit ADC With Eight Channels and
Configurable Resolution
– Integrated Ultralow-Power Comparator
– General-Purpose Timers (One 16-Bit, Two 8-Bit)
– 21 General-Purpose I/O (GPIO) Pins
(19 × 4 mA, 2 × 20 mA)
– 32-kHz Sleep Timer With Capture
– Two Powerful USARTs With Support for Several
Serial Protocols
– Full-Speed USB Interface
– IR Generation Circuitry
– Powerful Five-Channel DMA
– AES Security Coprocessor
– Battery Monitor and Temperature Sensor
– Each CC2540T Contains a Unique 48-Bit IEEE
Address
• Bluetooth v4.0 Compliant Protocol Stack for
Single-Mode BLE Solution
– Complete Power-Optimized Stack, Including
Controller and Host
• GAP: Central, Peripheral, Observer, or
Broadcaster (Including Combination Roles)
• ATT and GATT: Client and Server
• SMP: AES-128 Encryption and Decryption
• L2CAP
– Sample Applications and Profiles
• Generic Applications for GAP Central and
Peripheral Roles
• Proximity, Accelerometer, Simple Keys, and
Battery GATT Services
– Multiple Configuration Options
• Single-Chip Configuration, Allowing
Application to Run on CC2540T
• Network Processor Interface for Applications
Running on an External Microcontroller
– BTool: Windows PC Application for Evaluation,
Development, and Test
• Development Tools
– CC2540T Mini Development Kit
– SmartRF™ Software
– Supported by IAR Embedded Workbench™
Software for 8051
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC2540T
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
1.2
•
•
•
•
•
www.ti.com
Applications
2.4-GHz Bluetooth Low Energy Systems
Lighting
Motor Monitoring
Proximity Sensing
Cable Replacement
1.3
•
•
•
•
•
Power Tools
Maintenance
Wireless HMI and Remote Display
USB Dongles
Smart Phone Connectivity
Description
The CC2540T device is a cost-effective, low-power, true wireless MCU for Bluetooth low energy
applications. The CC2540T enables robust BLE master or slave nodes to be built with very low total bill-ofmaterial costs, and it can operate up to 125°C. The CC2540T combines an excellent RF transceiver with
an industry-standard enhanced 8051 MCU, in-system programmable flash memory, 8KB of RAM, and
many other powerful supporting features and peripherals. The CC2540T is suitable for systems where
very low power consumption is required. Very low-power sleep modes are available. Short transition times
between operating modes further enable low power consumption.
Combined with the Bluetooth low energy protocol stack from Texas Instruments, the CC2540TF256 forms
the market’s most flexible and cost-effective single-mode Bluetooth low energy solution.
Table 1-1. Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CC2540TF256RHAR
VQFN (40)
6.00 mm × 6.00 mm
CC2540TF256RHAT
VQFN (40)
6.00 mm × 6.00 mm
(1)
2
For more information, see Section 8, Mechanical Packaging and Orderable Information.
Device Overview
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1.4
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the CC2540T device.
XOSC_Q2
32-MHz
CRYSTAL OSC
XOSC_Q1
P2_4
32.768-kHz
CRYSTAL OSC
P2_3
P2_2
HIGHSPEED
RC-OSC
DEBUG
INTERFACE
P2_1
DCOUPL
POWER-ON RESET
BROWN OUT
CLOCK MUX
and
CALIBRATION
SFR Bus
RESET
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
WATCHDOG
TIMER
RESET_N
SLEEP TIMER
32-kHz
RC-OSC
POWER MANAGEMENT CONTROLLER
P2_0
PDATA
P1_7
P1_6
XRAM
8051 CPU
CORE
P1_5
IRAM
P1_4
SFR
MEMORY
ARBITRATOR
FLASH
FLASH
P1_3
P1_2
DMA
P1_1
UNIFIED
P1_0
IRQ CTRL
FLASH CTRL
P0_7
P0_6
ANALOG COMPARATOR
P0_5
1 KB SRAM
FIFOCTRL
Radio Arbiter
P0_4
OP-AMP
P0_2
AES
ENCRYPTION
AND
DECRYPTION
DS
ADC
AUDIO/DC
RADIO REGISTERS
Link Layer Engine
SFR Bus
P0_0
I/O CONTROLLER
P0_1
DEMODULATOR
SYNTH
P0_3
MODULATOR
USB_N
USB
USB_P
RECEIVE
USART 1
FREQUENCY
SYNTHESIZER
USART 0
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
DIGITAL
ANALOG
TIMER 4 (8-Bit)
MIXED
B0301-05
Figure 1-1. Functional Block Diagram
Device Overview
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3
CC2540T
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
Device Overview ......................................... 1
4.20
SPI AC Characteristics .............................. 15
1.1
Features .............................................. 1
4.21
Debug Interface AC Characteristics
1.2
Applications ........................................... 2
4.22
Timer Inputs AC Characteristics .................... 17
1.3
Description ............................................ 2
4.23
DC Characteristics .................................. 17
1.4
Functional Block Diagram ............................ 3
4.24
Typical Characteristics .............................. 18
2
3
Revision History ......................................... 4
Terminal Configuration and Functions .............. 5
4.25
Typical Current Savings ............................. 20
4
Specifications
4.1
1
3.1
4.2
4.3
4.4
4.5
4.6
5
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
16
Detailed Description ................................... 21
Pin Attributes ......................................... 6
5.1
Overview
............................................
Absolute Maximum Ratings ..........................
ESD Ratings ..........................................
Recommended Operating Conditions ................
Electrical Characteristics .............................
7
5.2
Functional Block Diagram ........................... 21
7
5.3
Block Descriptions................................... 22
7
6
............................................
21
Applications, Implementation, and Layout........ 25
7
6.1
Application Information .............................. 25
8
6.2
Input/Output Matching............................... 26
Thermal Resistance Characteristics for RHA
Package .............................................. 8
6.3
Crystal ............................................... 26
6.4
On-Chip 1.8-V Voltage Regulator Decoupling ...... 26
6.5
Power-Supply Decoupling and Filtering............. 26
6.6
Reference Design ................................... 27
.............................. 9
RF Receive Section .................................. 9
RF Transmit Section ................................ 10
Current Consumption With TPS62730 .............. 10
32-MHz Crystal Oscillator ........................... 11
32.768-kHz Crystal Oscillator ....................... 11
32-kHz RC Oscillator ................................ 11
16-MHz RC Oscillator ............................... 12
RSSI Characteristics ................................ 12
Frequency Synthesizer Characteristics ............. 12
Analog Temperature Sensor ........................ 12
Comparator Characteristics ......................... 12
ADC Characteristics................................. 13
Control Input AC Characteristics .................... 14
General Characteristics
4.7
................
7
8
Device and Documentation Support ............... 28
7.1
Documentation Support ............................. 28
7.2
7.3
Texas Instruments Low-Power RF Website ........ 28
Texas Instruments Low-Power RF Developer
Network.............................................. 28
7.4
Low-Power RF eNewsletter ......................... 29
7.5
Trademarks.......................................... 29
7.6
Electrostatic Discharge Caution ..................... 29
7.7
Export Control Notice
7.8
Glossary ............................................. 29
...............................
29
Mechanical Packaging and Orderable
Information .............................................. 29
8.1
Packaging Information
..............................
29
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from July 2, 2015 to November 30, 2015
•
•
•
•
4
Page
Changed several items in Features ................................................................................................ 1
Changed from Handling Ratings table to ESD Ratings table .................................................................. 7
Added MIN value for output power in the RF Transmit Section table ....................................................... 10
Added Bluetooth Low Energy Light Reference Design to the document. ................................................... 27
Revision History
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SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
3 Terminal Configuration and Functions
DVDD1
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3 / XOSC32K_Q2
P2_4 / XOSC32K_Q1
40
39
38
37
36
35
34
33
32
AVDD6
DCOUPL
The CC2540T pinout is shown in Figure 3-1, and a short description of the pins follows in Section 3.1.
31
30
R_BIAS
2
29
AVDD4
USB_N
3
28
AVDD1
DVDD_USB
4
27
AVDD2
P1_5
5
26
RF_N
P1_4
6
25
RF_P
P1_3
7
24
AVDD3
P1_2
8
23
XOSC_Q2
P1_1
9
22
12
13
14
15
16
17
18
19
P0_4
P0_3
P0_2
P0_1
P0_0
21
20
XOSC_Q1
AVDD5
RESET_N
10
11
P0_5
DVDD2
GND
Ground Pad
P0_6
USB_P
P1_0
1
P0_7
DGND_USB
P0076-05
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 3-1. CC2540T
RHA Package (VQFN)
Top View
Terminal Configuration and Functions
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CC2540T
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
3.1
www.ti.com
Pin Attributes
Table 3-1. Pin Attributes
NAME
NO.
TYPE
AVDD1
28
Power (analog)
2-V to 3.6-V analog power-supply connection
AVDD2
27
Power (analog)
2-V to 3.6-V analog power-supply connection
AVDD3
24
Power (analog)
2-V to 3.6-V analog power-supply connection
AVDD4
29
Power (analog)
2-V to 3.6-V analog power-supply connection
AVDD5
21
Power (analog)
2-V to 3.6-V analog power-supply connection
AVDD6
31
Power (analog)
2-V to 3.6-V analog power-supply connection
Power (digital)
1.8-V digital power-supply decoupling. Do not use for supplying external
circuits.
DCOUPL
40
DESCRIPTION
DGND_USB
1
Ground pin
DVDD_USB
4
Power (digital)
2-V to 3.6-V digital power-supply connection
DVDD1
39
Power (digital)
2-V to 3.6-V digital power-supply connection
DVDD2
10
Power (digital)
2-V to 3.6-V digital power-supply connection
GND
—
Ground
P0_0
19
Digital I/O
Port 0.0
P0_1
18
Digital I/O
Port 0.1
P0_2
17
Digital I/O
Port 0.2
P0_3
16
Digital I/O
Port 0.3
P0_4
15
Digital I/O
Port 0.4
P0_5
14
Digital I/O
Port 0.5
P0_6
13
Digital I/O
Port 0.6
P0_7
12
Digital I/O
Port 0.7
P1_0
11
Digital I/O
Port 1.0: 20-mA drive capability
P1_1
9
Digital I/O
Port 1.1: 20-mA drive capability
P1_2
8
Digital I/O
Port 1.2
P1_3
7
Digital I/O
Port 1.3
P1_4
6
Digital I/O
Port 1.4
P1_5
5
Digital I/O
Port 1.5
P1_6
38
Digital I/O
Port 1.6
P1_7
37
Digital I/O
Port 1.7
P2_0
36
Digital I/O
Port 2.0
P2_1
35
Digital I/O
Port 2.1
P2_2
34
Digital I/O
Port 2.2
P2_3/ XOSC32K_Q2
33
Digital I/O, Analog I/O Port 2.3/32.768 kHz XOSC
P2_4/ XOSC32K_Q1
32
Digital I/O, Analog I/O Port 2.4/32.768 kHz XOSC
RBIAS
30
Analog I/O
External precision bias resistor for reference current
RESET_N
20
Digital input
Reset, active-low
26
RF_N
25
RF_P
USB_N
3
Connect to GND
The ground pad must be connected to a solid ground plane.
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
Digital I/O
USB N
USB_P
2
Digital I/O
USB P
XOSC_Q1
22
Analog I/O
32-MHz crystal oscillator pin 1 or external-clock input
XOSC_Q2
23
Analog I/O
32-MHz crystal oscillator pin 2
6
Terminal Configuration and Functions
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SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
4 Specifications
4.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage
All supply pins must have the same voltage
Voltage on any digital pin
MIN
MAX
–0.3
3.9
V
–0.3
VDD + 0.3,
≤ 3.9
V
10
dBm
–40
125
°C
Input RF level
Tstg
(1)
(2)
Storage temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
4.2
ESD Ratings
VESD
(1)
(2)
4.3
UNIT
Electrostatic discharge (ESD)
performance
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001
Charged Device Model (CDM),
per JESD22-C101 (2)
(1)
All pins
VALUE
UNIT
±2000
V
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Operating ambient temperature range, TA
Operating supply voltage
MIN
MAX
UNIT
–40
125
°C
2
3.6
V
Specifications
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CC2540T
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
4.4
www.ti.com
Electrical Characteristics
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
Core current
consumption
Icore
Peripheral current
consumption (1)
Iperi
(1)
TEST CONDITIONS
MIN
TYP MAX UNIT
Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-MHz
crystal oscillator off; 32.768-kHz XOSC, POR, BOD and sleep timer
active; RAM and register retention
235
Power mode 2. Digital regulator off; 16-MHz RCOSC and 32-MHz
crystal oscillator off; 32.768-kHz XOSC, POR, and sleep timer active;
RAM and register retention
0.9
Power mode 3. Digital regulator off; no clocks; POR active; RAM and
register retention
0.4
Low MCU activity: 32-MHz XOSC running. No radio or peripherals. No
flash access, no RAM access.
6.7
Timer 1. Timer running, 32-MHz XOSC used
90
Timer 2. Timer running, 32-MHz XOSC used
90
Timer 3. Timer running, 32-MHz XOSC used
60
Timer 4. Timer running, 32-MHz XOSC used
70
Sleep timer, including 32.753-kHz RCOSC
0.6
ADC, when converting
1.2
µA
mA
µA
mA
Adds to core current Icore for each peripheral unit activated.
4.5
Thermal Resistance Characteristics for RHA Package
NAME
DESCRIPTION
RΘJC
Junction-to-case
RΘJB
RΘJA
°C/W (1)
(2)
AIR FLOW (m/s) (3)
16.1
0.00
Junction-to-board
5.5
0.00
Junction-to-free air
30.6
0.00
RΘJMA
Junction-to-moving air
0.2
0.00
PsiJT
Junction-to-package top
5.4
0.00
PsiJB
Junction-to-board
1.0
0.00
(1)
(2)
(3)
8
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
m/s = meters per second.
Specifications
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4.6
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
General Characteristics
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Power mode 1 → Active
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
4
µs
Power mode 2 or 3 → Active
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
120
µs
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,
with 32-MHz XOSC OFF
410
µs
With 32-MHz XOSC initially on
160
µs
150
µs
Active → TX or RX
RX/TX turnaround
RADIO PART
RF frequency range
Programmable in 2-MHz steps
Data rate and modulation format
1 Mbps, GFSK, 250-kHz deviation
4.7
2402
2480
MHz
MAX
UNIT
RF Receive Section
Measured on the TI CC2540 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
Receiver sensitivity (2)
High-gain mode
–93
dBm
(2)
Standard mode
–87
dBm
6
dBm
–5
dB
dB
Receiver sensitivity
Saturation (3)
Co-channel rejection (3)
(3)
±1 MHz
–5
Alternate-channel rejection (3)
±2 MHz
30
dB
–30
dBm
Adjacent-channel rejection
Blocking (3)
Frequency error tolerance (4)
Symbol rate error tolerance
Including both initial tolerance and drift
(5)
Conducted measurement with a 50-Ω single-ended load.
Spurious emission. Only largest spurious
Complies with EN 300 328, EN 300 440 class 2, FCC CFR47,
emission stated within each band.
Part 15 and ARIB STD-T-66
Current consumption
(3)
(4)
(5)
250
kHz
–80
80
ppm
–75
RX mode, standard mode, no peripherals active, low MCU
activity, MCU at 250 kHz
19.6
RX mode, high-gain mode, no peripherals active, low MCU
activity, MCU at 250 kHz
22.1
RX mode, high-gain mode, no peripherals active, low MCU
activity, MCU at 250 kHz;
TA = –40°C to 125°C, VDD = 2 V to 3.6 V, and fc = 2402 MHz
to 2480 MHz
(1)
(2)
–250
dBm
mA
30.5
0.1% BER maps to 30.8% PER
The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
Results based on standard gain mode
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
Specifications
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CC2540T
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
4.8
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RF Transmit Section
Measured on the TI CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz.
PARAMETER
TEST CONDITIONS
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting
Output power
TYP
1
4
Delivered to a single-ended 50 Ω load through a balun
Spurious emissions
(1)
4.9
UNIT
–23
27
dB
Conducted measurement with a 50-Ω single-ended load. Complies
with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB
STD-T-66 (1)
–41
dBm
TX mode, –23-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
21.1
TX mode, –6-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
23.8
TX mode, 0-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
27
TX mode, 4-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
31.6
mA
TX mode, 4-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz;
TA = –40°C to 125°C, VDD = 2 V to 3.6 V, and fc = 2402 MHz to
2480 MHz
Optimum load impedance
MAX
dBm
Delivered to a single-ended 50-Ω load through a balun using minimum
recommended output power setting
Programmable output power
range
Current consumption
MIN
39.6
Differential impedance as seen from the RF port (RF_P and RF_N)
toward the antenna
Ω
70 + j30
Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC resonator in front of the
antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect both from the signal trace to a good RF ground.
Current Consumption With TPS62730
Measured on the TI CC2540TPS62730 EM reference design with TA = 25°C, VDD = 3 V, and fc = 2440 MHZ.
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, 1% BER (1)
PARAMETER
Current consumption
(1)
10
TEST CONDITIONS
MIN
TYP
RX mode, standard mode, no peripherals active, low MCU activity,
MCU at 1 MHZ
15.8
RX mode, high-gain mode, no peripherals active, low MCU activity,
MCU at 1 MHZ
17.8
TX mode, –23-dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHZ
16.5
TX mode, –6-dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHZ
18.6
MAX
UNIT
mA
TX mode, 0-dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHZ
21
TX mode, 4-dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHZ
24.6
0.1% BER maps to 30.8% PER
Specifications
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4.10 32-MHz Crystal Oscillator
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
32
Crystal frequency accuracy
requirement (1)
MHz
–40
40
ppm
6
60
Ω
pF
ESR
Equivalent series resistance
C0
Crystal shunt capacitance
1
7
CL
Crystal load capacitance
10
16
Start-up time
0.25
The crystal oscillator must be in power down for
a guard time before it is used again. This
requirement is valid for all modes of operation.
The need for power-down guard time can vary
with crystal type and load.
Power-down guard time
(1)
UNIT
pF
ms
3
ms
Including aging and temperature dependency, as specified by [1]
4.11 32.768-kHz Crystal Oscillator
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
Crystal frequency accuracy requirement
TYP MAX
32.768
(1)
kHz
40
ppm
ESR
Equivalent series resistance
40
130
kΩ
C0
Crystal shunt capacitance
0.9
2
pF
CL
Crystal load capacitance
12
16
pF
Start-up time
0.4
(1)
–40
UNIT
s
Including aging and temperature dependency, as specified by [1]
4.12 32-kHz RC Oscillator
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
Calibrated frequency (1)
32.753
Frequency accuracy after calibration
±0.2%
Temperature coefficient (2)
Supply-voltage coefficient (3)
Calibration time
(1)
(2)
(3)
(4)
(4)
MAX
UNIT
kHz
0.4
%/°C
3
%/V
2
ms
The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
Frequency drift when temperature changes after calibration
Frequency drift when supply voltage changes after calibration
When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
Specifications
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4.13 16-MHz RC Oscillator
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
Frequency
TEST CONDITIONS
MIN
(1)
TYP
16
Uncalibrated frequency accuracy
±18%
Calibrated frequency accuracy
±0.6%
Start-up time
Initial calibration time
(1)
(2)
MAX
(2)
UNIT
MHz
10
µs
50
µs
The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
4.14 RSSI Characteristics
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
Useful RSSI range (1)
Absolute uncalibrated RSSI accuracy (1)
MIN
TYP
UNIT
–99 to –44
Standard mode
–90 to –35
High-gain mode
±4
dB
1
dB
Step size (LSB value)
(1)
MAX
High-gain mode
dBm
Assuming CC2540 EM reference design. Other RF designs give an offset from the reported value.
4.15
Frequency Synthesizer Characteristics
Measured on the TI CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz.
PARAMETER
Phase noise, unmodulated
carrier
4.16
TEST CONDITIONS
MIN
TYP
At ±1-MHz offset from carrier
–109
At ±3-MHz offset from carrier
–112
At ±5-MHz offset from carrier
–119
MAX
UNIT
dBc/Hz
Analog Temperature Sensor
Measured on the TI CC2540 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
Output
Temperature coefficient
Voltage coefficient
Initial accuracy without calibration
TYP
MAX
12-bit
4.5
/ 1°C
1
Measured using integrated ADC, internal band-gap
voltage reference, and maximum resolution
UNIT
1480
/ 0.1 V
±10
°C
Accuracy using 1-point calibration
±5
°C
Current consumption when enabled
0.5
mA
4.17
Comparator Characteristics
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2540T reference designs, post-calibration.
PARAMETER
TEST CONDITIONS
MIN
TYP
Common-mode maximum voltage
VDD
Common-mode minimum voltage
–0.3
Input offset voltage
Offset versus temperature
Offset versus operating voltage
MAX
UNIT
V
1
mV
16
µV/°C
4
mV/V
Supply current
230
nA
Hysteresis
0.15
mV
12
Specifications
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4.18
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
ADC Characteristics
TA = 25°C and VDD = 3 V
PARAMETER
ENOB (1)
TEST CONDITIONS
MIN
VDD is voltage on AVDD5 pin
0
VDD
V
VDD is voltage on AVDD5 pin
0
VDD
V
External reference voltage differential
VDD is voltage on AVDD5 pin
0
VDD
Input resistance, signal
Simulated using 4-MHz clock speed
197
kΩ
Full-scale signal (1)
Peak-to-peak, defines 0 dBFS
2.97
V
Effective number of bits
Single-ended input, 7-bit setting
5.7
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
9.3
Single-ended input, 12-bit setting
10.3
Differential input, 7-bit setting
6.5
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
Total harmonic distortion
10.9
7-bit setting, both single and differential
0–20
Single ended input, 12-bit setting, –6
dBFS (1)
–75.2
Differential input, 12-bit setting, –6
dBFS (1)
–86.6
Single-ended input, 12-bit setting (1)
70.2
(1)
dB
78.8
Differential input, 12-bit setting, –6
dBFS (1)
88.9
Common-mode rejection ratio
Differential input, 12-bit setting, 1-kHz
sine (0 dBFS), limited by ADC resolution
>84
dB
Crosstalk
Single ended input, 12-bit setting, 1-kHz
sine (0 dBFS), limited by ADC resolution
>84
dB
Offset
Midscale
–3
mV
Differential nonlinearity
Integral nonlinearity
Signal-to-noise-and-distortion
dB
0.68%
12-bit setting, mean (1)
0.05
12-bit setting, maximum (1)
0.9
12-bit setting, mean (1)
4.6
12-bit setting, maximum
(1)
13.3
12-bit setting, mean, clocked by RCOSC
10
12-bit setting, max, clocked by RCOSC
29
(1)
35.4
Single ended input, 9-bit setting (1)
46.8
Single ended input, 10-bit setting (1)
57.5
(1)
66.6
Single ended input, 7-bit setting
Single ended input, 12-bit setting
Differential input, 7-bit setting (1)
40.7
Differential input, 9-bit setting (1)
51.6
Differential input, 10-bit setting (1)
61.8
(1)
70.8
Differential input, 12-bit setting
(1)
kHz
79.3
Gain error
SINAD
(–THD+N)
bits
Single-ended input, 12-bit setting, –6
dBFS (1)
Signal to nonharmonic ratio
INL
V
9.7
12-bit setting, clocked by RCOSC
Differential input, 12-bit setting
DNL
UNIT
External reference voltage
Useful power bandwidth
CMRR
MAX
Input voltage
10-bit setting, clocked by RCOSC
THD
TYP
LSB
LSB
dB
Measured with 300-Hz sine-wave input and VDD as reference.
Specifications
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ADC Characteristics (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
Conversion time
MIN
TYP
7-bit setting
20
9-bit setting
36
10-bit setting
68
12-bit setting
132
Power consumption
mA
4
Internal reference temperature coefficient
Internal reference voltage
UNIT
µs
1.2
Internal reference VDD coefficient
4.19
MAX
mV/V
0.4
mV/10°C
1.24
V
Control Input AC Characteristics
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
System clock, fSYSCLK
tSYSCLK = 1 / fSYSCLK
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
16
RESET_N low duration
See item 1 in Figure 4-1. This is the shortest pulse that is recognized
as a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
1
µs
Interrupt pulse duration
See item 2 in Figure 4-1. This is the shortest pulse that is recognized
as an interrupt request.
20
ns
RESET_N
1
2
Px.n
T0299-01
Figure 4-1. Control Input AC Characteristics
14
Specifications
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4.20
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
SPI AC Characteristics
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
t1
TEST CONDITIONS
SCK period
SCK duty cycle
MIN
Master, RX and TX
250
Slave, RX and TX
250
TYP
MAX
UNIT
ns
Master
50%
Master
63
Slave
63
Master
63
Slave
63
t2
SSN low to SCK
t3
SCK to SSN high
t4
MOSI early out
Master, load = 10 pF
7
ns
t5
MOSI late out
Master, load = 10 pF
10
ns
t6
MISO setup
Master
90
t7
MISO hold
Master
10
SCK duty cycle
Slave
t10
MOSI setup
Slave
35
t11
MOSI hold
Slave
10
t9
MISO late out
Slave, load = 10 pF
Operating frequency
ns
ns
ns
ns
50%
ns
ns
ns
95
Master, TX only
8
Master, RX and TX
4
Slave, RX only
8
Slave, RX and TX
4
ns
MHz
SCK
t2
t3
SSN
t4
D0
MOSI
t6
MISO
t5
X
D1
t7
D0
X
X
T0478-01
Figure 4-2. SPI Master AC Characteristics
SCK
t2
t3
SSN
t8
D0
MISO
t10
MOSI
X
t9
X
D1
t11
D0
X
T0479-01
Figure 4-3. SPI Slave AC Characteristics
Specifications
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4.21
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Debug Interface AC Characteristics
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
MHz
fclk_dbg
Debug clock frequency (see Figure 4-4)
t1
Allowed high pulse on clock (see Figure 4-4)
35
ns
t2
Allowed low pulse on clock (see Figure 4-4)
35
ns
t3
EXT_RESET_N low to first falling edge on debug
clock (see Figure 4-6)
167
ns
t4
Falling edge on clock to EXT_RESET_N high
(see Figure 4-6)
83
ns
t5
EXT_RESET_N high to first debug command
(see Figure 4-6)
83
ns
t6
Debug data setup (see Figure 4-5)
2
ns
t7
Debug data hold (see Figure 4-5)
4
ns
t8
Clock-to-data delay (see Figure 4-5)
Load = 10 pF
30
ns
Time
DEBUG_ CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 4-4. Debug Clock–Basic Timing
Time
DEBUG_ CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 4-5. Debug Enable Timing
16
Specifications
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Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC2540)
P2_1
DEBUG_DATA
(from CC2540)
P2_1
t6
t8
t7
T0438-02
Figure 4-6. Data Setup and Hold Timing
4.22
Timer Inputs AC Characteristics
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
Input capture pulse duration
4.23
TEST CONDITIONS
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system clock
rate (16 MHz or 32 MHz).
MIN
TYP
MAX
UNIT
1.5
tSYSCLK
DC Characteristics
TA = 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Logic-0 input voltage
MAX
0.5
Logic-1 input voltage
2.5
Input equals 0 V
–50
50
Logic-1 input current
Input equals VDD
–50
50
20
Logic-0 output voltage, 4-mA pins
Output load 4 mA
Logic-1 output voltage, 4-mA pins
Output load 4 mA
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nA
nA
kΩ
0.5
2.4
V
V
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
V
V
Logic-0 input current
I/O-pin pullup and pulldown resistors
UNIT
17
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21
33
20.5
32.5
20
32
Current (mA)
Current (mA)
4.24 Typical Characteristics
19.5
19
31.5
31
18.5
30.5
18
-40
-20
0
20
40
60
Temperature (qC)
80
100
30
-40
120
-20
0
Gain = Standard Setting
Input = –70 dBm
VCC = 3 V
-72
7
-74
6
-76
5
Level (dBm)
Level (dBm)
100
120
Figure 4-8. TX Current vs Temperature
-78
-80
-82
-84
4
3
2
1
-86
-88
0
-90
-1
-92
-40
-20
0
20
40
60
Temperature (qC)
80
100
-2
-40
120
-20
Gain = Standard Setting
VCC = 3 V
0
20
40
60
Temperature (qC)
80
100
120
TX Power Setting = 4 dBm
VCC = 3 V
Figure 4-9. RX Sensitivity vs Temperature
Figure 4-10. TX Power vs Temperature
19.7
32
19.68
31.9
19.66
31.8
19.64
31.7
Current (mA)
Current (mA)
80
TX Power Setting = 4 dBm
VCC = 3 V
Figure 4-7. RX Current in Wait for Sync vs Temperature
19.62
19.6
19.58
31.6
31.5
31.4
19.56
31.3
19.54
31.2
19.52
31.1
31
19.5
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
2
Gain = Standard Setting
Input = –70 dBm
TA = 25°C
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
TA = 25°C
TX Power Setting = 4 dBm
Figure 4-11. RX Current in Wait for Sync vs Supply Voltage
18
20
40
60
Temperature (qC)
Figure 4-12. TX Current vs Supply Voltage
Specifications
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-87
5
-87.2
4.8
-87.4
4.6
-87.6
4.4
Level (dBm)
Level (dBm)
Typical Characteristics (continued)
-87.8
-88
-88.2
4.2
4
3.8
-88.4
3.6
-88.6
3.4
-88.8
3.2
-89
3
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
2
2.2
Gain = Standard Setting
TA = 25°C
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
TA = 25°C
TX Power Setting = 4 dBm
Figure 4-13. RX Sensitivity vs Supply Voltage
Figure 4-14. TX Power vs Supply Voltage
-87
70
-87.2
60
-87.4
50
Rejection (dB)
Level (dBm)
-87.6
-87.8
-88
-88.2
40
30
20
-88.4
10
-88.6
0
-88.8
-89
2400
2420
2440
2460
Frequency (MHz)
-10
2400
2480
Gain = Standard Setting
TA = 25°C
VCC = 3 V
2420
2440
2460
Frequency (MHz)
TA = 25°C
Figure 4-15. RX Sensitivity vs Frequency
2480
Wanted
Signal at
2426 MHz
with –67
dBm Level
VCC = 3 V
Gain = Standard Setting
Figure 4-16. RX Interferer Rejection (Selectivity) vs Interferer
Frequency
5
4.8
4.6
Level (dBm)
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2400
2420
2440
2460
Frequency (MHz)
2480
TA = 25°C
TX Power Setting = 4 dBm
VCC = 3 V
Figure 4-17. TX Power vs Frequency
Specifications
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Table 4-1. Output Power and Current Consumption (1) (2)
(1)
(2)
TYPICAL
OUTPUT POWER (dBm)
TYPICAL
CURRENT CONSUMPTION
(mA)
TYPICAL CURRENT
CONSUMPTION
WITH TPS62730 (mA)
4
32
24.6
0
27
21
–6
24
18.5
–23
21
16.5
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V and
fc = 2440 MHz. See SWRU191 for recommended register settings.
Measured on Texas Instruments CC2540TPS62730 EM reference design with TA = 25°C, VDD = 3 V
and fc = 2440 MHz. See SWRU191 for recommended register settings.
4.25 Typical Current Savings
25
40
35
30
35
20
20
20
15
15
10
30
DC/DC ON
DC/DC OFF
% Current Savings
Current (mA)
25
Current Savings (%)
30
25
Current (mA)
CC2540 Current Consumption
RX SG CLKCONMOD0x80
40
25
15
20
10
15
10
Current Savings (%)
CC2540 Current Consumption
TX 4dBm
35
DC/DC ON
DC/DC OFF
Current Savings
10
5
5
5
5
0
0
2.1
2.4
2.7
3
3.3
0
3.6
0
2.1
Supply (V)
Figure 4-18. Current Savings in TX at Room Temperature
2.4
2.7
3
3.3
3.6
Supply (V)
Figure 4-19. Current Savings in RX at Room Temperature
See the application note (SWRA365) for information regarding the CC2540T and TPS62730 como board
and the current savings that can be achieved using the como board.
20
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5 Detailed Description
5.1
Overview
The modules of the CC2540T device can be roughly divided into one of three categories:
• CPU-related modules
• Modules related to power, test, and clock distribution
• Radio-related modules
A short description of each module is given in the following subsections.
5.2
Functional Block Diagram
A block diagram of the CC2540T is shown in Figure 5-1.
Detailed Description
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XOSC_Q2
32-MHz
CRYSTAL OSC
XOSC_Q1
P2_4
32.768-kHz
CRYSTAL OSC
P2_3
P2_2
HIGHSPEED
RC-OSC
DEBUG
INTERFACE
P2_1
DCOUPL
POWER-ON RESET
BROWN OUT
CLOCK MUX
and
CALIBRATION
SFR Bus
RESET
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
WATCHDOG
TIMER
RESET_N
SLEEP TIMER
32-kHz
RC-OSC
POWER MANAGEMENT CONTROLLER
P2_0
PDATA
P1_7
P1_6
XRAM
8051 CPU
CORE
P1_5
IRAM
P1_4
SFR
MEMORY
ARBITRATOR
FLASH
FLASH
P1_3
P1_2
DMA
P1_1
UNIFIED
P1_0
IRQ CTRL
FLASH CTRL
P0_7
P0_6
ANALOG COMPARATOR
P0_5
1 KB SRAM
FIFOCTRL
Radio Arbiter
P0_4
OP-AMP
P0_2
AES
ENCRYPTION
AND
DECRYPTION
DS
ADC
AUDIO/DC
RADIO REGISTERS
Link Layer Engine
SFR Bus
P0_0
I/O CONTROLLER
P0_1
DEMODULATOR
SYNTH
P0_3
MODULATOR
USB_N
USB_P
USB
RECEIVE
USART 1
FREQUENCY
SYNTHESIZER
USART 0
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
DIGITAL
ANALOG
TIMER 4 (8-Bit)
MIXED
B0301-05
Figure 5-1. CC2540T Block Diagram
5.3
5.3.1
Block Descriptions
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses
(SFR, DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
22
Detailed Description
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The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the
physical memories and all peripherals through the SFR bus. The memory arbiter has four memory-access
points, access of which can map to one of three physical memories: an SRAM, flash memory, with
XREG/SFR registers. It is responsible for performing arbitration and sequencing between simultaneous
memory accesses to the same physical memory.
The SFR bus is drawn conceptually in Figure 5-1 as a common bus that connects all hardware
peripherals to the memory arbiter. The SFR bus in the block diagram also provides access to the radio
registers in the radio register bank, even though these are indeed mapped into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The
SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off
(power modes 2 and 3).
The 256-KB flash block provides in-circuit programmable non-volatile program memory for the device,
and maps into the CODE and XDATA memory spaces.
5.3.2
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and
4-bytewise programming. See the User's Guide (SWRU191) for details on the flash controller.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA
memory space, and thus has access to all physical memories. Each channel (trigger, priority, transfer
mode, addressing mode, source and destination pointers, and transfer count) is configured with DMA
descriptors that can be located anywhere in memory. Many of the hardware peripherals (AES core, flash
controller, USARTs, timers, ADC interface, and so forth) can be used with the DMA controller for efficient
operation by performing data transfers between a single SFR or XREG address and flash/SRAM.
Each CC2540T contains a unique 48-bit IEEE address that can be used as the public device address for a
Bluetooth device. Designers are free to use this address, or provide their own, as described in the
Bluetooth specification.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of
which is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced
even if the device is in a sleep mode (power modes 1 and 2) by bringing the CC2540T back to the active
mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit
debugging. Through this debug interface, it is possible to erase or program the entire flash memory,
control which oscillators are enabled, stop and start execution of the user program, execute instructions
on the 8051 core, set code breakpoints, and single-step through instructions in the code. Using these
techniques, it is possible to perform in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether
peripheral modules control certain pins or whether they are under software control, and if so, whether
each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected.
Each peripheral that connects to the I/O pins can choose between two different I/O pin locations to ensure
flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or
an internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except
power mode 3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get
out of power modes 1 or 2.
A built-in watchdog timer allows the CC2540T to reset itself if the firmware hangs. When enabled by
software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times
out.
Detailed Description
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Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit
period value, and five individually programmable counter/capture channels, each with a 16-bit compare
value. Each of the counter and capture channels can be used as a PWM output or to capture the timing of
edges on input signals. It can also be configured in IR generation mode, where it counts timer 3 periods
and the output is ANDed with the output of timer 3 to generate modulated consumer IR signals with
minimal CPU interaction.
Timer 2 is a 40-bit timer used by the Bluetooth low energy stack. It has a 16-bit counter with a
configurable timer period and a 24-bit overflow counter that can be used to keep track of the number of
periods that have transpired. A 40-bit capture register is also used to record the exact time at which a
start-of-frame delimiter is received or transmitted, or it is used to record the exact time at which
transmission ends. There are two 16-bit timer-compare registers and two 24-bit overflow-compare
registers that can be used to give exact timing for the start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable
prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value.
Each of the counter channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master or slave, or as a UART. They
provide double buffering on both RX and TX and hardware flow control and are thus well suited to highthroughput full-duplex applications. Each USART has its own high-precision baud-rate generator, which
leaves the ordinary timers free for other uses. When configured as SPI slaves, the USARTs sample the
input signal using SCK directly instead of using some oversampling scheme, and are thus well-suited for
high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES
algorithm with 128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as
well as hardware support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to
4-kHz, respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are
possible. The inputs can be selected as single-ended or differential. The reference voltage can be internal,
AVDD, or a single-ended or differential external signal. The ADC also has a temperature-sensor input
channel. The ADC can automate the process of periodic sampling or conversion over a sequence of
channels.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an
analog signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The
comparator output is connected to the I/O controller interrupt detector and can be treated by the MCU as a
regular I/O pin interrupt.
24
Detailed Description
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6 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
6.1
Application Information
Few external components are required for the operation of the CC2540T. A typical application circuit is
shown in Figure 6-1.
32-kHz Crystal
(1)
C331
2-V to 3.6-V Power Supply
XTAL2
C401
USB_P
3
USB_N
4
DVDD_USB
5
P1_5
6
P1_4
P1_3
8
P1_2
9
P1_1
P2_2 34
P2_1 35
P2_0 36
P1_7 37
P1_6 38
AVDD6 31
R301
RBIAS 30
L251
AVDD4 29
AVDD1 28
Antenna
(50 W)
C252
C251
AVDD2 27
L252
RF_N 26
L253
CC2540T
RF_P 25
DIE ATTACH PAD
C261
L261
AVDD3 24
XOSC_Q2 23
C262
C253
XOSC_Q1 22
19 P0_0
17 P0_2
18 P0_1
16 P0_3
15 P0_4
14 P0_5
12 P0_7
13 P0_6
11 P1_0
10 DVDD2
20 RESET_N
7
P2_4/XOSC32K_Q1 32
DGND_USB
P2_3/XOSC32K_Q2 33
1
2
DVDD1 39
DCOUPL 40
C321
AVDD5
21
XTAL1
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
C221
C231
S0383-03
(1) 32-kHz crystal is mandatory when running the chip in low-power modes, except if the link layer is in the standby
state (Vol. 6 Part B Section 1.1, see [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Figure 6-1. CC2540T Application Circuit
Applications, Implementation, and Layout
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Table 6-1. Overview of External Components (Excluding Supply Decoupling Capacitors)
COMPONENT
6.2
DESCRIPTION
VALUE
C221
32-MHz XTAL loading capacitor
12 pF
C231
32-MHz XTAL loading capacitor
12 pF
C251
Part of the RF matching network
18 pF
C252
Part of the RF matching network
1 pF
C253
Part of the RF matching network
1 pF
C261
Part of the RF matching network
18 pF
C262
Part of the RF matching network
1 pF
C321
32-kHz XTAL loading capacitor
15 pF
C331
32-kHz XTAL loading capacitor
15 pF
C401
Decoupling capacitor for the internal digital regulator
1 µF
L251
Part of the RF matching network
2 nH
L252
Part of the RF matching network
1 nH
L253
Part of the RF matching network
3 nH
L261
Part of the RF matching network
2 nH
R301
Resistor used for internal biasing
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize
performance. The balun can be implemented using low-cost discrete inductors and capacitors. The
recommended balun shown consists of C262, L261, C252, and L252.
6.3
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz
crystal oscillator. See Section 4.10 for details. The load capacitance seen by the 32-MHz crystal is given
by Equation 1:
1
CL =
+ Cparasitic
1
1
+
C221 C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for
32.768-kHz crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very
sleep-current consumption and accurate wake-up times are needed. The load capacitance seen by
32.768-kHz crystal is given by Equation 2:
1
CL =
+ Cparasitic
1
1
+
C321 C331
the
low
the
(2)
A series resistor may be used to comply with the ESR requirement.
6.4
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling
capacitor (C401) for stable operation.
6.5
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in
an application. TI provides a compact reference design that should be followed very closely (see
Section 6.6).
26
Applications, Implementation, and Layout
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6.6
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
Reference Design
Bluetooth Low Energy Light Reference Design
This reference design is an example of using the SimpleLink™ Bluetooth low energy CC2540T high
temperature range, wireless microcontroller in lighting applications. The board includes RGBW LEDs
controlled by the CC2540T and is USB powered. The board can be controlled out-of-the-box by the TI
BLE Multitool smart phone app.
Applications, Implementation, and Layout
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7 Device and Documentation Support
7.1
Documentation Support
7.1.1
Related Documentation
The following documents describe the CC2540T processor. Copies of these documents are available on
the Internet at www.ti.com.
[1]
Bluetooth® Core Technical Specification, Core Version 4.0
SWRU191
CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications,
CC2540/41 System-on-Chip Solution for 2.4-GHz Bluetooth Low Energy Applications
SWRA365
Current Savings in CC254x Using the TPS62730
7.1.2
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.2
Texas Instruments Low-Power RF Website
•
•
•
Forums, videos, and blogs
RF design help
E2E interaction
Join us today at www.ti.com/lprf-forum.
7.3
Texas Instruments Low-Power RF Developer Network
Texas Instruments has launched an extensive network of low-power RF development partners to help
customers speed up their application development. The network consists of recommended companies, RF
consultants, and independent design houses that provide a series of hardware module products and
design services, including:
• RF circuit, low-power RF, and ZigBee® design services
• Low-power RF and ZigBee module solutions and development tools
• RF certification services and RF circuit manufacturing
Need help with modules, engineering services, or development tools?
Search the Low-Power RF Developer Network tool to find a suitable partner.
www.ti.com/lprfnetwork
28
Device and Documentation Support
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7.4
SWRS172A – JULY 2014 – REVISED NOVEMBER 2015
Low-Power RF eNewsletter
The Low-Power RF eNewsletter keeps the user up-to-date on new products, news releases, developers’
news, and other news and events associated with low-power RF products from TI. The Low-Power RF
eNewsletter articles include links to get more online information.
Sign up today on
www.ti.com/lprfnewsletter
7.5
Trademarks
SmartRF, SimpleLink, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
IAR Embedded Workbench is a trademark of IAR Systems AB.
ZigBee is a registered trademark of ZigBee Alliance, Inc.
All other trademarks are the property of their respective owners.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical Packaging and Orderable Information
8.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2015, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
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11-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CC2540TF256RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2540T
F256
CC2540TF256RHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 125
CC2540T
F256
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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