CC2541
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SWRS110D – JANUARY 2012 – REVISED JUNE 2013
2.4-GHz Bluetooth™ low energy and Proprietary System-on-Chip
Check for Samples: CC2541
FEATURES
1
•
23
•
•
•
•
RF
– 2.4-GHz Bluetooth low energy Compliant
and Proprietary RF System-on-Chip
– Supports 250-kbps, 500-kbps, 1-Mbps, 2Mbps Data Rates
– Excellent Link Budget, Enabling LongRange Applications Without External Front
End
– Programmable Output Power up to 0 dBm
– Excellent Receiver Sensitivity (–94 dBm at
1 Mbps), Selectivity, and Blocking
Performance
– Suitable for Systems Targeting Compliance
With Worldwide Radio Frequency
Regulations: ETSI EN 300 328 and EN 300
440 Class 2 (Europe), FCC CFR47 Part 15
(US), and ARIB STD-T66 (Japan)
Layout
– Few External Components
– Reference Design Provided
– 6-mm × 6-mm QFN-40 Package
– Pin-Compatible With CC2540 (When Not
Using USB or I2C)
Low Power
– Active-Mode RX Down to: 17.9 mA
– Active-Mode TX (0 dBm): 18.2 mA
– Power Mode 1 (4-µs Wake-Up): 270 µA
– Power Mode 2 (Sleep Timer On): 1 µA
– Power Mode 3 (External Interrupts): 0.5 µA
– Wide Supply-Voltage Range (2 V–3.6 V)
TPS62730 Compatible Low Power in Active
Mode
– RX Down to: 14.7 mA (3-V supply)
– TX (0 dBm): 14.3 mA (3-V supply)
White space
White space
White space
White space
White space
White space
Microcontroller
•
•
– High-Performance and Low-Power 8051
Microcontroller Core With Code Prefetch
– In-System-Programmable Flash, 128- or
256-KB
– 8-KB RAM With Retention in All Power
Modes
– Hardware Debug Support
– Extensive Baseband Automation, Including
Auto-Acknowledgment and Address
Decoding
– Retention of All Relevant Registers in All
Power Modes
Peripherals
– Powerful Five-Channel DMA
– General-Purpose Timers (One 16-Bit, Two
8-Bit)
– IR Generation Circuitry
– 32-kHz Sleep Timer With Capture
– Accurate Digital RSSI Support
– Battery Monitor and Temperature Sensor
– 12-Bit ADC With Eight Channels and
Configurable Resolution
– AES Security Coprocessor
– Two Powerful USARTs With Support for
Several Serial Protocols
– 23 General-Purpose I/O Pins
(21 × 4 mA, 2 × 20 mA)
– I2C interface
– 2 I/O Pins Have LED Driving Capabilities
– Watchdog Timer
– Integrated High-Performance Comparator
Development Tools
– CC2541 Evaluation Module Kit
(CC2541EMK)
– CC2541 Mini Development Kit (CC2541DKMINI)
– SmartRF™ Software
– IAR Embedded Workbench™ Available
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc..
ZigBee is a registered trademark of ZigBee Alliance.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
CC2541
SWRS110D – JANUARY 2012 – REVISED JUNE 2013
www.ti.com
SOFTWARE FEATURES
CC2541 WITH TPS62730
•
•
Bluetooth v4.0 Compliant Protocol Stack for
Single-Mode BLE Solution
– Complete Power-Optimized Stack,
Including Controller and Host
– GAP – Central, Peripheral, Observer, or
Broadcaster (Including Combination
Roles)
– ATT / GATT – Client and Server
– SMP – AES-128 Encryption and
Decryption
– L2CAP
– Sample Applications and Profiles
– Generic Applications for GAP Central
and Peripheral Roles
– Proximity, Accelerometer, Simple Keys,
and Battery GATT Services
– More Applications Supported in BLE
Software Stack
– Multiple Configuration Options
– Single-Chip Configuration, Allowing
Applications to Run on CC2541
– Network Processor Interface for
Applications Running on an External
Microcontroller
– BTool – Windows PC Application for
Evaluation, Development, and Test
APPLICATIONS
•
•
•
•
•
•
2.4-GHz Bluetooth low energy Systems
Proprietary 2.4-GHz Systems
Human-Interface Devices (Keyboard, Mouse,
Remote Control)
Sports and Leisure Equipment
Mobile Phone Accessories
Consumer Electronics
•
•
•
•
•
•
TPS62730 is a 2-MHz Step-Down Converter
With Bypass Mode
Extends Battery Lifetime by up to 20%
Reduced Current in All Active Modes
30-nA Bypass Mode Current to Support LowPower Modes
RF Performance Unchanged
Small Package Allows for Small Solution Size
CC2541 Controllable
DESCRIPTION
The CC2541 is a power-optimized true system-onchip (SoC) solution for both Bluetooth low energy and
proprietary 2.4-GHz applications. It enables robust
network nodes to be built with low total bill-of-material
costs. The CC2541 combines the excellent
performance of a leading RF transceiver with an
industry-standard enhanced 8051 MCU, in-system
programmable flash memory, 8-KB RAM, and many
other powerful supporting features and peripherals.
The CC2541 is highly suited for systems where
ultralow power consumption is required. This is
specified by various operating modes. Short transition
times between operating modes further enable low
power consumption.
The CC2541 is pin-compatible with the CC2540 in
the 6-mm × 6-mm QFN40 package, if the USB is not
used on the CC2540 and the I2C/extra I/O is not used
on the CC2541. Compared to the CC2540, the
CC2541 provides lower RF current consumption. The
CC2541 does not have the USB interface of the
CC2540, and provides lower maximum output power
in TX mode. The CC2541 also adds a HW I2C
interface.
The CC2541 is pin-compatible with the CC2533
RF4CE-optimized IEEE 802.15.4 SoC.
The CC2541 comes in two different versions:
CC2541F128/F256, with 128 KB and 256 KB of flash
memory, respectively.
For the CC2541 block diagram, see Figure 1.
2
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CC2541
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SWRS110D – JANUARY 2012 – REVISED JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
RESET
XOSC_Q2
WATCHDOG TIMER
XOSC_Q1
CLOCK MUX and
CALIBRATION
32.768-kHz
CRYSTAL OSC
P2_4
P2_3
P2_2
DEBUG
INTERFACE
P2_1
DCOUPL
POWER-ON RESET
BROWN OUT
32-MHZ
CRYSTAL OSC
HIGH SPEED
RC-OSC
SFR bus
RESET_N
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
SLEEP TIMER
POWER MGT. CONTROLLER
32-kHz
RC-OSC
P2_0
PDATA
P1_7
P1_6
P1_5
RAM
SRAM
FLASH
FLASH
XRAM
8051 CPU
CORE
IRAM
P1_4
SFR
MEMORY
ARBITRATOR
P1_3
P1_2
UNIFIED
DMA
P1_1
P1_0
IRQ
CTRL
ANALOG COMPARATOR
P0_4
P0_3
P0_2
P0_1
P0_0
FIFOCTRL
OP-
DS ADC
AUDIO / DC
Radio Arbiter
P0_5
I/O CONTROLLER
P0_6
AES
ENCRYPTION
and
DECRYPTION
Link Layer Engine
2
I C
SCL
SFR bus
DEMODULATOR
SDA
1-KB SRAM
RADIO
REGISTERS
SYNTH
P0_7
FLASH CTRL
MODULATOR
USART 1
RECEIVE
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
FREQUENCY
SYNTHESIZER
USART 0
TRANSMIT
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RF_P RF_N
DIGITAL
ANALOG
MIXED
Figure 1. Block Diagram
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CC2541
SWRS110D – JANUARY 2012 – REVISED JUNE 2013
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
MAX
UNIT
–0.3
3.9
V
–0.3
VDD + 0.3 ≤ 3.9
V
10
dBm
125
°C
All pins, excluding pins 25 and 26, according to human-body
model, JEDEC STD 22, method A114
2
kV
All pins, according to human-body model, JEDEC STD 22,
method A114
1
kV
500
V
All supply pins must have the same voltage
Voltage on any digital pin
Input RF level
Storage temperature range
ESD (2)
–40
According to charged-device model, JEDEC STD 22, method
C101
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CAUTION: ESD sesnsitive device. Precautions should be used when handling the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Operating ambient temperature range, TA
NOM
MAX
UNIT
–40
85
°C
2
3.6
V
Operating supply voltage
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V,
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER
PARAMETER
Icore
Iperi
4
Core current consumption
Peripheral current consumption
(Adds to core current Icore for each
peripheral unit activated)
TEST CONDITIONS
MIN
TYP MAX UNIT
RX mode, standard mode, no peripherals active, low MCU
activity
17.9
RX mode, high-gain mode, no peripherals active, low MCU
activity
20.2
TX mode, –20 dBm output power, no peripherals active, low
MCU activity
16.8
TX mode, 0 dBm output power, no peripherals active, low
MCU activity
18.2
Power mode 1. Digital regulator on; 16-MHz RCOSC and 32MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and
sleep timer active; RAM and register retention
270
Power mode 2. Digital regulator off; 16-MHz RCOSC and 32MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep
timer active; RAM and register retention
1
mA
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
0.5
Low MCU activity: 32-MHz XOSC running. No radio or
peripherals. Limited flash access, no RAM access.
6.7
Timer 1. Timer running, 32-MHz XOSC used
90
Timer 2. Timer running, 32-MHz XOSC used
90
Timer 3. Timer running, 32-MHz XOSC used
60
Timer 4. Timer running, 32-MHz XOSC used
70
Sleep timer, including 32.753-kHz RCOSC
0.6
ADC, when converting
1.2
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µA
mA
μA
mA
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: CC2541
CC2541
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SWRS110D – JANUARY 2012 – REVISED JUNE 2013
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Power mode 1 → Active
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
4
μs
Power mode 2 or 3 → Active
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
120
μs
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,
with 32-MHz XOSC OFF
500
μs
With 32-MHz XOSC initially on
180
μs
Proprietary auto mode
130
BLE mode
150
Active → TX or RX
RX/TX turnaround
μs
RADIO PART
RF frequency range
Programmable in 1-MHz steps
Data rate and modulation format
2 Mbps, GFSK, 500-kHz deviation
2 Mbps, GFSK, 320-kHz deviation
1 Mbps, GFSK, 250-kHz deviation
1 Mbps, GFSK, 160-kHz deviation
500 kbps, MSK
250 kbps, GFSK, 160-kHz deviation
250 kbps, MSK
2379
2496
MHz
RF RECEIVE SECTION
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Receiver sensitivity
–90
dBm
Saturation
BER < 0.1%
–1
dBm
Co-channel rejection
Wanted signal at –67 dBm
–9
dB
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
–2
±4 MHz offset, 0.1% BER, wanted signal –67 dBm
36
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm
41
In-band blocking rejection
dB
Frequency error tolerance (1)
Including both initial tolerance and drift. Sensitivity better than –67dBm,
250 byte payload. BER 0.1%
–300
300
kHz
Symbol rate error
tolerance (2)
Maximum packet length. Sensitivity better than–67dBm, 250 byte
payload. BER 0.1%
–120
120
ppm
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER
Receiver sensitivity
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal at –67 dBm
In-band blocking rejection
–86
dBm
–7
dBm
–12
dB
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
–1
±4 MHz offset, 0.1% BER, wanted signal –67 dBm
34
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm
39
dB
Frequency error tolerance (1)
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250 byte payload. BER 0.1%
–300
300
kHz
Symbol rate error
tolerance (2)
Maximum packet length. Sensitivity better than –67 dBm, 250 byte
payload. BER 0.1%
–120
120
ppm
(1)
(2)
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
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CC2541
SWRS110D – JANUARY 2012 – REVISED JUNE 2013
www.ti.com
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BER
Receiver sensitivity (3) (4)
Saturation (4)
Co-channel rejection
High-gain mode
–94
Standard mode
–88
BER < 0.1%
(4)
In-band blocking rejection (4)
5
dBm
Wanted signal –67 dBm
–6
dB
±1 MHz offset, 0.1% BER, wanted signal –67 dBm
–2
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
26
±3 MHz offset, 0.1% BER, wanted signal –67 dBm
34
>6 MHz offset, 0.1% BER, wanted signal –67 dBm
Out-of-band blocking
rejection (4)
dBm
dB
33
Minimum interferer level < 2 GHz (Wanted signal –67 dBm)
–21
Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm)
–25
Minimum interferer level > 3 GHz (Wanted signal –67 dBm)
dBm
–7
Intermodulation (4)
Minimum interferer level
Frequency error tolerance (5)
Including both initial tolerance and drift. Sensitivity better than -67dBm,
250 byte payload. BER 0.1%
Symbol rate error
tolerance (6)
Maximum packet length. Sensitivity better than –67 dBm, 250 byte
payload. BER 0.1%
–36
dBm
–250
250
kHz
–80
80
ppm
1 Mbps, GFSK, 160-kHz Deviation, 0.1% BER
Receiver sensitivity (7)
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal 10 dB above sensitivity level
In-band blocking rejection
Frequency error tolerance
(5)
Symbol rate error
tolerance (6)
–91
dBm
0
dBm
–9
dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
2
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
24
±3-MHz offset, 0.1% BER, wanted signal -–67 dBm
27
>6-MHz offset, 0.1% BER, wanted signal –67 dBm
32
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
dB
–200
200
kHz
–80
80
ppm
500 kbps, MSK, 0.1% BER
Receiver sensitivity (7)
–99
dBm
Saturation
BER < 0.1%
0
dBm
Co-channel rejection
Wanted signal –67 dBm
–5
dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
20
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
27
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
28
In-band blocking rejection
Frequency error tolerance
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Symbol rate error tolerance
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
(3)
(4)
(5)
(6)
(7)
6
dB
–150
150
kHz
–80
80
ppm
The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
Results based on standard-gain mode.
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
Results based on high-gain mode.
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SWRS110D – JANUARY 2012 – REVISED JUNE 2013
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
–98
dBm
0
dBm
dB
250 kbps, GFSK, 160 kHz Deviation, 0.1% BER
Receiver sensitivity
(8)
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal -67 dBm
–3
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
23
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
28
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
29
In-band blocking rejection
Frequency error tolerance (9)
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Symbol rate error
tolerance (10)
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
dB
–150
150
kHz
–80
80
ppm
250 kbps, MSK, 0.1% BER
Receiver sensitivity
(11)
–99
dBm
0
dBm
Wanted signal -67 dBm
–5
dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
20
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
29
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
30
Saturation
BER < 0.1%
Co-channel rejection
In-band blocking rejection
Frequency error tolerance
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Symbol rate error tolerance
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
dB
–150
150
kHz
–80
80
ppm
ALL RATES/FORMATS
Spurious emission in RX.
Conducted measurement
f < 1 GHz
–67
dBm
Spurious emission in RX.
Conducted measurement
f > 1 GHz
–57
dBm
(8)
(9)
(10)
(11)
Results based on standard-gain mode.
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
Results based on high-gain mode.
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CC2541
SWRS110D – JANUARY 2012 – REVISED JUNE 2013
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
Output power
Programmable output power
range
MIN
TYP
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting
0
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting
–23
MAX
UNIT
dBm
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting
f < 1 GHz
23
dB
–52
dBm
Spurious emission conducted f > 1 GHz
–48
dBm
measurement
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Differential impedance as seen from the RF port (RF_P and RF_N)
toward the antenna
Optimum load impedance
Ω
70 +j30
Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC
resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect
both from the signal trace to a good RF ground.
CURRENT CONSUMPTION WITH TPS62730
Measured on Texas Instruments CC2541 TPA62730 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz,
1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy Mode, 1% BER (1)
PARAMETER
Current consumption
TEST CONDITIONS
MIN
TYP
RX mode, standard mode, no peripherals active, low MCU activity, MCU
at 1 MHz
14.7
RX mode, high-gain mode, no peripherals active, low MCU activity,
MCU at 1 MHz
16.7
TX mode, –20 dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHz
UNIT
mA
13.1
TX mode, 0 dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHz
(1)
MAX
14.3
0.1% BER maps to 30.8% PER
32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
32
Crystal frequency accuracy
requirement (1)
UNIT
MHz
–40
40
ppm
ESR
Equivalent series resistance
6
60
Ω
C0
Crystal shunt capacitance
1
7
pF
CL
Crystal load capacitance
10
16
pF
Start-up time
Power-down guard time
(1)
8
0.25
The crystal oscillator must be in power down for a guard
time before it is used again. This requirement is valid for
all modes of operation. The need for power-down guard
time can vary with crystal type and load.
3
ms
ms
Including aging and temperature dependency, as specified by [1]
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32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
UNIT
40
ppm
32.768
Crystal frequency accuracy requirement (1)
–40
kHz
ESR
Equivalent series resistance
40
130
kΩ
C0
Crystal shunt capacitance
0.9
2
pF
CL
Crystal load capacitance
12
16
pF
Start-up time
0.4
(1)
s
Including aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
Calibrated frequency (1)
32.753
Frequency accuracy after calibration
±0.2%
Temperature coefficient (2)
MAX
UNIT
kHz
0.4
%/°C
Supply-voltage coefficient (3)
3
%/V
Calibration time (4)
2
ms
(1)
(2)
(3)
(4)
The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
Frequency drift when temperature changes after calibration
Frequency drift when supply voltage changes after calibration
When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
Frequency
TEST CONDITIONS
(1)
MIN
TYP
16
Uncalibrated frequency accuracy
±18%
Calibrated frequency accuracy
±0.6%
Start-up time
Initial calibration time
(1)
(2)
MAX
(2)
UNIT
MHz
10
μs
50
μs
The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
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RSSI CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Useful RSSI range (1)
RSSI offset (1)
Reduced gain by AGC algorithm
64
High gain by AGC algorithm
64
Reduced gain by AGC algorithm
79
High gain by AGC algorithm
99
Absolute uncalibrated accuracy (1)
dB
dBm
±6
dB
1
dB
Step size (LSB value)
All Other Rates/Formats
Useful RSSI range (1)
RSSI offset (1)
Standard mode
64
High-gain mode
64
Standard mode
98
High-gain mode
107
Absolute uncalibrated accuracy (1)
dBm
±3
dB
1
dB
Step size (LSB value)
(1)
dB
Assuming CC2541 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
Phase noise, unmodulated carrier
MIN
TYP
At ±1-MHz offset from carrier
–109
At ±3-MHz offset from carrier
–112
At ±5-MHz offset from carrier
–119
MAX
UNIT
dBc/Hz
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Output
TYP
Initial accuracy without calibration
UNIT
12-bit
4.5
/ 1°C
1
0.1 V
Temperature coefficient
Voltage coefficient
MAX
1480
Measured using integrated ADC, internal band-gap voltage
reference, and maximum resolution
±10
°C
Accuracy using 1-point calibration
±5
°C
Current consumption when enabled
0.5
mA
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2541 reference designs, post-calibration.
PARAMETER
TEST CONDITIONS
TYP MAX
VDD
Common-mode minimum voltage
–0.3
Input offset voltage
Offset vs temperature
Offset vs operating voltage
10
MIN
Common-mode maximum voltage
UNIT
V
1
mV
16
µV/°C
4
mV/V
Supply current
230
nA
Hysteresis
0.15
mV
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ADC CHARACTERISTICS
TA = 25°C and VDD = 3 V
PARAMETER
ENOB (1)
TEST CONDITIONS
MIN
VDD is voltage on AVDD5 pin
0
VDD
V
VDD is voltage on AVDD5 pin
0
VDD
V
External reference voltage differential VDD is voltage on AVDD5 pin
0
VDD
Simulated using 4-MHz clock speed
197
kΩ
Full-scale signal (1)
Peak-to-peak, defines 0 dBFS
2.97
V
Effective number of bits
Total harmonic distortion
Signal to nonharmonic ratio
Single-ended input, 7-bit setting
5.7
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
9.3
Single-ended input, 12-bit setting
10.3
Differential input, 7-bit setting
6.5
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
10.9
7-bit setting, both single and differential
0–20
Single ended input, 12-bit setting, –6 dBFS (1)
–75.2
Differential input, 12-bit setting, –6 dBFS (1)
–86.6
79.3
(1)
dB
78.8
88.9
Common-mode rejection ratio
Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
>84
dB
Crosstalk
Single ended input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
>84
dB
Offset
Midscale
–3
mV
Differential nonlinearity
0.68%
12-bit setting, mean (1)
0.05
(1)
0.9
12-bit setting, maximum (1)
13.3
12-bit setting, maximum
Integral nonlinearity
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Signal-to-noise-and-distortion
Conversion time
(1)
dB
Differential input, 12-bit setting, –6 dBFS (1)
12-bit setting, mean (1)
SINAD
(–THD+N)
kHz
70.2
Differential input, 12-bit setting (1)
Single-ended input, 12-bit setting, –6 dBFS
bits
9.7
12-bit setting, clocked by RCOSC
Gain error
INL
V
Input resistance, signal
Single-ended input, 12-bit setting (1)
DNL
UNIT
External reference voltage
Useful power bandwidth
CMRR
MAX
Input voltage
10-bit setting, clocked by RCOSC
THD
TYP
LSB
4.6
10
LSB
29
Single ended input, 7-bit setting (1)
35.4
Single ended input, 9-bit setting (1)
46.8
Single ended input, 10-bit setting (1)
57.5
Single ended input, 12-bit setting (1)
66.6
Differential input, 7-bit setting (1)
40.7
Differential input, 9-bit setting (1)
51.6
Differential input, 10-bit setting (1)
61.8
Differential input, 12-bit setting (1)
70.8
7-bit setting
20
9-bit setting
36
10-bit setting
68
12-bit setting
132
dB
μs
Measured with 300-Hz sine-wave input and VDD as reference.
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ADC CHARACTERISTICS (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Power consumption
MAX
UNIT
1.2
Internal reference VDD coefficient
mA
4
Internal reference temperature
coefficient
Internal reference voltage
mV/V
0.4
mV/10°C
1.24
V
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
16
RESET_N low duration
See item 1, Figure 2. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
1
µs
Interrupt pulse duration
See item 2, Figure 2.This is the shortest pulse that is recognized as
an interrupt request.
20
ns
RESET_N
1
2
Px.n
T0299-01
Figure 2. Control Input AC Characteristics
12
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SPI AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
t1
TEST CONDITIONS
SCK period
SCK duty cycle
MIN
Master, RX and TX
250
Slave, RX and TX
250
Master
TYP MAX
UNIT
ns
50%
Master
63
Slave
63
Master
63
Slave
63
t2
SSN low to SCK
t3
SCK to SSN high
t4
MOSI early out
Master, load = 10 pF
7
ns
t5
MOSI late out
Master, load = 10 pF
10
ns
t6
MISO setup
Master
90
t7
MISO hold
Master
10
SCK duty cycle
Slave
t10
MOSI setup
Slave
35
ns
t11
MOSI hold
Slave
10
ns
t9
MISO late out
Slave, load = 10 pF
Operating frequency
ns
ns
ns
ns
50%
ns
95
Master, TX only
8
Master, RX and TX
4
Slave, RX only
8
Slave, RX and TX
4
ns
MHz
SCK
t2
t3
SSN
t4
D0
MOSI
t6
MISO
X
t5
X
D1
t7
D0
X
T0478-01
Figure 3. SPI Master AC Characteristics
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SCK
t2
t3
SSN
t8
D0
MISO
X
t10
MOSI
t9
t11
D0
X
D1
X
T0479-01
Figure 4. SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
MHz
fclk_dbg
Debug clock frequency (see Figure 5)
t1
Allowed high pulse on clock (see Figure 5)
35
ns
t2
Allowed low pulse on clock (see Figure 5)
35
ns
t3
EXT_RESET_N low to first falling edge on debug clock (see
Figure 7)
167
ns
t4
Falling edge on clock to EXT_RESET_N high (see Figure 7)
83
ns
t5
EXT_RESET_N high to first debug command (see Figure 7)
83
ns
t6
Debug data setup (see Figure 6)
2
ns
t7
Debug data hold (see Figure 6)
t8
Clock-to-data delay (see Figure 6)
4
ns
Load = 10 pF
30
ns
Time
DEBUG_ CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 5. Debug Clock – Basic Timing
14
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Time
DEBUG_ CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 6. Debug Enable Timing
Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC2541)
P2_1
DEBUG_DATA
(from CC2541)
P2_1
t6
t8
t7
Figure 7. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
Input capture pulse duration
TEST CONDITIONS
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
MIN
1.5
TYP
MAX
UNIT
tSYSCLK
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DC CHARACTERISTICS
TA = 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Logic-0 input voltage
Logic-1 input voltage
UNIT
0.5
V
2.4
V
Logic-0 input current
Input equals 0 V
–50
50
nA
Logic-1 input current
Input equals VDD
–50
50
nA
I/O-pin pullup and pulldown resistors
20
Logic-0 output voltage, 4- mA pins
Output load 4 mA
Logic-1 output voltage, 4-mA pins
Output load 4 mA
Logic-0 output voltage, 20- mA pins
Output load 20 mA
Logic-1 output voltage, 20-mA pins
Output load 20 mA
kΩ
0.5
2.5
V
0.5
2.5
V
V
V
DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2541 pinout is shown in Figure 8 and a short description of the pins follows.
DVDD1
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3 / OSC32K_Q2
P2_4 / OSC32K_Q1
40
39
38
37
36
35
34
33
32
AVDD6
DCOUPL
CC2541
RHA Package
(Top View)
31
30
R_BIAS
2
29
AVDD4
SDA
3
28
AVDD1
GND
1
SCL
NC
4
27
AVDD2
P1_5
5
26
RF_N
P1_4
6
25
RF_P
P1_3
7
24
AVDD3
P1_2
8
23
XOSC_Q2
P1_1
9
22
14
15
16
17
18
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
19
P0_0
13
21
20
XOSC_Q1
AVDD5
RESET_N
12
P0_7
10
11
P1_0
DVDD2
GND
Ground Pad
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 8. Pinout Top View
16
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PIN DESCRIPTIONS
PIN NAME
PIN
PIN TYPE
DESCRIPTION
AVDD1
28
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD2
27
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD3
24
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD4
29
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD5
21
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD6
31
Power (analog)
2-V–3.6-V analog power-supply connection
DCOUPL
40
Power (digital)
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
DVDD1
39
Power (digital)
2-V–3.6-V digital power-supply connection
DVDD2
10
Power (digital)
2-V–3.6-V digital power-supply connection
GND
1
Ground pin
Connect to GND
GND
—
Ground
The ground pad must be connected to a solid ground plane.
NC
4
Unused pins
Not connected
P0_0
19
Digital I/O
Port 0.0
P0_1
18
Digital I/O
Port 0.1
P0_2
17
Digital I/O
Port 0.2
P0_3
16
Digital I/O
Port 0.3
P0_4
15
Digital I/O
Port 0.4
P0_5
14
Digital I/O
Port 0.5
P0_6
13
Digital I/O
Port 0.6
P0_7
12
Digital I/O
Port 0.7
P1_0
11
Digital I/O
Port 1.0 – 20-mA drive capability
P1_1
9
Digital I/O
Port 1.1 – 20-mA drive capability
P1_2
8
Digital I/O
Port 1.2
P1_3
7
Digital I/O
Port 1.3
P1_4
6
Digital I/O
Port 1.4
P1_5
5
Digital I/O
Port 1.5
P1_6
38
Digital I/O
Port 1.6
P1_7
37
Digital I/O
Port 1.7
P2_0
36
Digital I/O
Port 2.0
P2_1/DD
35
Digital I/O
Port 2.1 / debug data
P2_2/DC
34
Digital I/O
Port 2.2 / debug clock
P2_3/
OSC32K_Q2
33
Digital I/O, Analog I/O
Port 2.3/32.768 kHz XOSC
P2_4/
OSC32K_Q1
32
Digital I/O, Analog I/O
Port 2.4/32.768 kHz XOSC
RBIAS
30
Analog I/O
External precision bias resistor for reference current
RESET_N
20
Digital input
Reset, active-low
RF_N
26
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
25
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
SCL
2
I2C clock or digital I/O
Can be used as I2C clock pin or digital I/O. Leave floating if not used. If grounded
disable pull up
SDA
3
I2C clock or digital I/O
Can be used as I2C data pin or digital I/O. Leave floating if not used. If grounded
disable pull up
XOSC_Q1
22
Analog I/O
32-MHz crystal oscillator pin 1 or external clock input
XOSC_Q2
23
Analog I/O
32-MHz crystal oscillator pin 2
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BLOCK DIAGRAM
A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
RESET
XOSC_Q2
WATCHDOG TIMER
XOSC_Q1
CLOCK MUX and
CALIBRATION
32.768-kHz
CRYSTAL OSC
P2_4
P2_3
P2_2
DEBUG
INTERFACE
P2_1
DCOUPL
POWER-ON RESET
BROWN OUT
32-MHZ
CRYSTAL OSC
HIGH SPEED
RC-OSC
SFR bus
RESET_N
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
SLEEP TIMER
POWER MGT. CONTROLLER
32-kHz
RC-OSC
P2_0
PDATA
P1_7
P1_6
P1_5
RAM
SRAM
FLASH
FLASH
XRAM
8051 CPU
CORE
IRAM
P1_4
SFR
MEMORY
ARBITRATOR
P1_3
P1_2
UNIFIED
DMA
P1_1
P1_0
IRQ
CTRL
ANALOG COMPARATOR
P0_4
P0_3
P0_2
P0_1
P0_0
FIFOCTRL
OP-
DS ADC
AUDIO / DC
Radio Arbiter
P0_5
I/O CONTROLLER
P0_6
AES
ENCRYPTION
and
DECRYPTION
Link Layer Engine
2
I C
SCL
SFR bus
DEMODULATOR
SDA
1-KB SRAM
RADIO
REGISTERS
SYNTH
P0_7
FLASH CTRL
MODULATOR
USART 1
RECEIVE
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
FREQUENCY
SYNTHESIZER
USART 0
TRANSMIT
TIMER 3 (8-bit)
RF_P RF_N
TIMER 4 (8-bit)
DIGITAL
ANALOG
MIXED
Figure 9. CC2541 Block Diagram
18
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BLOCK DESCRIPTIONS
A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 9 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is
an ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 and
mode 3).
The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,
ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers
between a single SFR or XREG address and flash/SRAM.
Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for a
Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth
specfication.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the
device is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators
are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code
breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform incircuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an
internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode
3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1
or mode 2.
A built-in watchdog timer allows the CC2541 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
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Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counter
that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is also
used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which
transmission ends. There are two 16-bit output compare registers and two 24-bit overflow compare registers that
can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free
for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead
of using some oversampling scheme, and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,
respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The
inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a singleended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can
automate the process of periodic sampling or conversion over a sequence of channels.
The I2C module provides a digital peripheral connection with two pins and supports both master and slave
operation. I2C support is compliant with the NXP I2C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as well as
master and slave modes.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
20
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TYPICAL CHARACTERISTICS
RX CURRENT
vs
TEMPERATURE
TX CURRENT
vs
TEMPERATURE
19
19.5
19
Current (mA)
18.5
Current (mA)
TX Power Setting = 0 dBm
VCC = 3 V
1 Mbps GFSK 250 kHz
Standard Gain Setting
Input = −70 dBm
VCC = 3 V
18
17.5
17
−20
0
20
40
Temperature (°C)
60
17
−40
80
0
20
40
Temperature (°C)
Figure 10.
Figure 11.
RX SENSITIVITY
vs
TEMPERATURE
TX POWER
vs
TEMPERATURE
60
80
G002
4.0
TX Power Setting = 0 dBm
VCC = 3 V
1 Mbps GFSK 250 kHz
Standard Gain Setting
VCC = 3 V
2.0
Level (dBm)
−86
−88
−90
0.0
−2.0
−92
−40
−20
0
20
40
Temperature (°C)
60
−4.0
−40
80
−20
0
G003
20
40
Temperature (°C)
Figure 12.
Figure 13.
RX CURRENT
vs
SUPPLY VOLTAGE
TX CURRENT
vs
SUPPLY VOLTAGE
20
60
80
G004
20
1 Mbps GFSK 250 kHz
Standard Gain Setting
Input = −70 dBm
TA = 25°C
19.5
19
Current (mA)
19
18
17.5
18.5
18
17.5
17
17
16.5
16.5
2
2.2
2.4
2.6
2.8
3
Voltage (V)
3.2
3.4
TX Power Setting = 0 dBm
TA = 25°C
19.5
18.5
16
−20
G001
−84
Level (dBm)
18
17.5
16.5
−40
Current (mA)
18.5
3.6
16
2
G005
Figure 14.
2.2
2.4
2.6
2.8
3
Voltage (V)
3.2
3.4
3.6
G006
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
RX SENSITIVITY
vs
SUPPLY VOLTAGE
TX POWER
vs
SUPPLY VOLTAGE
−84
4
2
Level (dBm)
−86
Level (dBm)
TX Power Setting = 0 dBm
TA = 25°C
1 Mbps GFSK 250 kHz
Standard Gain Setting
TA = 25°C
−88
−90
−92
−2
2
2.2
2.4
2.6
2.8
3
Voltage (V)
3.2
3.4
−4
3.6
2
G007
2.2
2.4
2.6
2.8
3
Voltage (V)
Figure 16.
Figure 17.
RX SENSITIVITY
vs
FREQUENCY
TX POWER
vs
FREQUENCY
−84
3.2
3.4
3.6
G008
4
1 Mbps GFSK 250 kHz
Standard Gain Setting
TA = 25°C
VCC = 3 V
−88
TX Power Setting = 0 dBm
TA = 25°C
VCC = 3 V
2
Level (dBm)
−86
Level (dBm)
0
0
−90
−2
−92
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G009
−4
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G010
Figure 18.
Figure 19.
Table 1. Output Power (1) (2)
(1)
(2)
22
TXPOWER Setting
Typical Output Power (dBm)
0xE1
0
0xD1
–2
0xC1
–4
0xB1
–6
0xA1
–8
0x91
–10
0x81
–12
0x71
–14
0x61
–16
0x51
–18
0x41
–20
0x31
–23
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz. See SWRU191 for
recommended register settings.
1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy mode, 1% BER
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Table 2. Output Power and Current Consumption
Typical Output Power (dBm)
Typical Current Consumption
(mA) (1)
Typical Current Consumption
With TPS62730 (mA) (2)
0
18.2
14.3
–20
16.8
13.1
(1)
(2)
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc =
2440 MHz. See SWRU191 for recommended register settings.
Measured on Texas Instruments CC2541 TPS62730 EM reference design with TA = 25°C, VDD = 3 V
and fc = 2440 MHz. See SWRU191 for recommended register settings.
TYPICAL CURRENT SAVINGS WHEN USING TPS62730
Current Consumption TX 0 dBm
0
25
40
25
40
DC/DC OFF
DC/DC OFF
35
DC/DC ON
35
20
Current Savings
Current Savings
30
20
10
15
Current (mA)
25
15
Current Savings (%)
Current (mA)
30
25
15
20
10
15
10
10
5
5
5
0
Current Savings (%)
DC/DC ON
20
Current Consumption RX SG
CLKCONMOD 0xBF
2.1
2.4
2.7
3
Supply (V)
3.3
3.6
Figure 20. Current Savings in TX at Room
Temperature
0
5
0
2.1
2.4
2.7
3
Supply (V)
3.3
3.6
0
Figure 21. Current Savings in RX at Room
Temperature
The application note (SWRA365) has information regarding the CC2541 and TPS62730 combo board and the
current savings that can be achieved using the combo board.
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2541. A typical application circuit is shown in
Figure 22.
32-kHz Crystal
(1)
C331
2-V to 3.6-V Power Supply
XTAL2
C401
3
SDA
4
NC
5
P1_5
6
P1_4
7
P1_2
9
P1_1
P2_1 35
P2_2 34
P2_0 36
P1_7 37
P1_6 38
AVDD6 31
AVDD4 29
Antenna
(50 W)
AVDD1 28
AVDD2 27
RF_N 26
CC2541
RF_P 25
DIE ATTACH PAD
P1_3
8
R301
RBIAS 30
AVDD3 24
XOSC_Q2 23
XOSC_Q1 22
19 P0_0
18 P0_1
17 P0_2
16 P0_3
14 P0_5
15 P0_4
12 P0_7
13 P0_6
11 P1_0
10 DVDD2
20 RESET_N
SCL
P2_4/XOSC32K_Q1 32
GND
P2_3/XOSC32K_Q2 33
1
2
DVDD1 39
DCOUPL 40
C321
AVDD5
21
XTAL1
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
C231
C221
(1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is in
the standby state (Vol. 6 Part B Section 1.1 in [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Figure 22. CC2541 Application Circuit
Table 3. Overview of External Components (Excluding Supply Decoupling Capacitors)
Component
Description
C401
Decoupling capacitor for the internal 1.8-V digital voltage regulator
R301
Precision resistor ±1%, used for internal biasing
Value
1 µF
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2541EM,
for recommended balun.
24
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SWRS110D – JANUARY 2012 – REVISED JUNE 2013
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See 32-MHz CRYSTAL OSCILLATOR for details. The load capacitance seen by the 32-MHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C221 C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C321 C331
(2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
References
1. Bluetooth® Core Technical Specification document, version 4.0
http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip
2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications/CC2541 System-onChip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191)
3. Current Savings in CC254x Using the TPS62730 (SWRA365).
Additional Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standardbased wireless applications for use in industrial and consumer applications. Our selection includes RF
transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the
sub-1- and 2.4-GHz frequency bands.
In addition, Texas Instruments provides a large selection of support collateral such as development tools,
technical documentation, reference designs, application expertise, customer support, third-party and university
programs.
The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance
to interact with fellow engineers from all over the world.
With a broad selection of product solutions, end application possibilities, and a range of technical support, Texas
Instruments offers the broadest low-power RF portfolio. We make RF easy!
The following subsections point to where to find more information.
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Texas Instruments Low-Power RF Web Site
•
•
•
Forums, videos, and blogs
RF design help
E2E interaction
Join us today at www.ti.com/lprf-forum.
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Texas Instruments has launched an extensive network of low-power RF development partners to help customers
speed up their application development. The network consists of recommended companies, RF consultants, and
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Spacer
REVISION HISTORY
Changes from Original (January 2012) to Revision A
•
Page
Changed data sheet status from Product Preview to Production Data ................................................................................ 1
Changes from Revision A (February 2012) to Revision B
Page
•
Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ....................................................................... 10
•
Changed Figure 22 text From: Optional 32-kHz Crystal To: 32-kHz Crystal ..................................................................... 24
Changes from Revision B (August 2012) to Revision C
Page
•
Changed the "Internal reference voltage" TYP value From 1.15 V To: 1.24 V .................................................................. 12
•
Changed pin XOSC_Q1 Pin Type From Analog O To: Analog I/O, and changed the Pin Description .............................. 17
•
Changed pin XOSC_Q2 Pin Type From Analog O To: Analog I/O .................................................................................... 17
Changes from Revision C (November 2012) to Revision D
Page
•
Changed the RF TRANSMIT SECTION, Output power TYP value From: –20 To: –23 ....................................................... 8
•
Changed the RF TRANSMIT SECTION, Programmable output power range TYP value From: 20 To: 23 ........................ 8
•
Added row 0x31 to Table 1 ................................................................................................................................................. 22
26
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CC2541F128RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC2541
F128
CC2541F128RHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC2541
F128
CC2541F256RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC2541
F256
CC2541F256RHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC2541
F256
HPA01215RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2541
F128
HPA01216RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2541
F256
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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