CC2543RHMT

CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 System-on-Chip for 2.4-GHz RF Applications FEATURES 1 • • • RF section – Single-Chip 2.4-GHz RF Transceiver and MCU – Supports 250 kbps, 500 kbps, 1 Mbps and 2 Mbps data rates – Excellent Link Budget, Enabling Long Range Without External Front-Ends – Programmable Output Power up to 5 dBm – Excellent Receiver Sensitivity (–90 dBm at 2 Mbps, –98 dBm at 250 kbps) – Suitable for Systems Targeting Compliance With Worldwide Radio Frequency Regulations: ETSI EN 300 328 and EN 300 440 Category 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) – Accurate RSSI Function Layout – Few External Components – Pin Out Suitable for Single Layer PCB Applications – Reference Designs Available – 32-pin 5-mm × 5-mm QFN (16 General I/O Pins) Package Low Power – Active Mode RX Best Performance: 21.2 mA – Active Mode TX (0 dBm): 26 mA – Power Mode 1 (5 µs Wake-Up): 235 µA – Power mode 2 (sleep timer on): 0.9 µA – Power mode 3 (External interrupts): 0.4µA – Wide Supply Voltage Range (2V to 3.6V) – Full RAM and Register Retention in All Power Modes • • Microcontroller – High-Performance and Low-Power 8051 Microcontroller Core With Code Prefetch – 32-KB Flash Program Memory – 1 KB SRAM – Hardware Debug Support – Extensive Baseband Automation, Including Auto-Acknowledgement and Address Decoding Peripherals – Two-Channel DMA with Access to all Memory Areas and Peripherals – General-Purpose Timers (One 16-Bit, Two 8-Bit) – Radio Timer, 40-Bit – IR Generation Circuitry – Several Oscillators: – 32MHz XOSC – 16MHz RCOSC – 32kHz RCOSC – 32-kHz Sleep Timer With Capture – AES Security Coprocessor – UART/SPI/I2C Serial Interface – 16 General-Purpose I/O pins (3 × 20-mA Drive Strength, Remaining pins have 4 mA Drive Strength) – Watchdog Timer – True Random-Number Generator – ADC and Analog Comparator APPLICATIONS • • • Proprietary 2.4-GHz Systems Human Interface Devices (keyboard, mouse) Consumer Electronics 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION The CC2543 is an optimized system-on-chip (SoC) solution with data rates up to 2Mbps built with low bill-ofmaterial cost. The CC2543 combines the excellent performance of a leading RF transceiver with a single-cycle 8051 compliant CPU, 32-KB in-system programmable flash memory, up to 1-KB RAM, and many other powerful features. The CC2543 has efficient power modes with RAM and register retention below 1 μA, making it highly suited for low-duty-cycle systems where ultra-low power consumption is required. Short transition times between operating modes further ensure low energy consumption. The CC2543 is compatible with the CC2541/CC2544/CC2545. It comes in a 5-mm × 5-mm QFN32 package, with SPI/UART/I2C interface. The CC2543 comes complete with reference designs from Texas Instruments. The device targets wireless consumer and HID applications. The CC2543 is tailored for peripheral devices such as wireless mice. For block diagram, see Figure 7. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltage VDD All supply pins must have the same voltage Voltage on any digital pin MIN MAX –0.3 3.9 –0.3 VDD + 0.3 ≤ 3.9 Input RF level (1) (2) V V 10 dBm 125 °C All pins, excluding 20 and 21, according to human-body model, JEDEC STD 22, method A114 (HBM) 2.5 kV All pins, according to human-body model, JEDEC STD 22, method A114 (HBM) 1.5 kV According to charged-device model, JEDEC STD 22, method C101 (CDM) 750 V Storage temperature range ESD (2) UNIT –40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. CAUTION: ESD sensitive device. Precaution should be used when handing the device in order to prevent permanent damage. RECOMMENDED OPERATING CONDITIONS Operating ambient temperature range, TA Operating supply voltage VDD 2 All supply pins must have same voltage Submit Documentation Feedback MIN MAX –40 85 UNIT °C 2 3.6 V Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS Measured on Texas Instruments CC2543EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2 Mbps, GFSK, 320-kHz deviation RX mode, no peripherals active, low MCU activity I core– Core current consumption I peri– Peripheral current consumption (Adds to core current Icore for each peripheral unit activated) 21.2 mA TX mode, 0-dBm output power, no peripherals active, low MCU activity 26 mA TX mode, 5-dBm output power, no peripherals active, low MCU activity 29.4 mA Active mode, 16-MHz RCOSC, Low MCU activity 3 mA Active mode, 32-MHz clock frequency, low MCU activity 6 mA Power mode 0, CPU clock halted, all peripherals on, no clock division, 32-MHz crystal selected 4.5 mA Power mode 0, CPU clock halted, all peripherals on, clock division at max (Limits max speed in peripherals except radio), 32-MHz crystal selected 3.1 mA Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-MHz crys tal oscillator off; 32.753-kHz RCOSC, POR, BOD, and sleep timer active; RAM and register retention 235 µA Power mode 2. Digital regulator off, 16 MHz RCOSC and 32 MHz crystal oscillator off; 32.753 kHz RCOSC, POR and sleep timer active; RAM and register retention 0.9 µA Power mode 3. Digital regulator off, no clocks, POR active; RAM and register retention 0.4 µA Timer 1 (16-bit). Timer running, 32-MHz XOSC used 90 µA Radio timer(40 bit). Timer running, 32-MHz XOSC used 90 µA Timer 3 (8-bit). Timer running, 32-MHz XOSC used 60 µA Timer 4 (8-bit). Timer running, 32-MHz XOSC used 70 µA Sleep timer. Including 32.753-kHz RCOSC 0.6 µA GENERAL CHARACTERISTICS Measured on Texas Instruments CC2543EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT WAKE-UP AND TIMING Power mode 1 → Active Digital regulator ON, 16-MHz RCOSC and 32-MHz crystal oscillator OFF. Start-up of 16-MHz RCOSC Power mode 2 or 3 → Active Active → TX or RX RX/TX turnaround 5 µs Digital regulator OFF, 16 MHz RCOSC and 32 MHz crystal oscillator OFF. Start-up of regulator and 16 MHz RCOSC 130 µs Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, with 32-MHz XOSC OFF 500 µs With 32-MHz XOSC initially ON 180 µs RCOSC, with 32MHz XOSC OFF 130 µs RADIO PART RF frequency range Programmable in 1-MHz steps Data rates and modulation formats 2 Mbps, GFSK 320-kHz deviation 2-Mbps, GFSK 500 kHz deviation 1-Mbps, GFSK 250 kHz deviation 1-Mbps, GFSK 160 kHz deviation 500 kbps, MSK 250 kbps, GFSK 160 kHz deviation 250 kbps, MSK 2379 2496 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 MHz 3 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com RF RECEIVE SECTION Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2 Mbps, GFSK, 320-kHz DEVIATION, 0.1% BER Receiver sensitivity Saturation Co-channel rejection Wanted signal at –67 dBm In-band blocking rejection –86 dBm –8 dBm –13 dB ±2-MHz offset, wanted signal at –67 dBm –1 ±4-MHz offset, wanted signal at –67 dBm 34 >±6-MHz offset, wanted signal at –67 dBm 38 dB 1-MHz resolution. Wanted signal at –67 dBm, f < 2 GHz Two exception frequencies with poorer performance –32 1-MHz resolution. Wanted signal at –67 dBm, 2 GHz > f < 3 GHz Two exception frequencies with poorer performance –38 1-MHz resolution. Wanted signal at –67 dBm, f > 3GHz Two exception frequencies with poorer performance –12 Intermodulation Wanted signal at –64 dBm, 1st interferer is CW, 2nd interferer is GFSKmodulated signal. Offsets of interferers are: 6 and 12 MHz 8 and 16 MHz 10 and 20 MHz –43 Frequency error tolerance (1) Including both initial tolerance and drift. Sensitivity better than –70 dBm. 250 byte payload. –300 300 kHz Symbol rate error tolerance (2) Sensitivity better than -70 dBm. 250 byte payload. –120 120 ppm Out-of-band blocking rejection dBm dBm 2 Mbps, GFSK, 500 kHz DEVIATION, 0.1% BER Receiver sensitivity Saturation Co-channel rejection Frequency error tolerance (1) Symbol rate error tolerance (2) dBm –3 dBm –10 dB ±2 MHz offset, wanted signal at –67 dBm –3 dB ±4 MHz offset, wanted signal at –67 dBm 36 dB >±6 MHz offset, wanted signal at –67 dBm 44 dB Wanted signal at –67 dBm In-band blocking rejection –90 Including both initial tolerance and drift. Sensitivity better than –70 dBm. 250 byte payload. –300 300 kHz Sensitivity better than -70 dBm. 250 byte payload. –120 120 ppm 1 Mbps, GFSK, 250 kHz DEVIATION, 0.1% BER Receiver sensitivity Saturation Co-channel rejection In-band blocking rejection Wanted signal at –67 dBm 6 dBm –7 dB 0 ±2 MHz offset, wanted signal –67 dBm 30 ±3 MHz offset, wanted signal –67 dBm 34 >±5 MHz offset, wanted signal –67 dBm 38 Frequency error tolerance Symbol rate error tolerance Sensitivity better than –70 dBm. 250 byte payload. 4 dBm ±1 MHz offset, wanted signal –67 dBm Including both initial tolerance and drift. Sensitivity better than –70 dBm. 250 byte payload. (1) (2) –94 dB –250 250 kHz -80 80 ppm Difference between center frequency of the received RF signal and local oscillator frequency Difference between incoming symbol rate and the internally generated symbol rate Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 RF RECEIVE SECTION (continued) Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1 Mbps, GFSK, 160 kHz DEVIATION, 0.1% BER Receiver sensitivity Saturation Co-channel rejection In band blocking rejection Wanted signal at –67 dBm –91 dBm 6 dBm –8 dB ±1 MHz offset, wanted signal at –67 dBm 2 ±2 MHz offset, wanted signal at –67 dBm 28 ±3 MHz offset, wanted signal at –67 dBm 33 >±5 MHz offset, wanted signal at –67 dBm 36 Frequency error tolerance Including both initial tolerance and drift, Sensitivity better than –67 dBm Symbol rate error tolerance Maximum packet length dB –250 250 kHz –80 80 ppm 500 kbps, MSK, 0.1% BER Receiver sensitivity –98 dBm 6 dBm Wanted signal at –67 dBm –5 dB ±1 MHz offset, wanted signal at –67 dBm 21 ±2 MHz offset, wanted signal at –67 dBm 32 >±2 MHz offset, wanted signal at –67 dBm 33 Saturation Co-channel rejection In band blocking rejection Frequency error tolerance Including both initial tolerance and drift, Sensitivity better than –67dBm Symbol rate error tolerance Maximum packet length dB –150 150 kHz –60 60 ppm 250 kbps, GFSK, 160 kHz DEVIATION , 0.1% BER Receiver sensitivity Saturation Co-channel rejection In-band blocking rejection –98 dBm 6 dBm Wanted signal at –67 dBm –2 dB ±1 MHz offset, wanted signal at –67 dBm 22 ±2 MHz offset, wanted signal at –67 dBm 32 >±2 MHz offset, wanted signal at –67 dBm dB 32 Frequency error tolerance Including both initial tolerance and drift, Sensitivity better than –67 dBm Symbol rate error tolerance Maximum packet length –150 150 kHz –60 60 ppm 250 kbps, MSK, 0.1% BER Receiver sensitivity –98 dBm 6 dBm Wanted signal at –67 dBm –5 dB ±1 MHz offset, wanted signal at –67 dBm 21 ±2 MHz offset, wanted signal at –67 dBm 32 >2 MHz offset, wanted signal at –67 dBm 33 Saturation Co-channel rejection In-band blocking rejection Frequency error tolerance Including both initial tolerance and drift, Sensitivity better than –67 dBm Symbol rate error tolerance Maximum packet length dB –150 150 kHz –60 60 ppm ALL RATES/FORMATS Spurious emission in RX. Conducted measurement f < 1 GHz –67 dBm Spurious emission in RX. Conducted measurement f > 1 GHz –60 dBm Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 5 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com RF TRANSMIT SECTION Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output power, maximum setting Delivered to a single-ended 50-Ω load through a balun using maximum recommended output power setting. 5 dBm Output power, minimum setting Delivered to a single-ended 50-Ω load through a balun using minimum recommended output power setting. –20 dBm 25 dB f < 1 GHz –46 dBm f > 1 GHz –46 dBm Programmable output power range Delivered to a single-ended 50-Ω load through a balun. Spurious emission in TX. Conducted measurement Suitable for Systems Targeting Compliance With Worldwide Radio Frequency Regulations: ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) Use a simple LC filter (1.6nH and 1.8pF in parallel to ground) to pass ETSI conducted requirements below 1GHz in restricted bands. For radiated measurements low antenna gain for these frequencies (depending on antenna design) can achieve the same attenuation of these low frequency components (see EM reference design). 32-MHz CRYSTAL OSCILLATOR Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN Crystal frequency TYP MAX 32 MHz –30 –40 –60 30 40 60 Equivalent series resistance 6 60 Ω Crystal shunt capacitance 1 7 pF Crystal load capacitance 10 16 pF Crystal frequency accuracy requirement 250 kbps and 500 kbps data rates 1 Mbps data rate 2 Mbps data rate UNIT Start-up time 0.25 Power-down guard time The crystal oscillator must be in power down for a guard time before it is used again. This requirement is valid for all modes of operation. The need for power-down guard time can vary with crystal type and load. ppm ms 3 ms 32-kHz RC OSCILLATOR Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP Calibrated frequency 32.753 Frequency accuracy after calibration ±0.2% Temperature coefficient MAX UNIT kHz 0.4 %/ºC Supply-voltage coefficient 3 %/V Calibration time 2 ms 16-MHz RC OSCILLATOR Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted. PARAMETER TEST CONDITIONS Calibrated frequency MIN TYP 16 Uncalibrated frequency accuracy ±18% Frequency accuracy after calibration ±0.6% MAX UNIT MHz Start-up time 10 µs Initial calibration time 50 µs 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 RSSI CHARACTERISTICS Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted. 2Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER RSSI range (1) RSSI offset (1) Reduced gain by AC algorithm 64 High gain by AGC algorithm 64 Reduced gain by AGC algorithm 79 High gain by AGC algorithm 99 dB dBm Absolute uncalibrated accuracy (1) ±3 dB Step size (LSB value) 1 dB All Other Rates/Formats RSSI range (1) 64 dB RSSI offset (1) 99 dBm Absolute uncalibrated accuracy ±3 dB Step size (LSB value) 1 dB (1) Assuming CC2543 EM reference design. Other RF designs give an offset from the reported value. FREQUENCY SYNTHESIZER CHARACTERISTICS Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted. PARAMETER TEST CONDITIONS Phase noise, unmodulated carrier MIN TYP At ±1 MHz from carrier –112 At ±3 MHz from carrier –119 At ±5 MHz from carrier –122 MAX UNIT dBc/Hz ANALOG TEMPERATURE SENSOR Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V unless otherwise noted PARAMETER TEST CONDITIONS Output Temperature coefficient Voltage coeficcient MIN TYP MAX UNIT 1480 12-bit 4.5 / 1ºC 1 / 0.1V ±10 ºC Accuracy using 1-point calibration ±5 ºC Current consumption when enabled 0.5 mA Initial accuracy without calibration Measured using integrated ADC, internal band-gap voltage reference, and maximum resolution COMPARATOR CHARACTERISTICS TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2543 reference designs, post-calibration. PARAMETER TEST CONDITIONS MIN TYP MAX Common-mode maximum voltage VDD Common-mode minimum voltage –0.3 Input offset voltage Offset vs temperature Offset vs operating voltage UNIT V 1 mV 16 µV/°C 4 mV/V Supply current 230 nA Hysteresis 0.15 mV Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 7 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com ADC CHARACTERISTICS TA = 25°C and VDD = 3 V PARAMETER ENOB (1) TEST CONDITIONS MIN VDD is voltage from supply 0 VDD V VDD is voltage from supply 0 VDD V External reference voltage differential VDD is voltage from supply 0 VDD Simulated using 4-MHz clock speed 197 kΩ Full-scale signal (1) Peak-to-peak, defines 0 dBFS 2.97 V Effective number of bits Single-ended input, 7-bit setting 5.7 Single-ended input, 9-bit setting 7.5 Single-ended input, 10-bit setting 9.3 Single-ended input, 12-bit setting 10.3 Differential input, 7-bit setting 6.5 Differential input, 9-bit setting 8.3 Differential input, 10-bit setting 10 Differential input, 12-bit setting 11.5 Signal to nonharmonic ratio 12-bit setting, clocked by RCOSC 10.9 7-bit setting, both single and differential 0–20 Single ended input, 12-bit setting, –6 dBFS (1) –75.2 Differential input, 12-bit setting, –6 dBFS (1) –86.6 79.3 Single-ended input, 12-bit setting, –6 dBFS (1) 78.8 dB 88.9 Common-mode rejection ratio Differential input, 12-bit setting, 1-kHz sine (0 dBFS), limited by ADC resolution >84 dB Crosstalk Single ended input, 12-bit setting, 1-kHz sine (0 dBFS), limited by ADC resolution >84 dB Offset Midscale –3 mV Differential nonlinearity 0.68% 12-bit setting, mean (1) 0.05 (1) 0.9 12-bit setting, maximum (1) 13.3 12-bit setting, maximum Integral nonlinearity Signal-to-noise-and-distortion Conversion time LSB 4.6 12-bit setting, mean, clocked by RCOSC 12-bit setting, max, clocked by RCOSC 8 dB Differential input, 12-bit setting, –6 dBFS (1) 12-bit setting, mean (1) (1) kHz 70.2 Differential input, 12-bit setting (1) Gain error SINAD (–THD+N) bits 9.7 Single-ended input, 12-bit setting (1) INL V Input resistance, signal Total harmonic distortion DNL UNIT External reference voltage Useful power bandwidth CMRR MAX Input voltage 10-bit setting, clocked by RCOSC THD TYP 10 LSB 29 Single ended input, 7-bit setting (1) 35.4 Single ended input, 9-bit setting (1) 46.8 Single ended input, 10-bit setting (1) 57.5 Single ended input, 12-bit setting (1) 66.6 Differential input, 7-bit setting (1) 40.7 Differential input, 9-bit setting (1) 51.6 Differential input, 10-bit setting (1) 61.8 Differential input, 12-bit setting (1) 70.8 7-bit setting 20 9-bit setting 36 10-bit setting 68 12-bit setting 132 dB μs Measured with 300-Hz sine-wave input and VDD as reference. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 ADC CHARACTERISTICS (continued) TA = 25°C and VDD = 3 V PARAMETER TEST CONDITIONS MIN TYP Power consumption MAX UNIT 1.2 Internal reference VDD coefficient mA 4 Internal reference temperature coefficient Internal reference voltage mV/V 0.4 mV/10°C 1.15 V DC CHARACTERISTICS Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 V Logic-0 input voltage Logic-1 input voltage 2.5 Logic-0 input current –50 50 nA V Logic-1 input current –50 50 nA I/O pin pullup and pulldown resistors 20 Logic-0 output voltage 4-mA pins Output load 4 mA Logic-1 output voltage 4-mA pins Output load 4 mA Logic-0 output voltage 20-mA pins Output load 20 mA Logic-1 output voltage 20-mA pins Output load 20 mA (1) kΩ 0.5 V 2.4 V 0.5 V 2.4 V Note that only two of the three 20mA pins can drive in the same direction at the same time, and toggle at the same time. CONTROL INPUT AC CHARACTERISTICS TA = –40°C to 85°C, VDD = 2 V to 3.6 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 32 MHz System clock, fSYSCLK tSYSCLK = 1/ fSYSCLK The undivided system clock is 32 MHz when crystal oscillator is used. The undivided system clock is 16 MHz when calibrated 16-MHz RC oscillator is used. RESET_N low duration See item 1, Figure 1. This is the shortest pulse that is recognized as a complete reset pin request. Note that shorter pulses may be recognized but do not lead to complete reset of all modules within the chip. 1 µs Interrupt pulse duration See item 2, Figure 1.This is the shortest pulse that is recognized as an interrupt request. 20 ns 16 RESET_N 1 2 Px.n T0299-01 Figure 1. Control Input AC Characteristics Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 9 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com SPI AC CHARACTERISTICS TA = –40°C to 85°C, VDD = 2 V to 3.6 V PARAMETER t1 TEST CONDITIONS SCK period SCK duty cycle MIN Master, RX and TX 250 Slave, RX and TX 250 Master TYP MAX UNIT ns 50% Master 63 Slave 63 Master 63 Slave 63 t2 SSN low to SCK, Figure 2 and Figure 3 t3 SCK to SSN high t4 MOSI early out Master, load = 10 pF 7 ns t5 MOSI late out Master, load = 10 pF 10 ns t6 MISO setup Master 90 t7 MISO hold Master 10 SCK duty cycle Slave t10 MOSI setup Slave 35 ns t11 MOSI hold Slave 10 ns t8 MISO early out Slave, load = 10 pF 0 ns t9 MISO late out Slave, load = 10 pF 95 ns Operating frequency ns ns ns ns 50% ns Master, TX only 8 Master, RX and TX 4 Slave, RX only 8 Slave, RX and TX 4 MHz SCK t2 t3 SSN t4 D0 MOSI t6 MISO X t5 X D1 t7 D0 X T0478-01 Figure 2. SPI Master AC Characteristics 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 SCK t2 t3 SSN t8 D0 MISO X t10 MOSI X t9 D1 t11 D0 X T0479-01 Figure 3. SPI Slave AC Characteristics DEBUG INTERFACE AC CHARACTERISTICS TA = –40°C to 85°C, VDD = 2 V to 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 12 MHz fclk_dbg Debug clock frequency (see Figure 4) t1 Allowed high pulse on clock (see Figure 4) 35 ns t2 Allowed low pulse on clock (see Figure 4) 35 ns t3 EXT_RESET_N low to first falling edge on debug clock (see Figure 5) 167 ns t4 Falling edge on clock to EXT_RESET_N high (see Figure 5) 83 ns t5 EXT_RESET_N high to first debug command (see Figure 5) 83 ns t6 Debug data setup (see Figure 6) 2 ns t7 Debug data hold (see Figure 6) 4 ns t8 Clock-to-data delay (see Figure 6) Load = 10 pF 30 ns Time DEBUG_ CLK P2_2 t1 t2 1/fclk_dbg T0436-01 Figure 4. Debug Clock – Basic Timing Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 11 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com Time DEBUG_ CLK P2_2 RESET_N t3 t4 t5 T0437-01 Figure 5. Debug Enable Timing Time DEBUG_ CLK P2_2 DEBUG_DATA (to CC2543) P2_1 DEBUG_DATA (from CC2543) P2_1 t6 t8 t7 T0438-03 Figure 6. Data Setup and Hold Timing TIMER INPUTS AC CHARACTERISTICS TA = –40°C to 85°C, VDD = 2 V to 3.6 V PARAMETER Input capture pulse duration 12 TEST CONDITIONS MIN Synchronizers determine the shortest input pulse that can be recognized. The synchronizers operate at the current system clock rate (16 MHz or 32 MHz). 1.5 Submit Documentation Feedback TYP MAX UNIT tSYSCLK Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 DEVICE INFORMATION PIN DESCRIPTIONS RBIAS 28 27 26 25 P1_1 P1_2 32 31 30 29 P1_0 VDD DCPL1 VSS P1_4 CC2543 RHB Package (Top View) 24 VDD P2_1/DD 2 23 VDD P2_0 3 22 VSS P0_7 4 21 RF_N P0_6 5 20 RF_P P0_5 6 19 VSS P0_4 7 18 VDD P0_3 8 17 XOSC_Q2 XOSC_Q1 VDD P2_2/DC RESET_N VDD 10 11 12 13 14 15 16 P0_0 9 P0_1 1 P0_2 P1_3 NOTE: The exposed ground pad must be connected to a solid ground plane; this is the main ground connection for the chip. Table 1. Pin Description Table NAME PIN P1_3 1 Digital I/O PIN TYPE Port 1.3 DESCRIPTION P2_1/DD 2 Digital I/O / Debug Port 2.1 / Debug Data P2_0 3 Digital I/O Port 2.0 P0_7 4 Digital I/O Port 0.7 P0_6 5 Digital I/O Port 0.6 P0_5 6 Digital I/O Port 0.5 P0_4 7 Digital I/O Port 0.4 P0_3 8 Digital I/O Port 0.3 P0_2 9 Digital I/O Port 0.2 P0_1 10 Digital I/O Port 0.1 P0_0 11 Digital I/O Port 0.0 VDD 12 Power (analog) 2-V-3.6V analog power-supply connection RESET_N 13 Digital input Reset, active-low P2_2/DC 14 Digital I/O / Debug Port 2.2 / Debug Clock VDD 15 Power (analog) 2-V-3.6V analog power-supply connection XOSC_Q1 16 Analog O 32-MHz crystal oscillator pin 1 XOSC_Q2 17 Analog O 32-MHz crystal oscillator pin 2 VDD 18 Power (analog) 2-V-3.6V analog power-supply connection VSS 19 Unused pin Connect to ground RF_P 20 RF I/O Positive RF input signal to LNA during RX Positive RF output signal from PA during TX Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 13 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com Table 1. Pin Description Table (continued) 14 NAME PIN RF_N 21 RF I/O PIN TYPE Negative RF input signal to LNA during RX Negative RF output signal from PA during TX DESCRIPTION VSS 22 Unused pin Connect to ground VDD 23 Power (analog) 2-V–3.6-V analog power-supply connection VDD 24 Power (analog) 2-V–3.6-V analog power-supply connection RBIAS 25 Analog I/O External precision bias resistor for reference current P1_2 26 Digital I/O Port 1.2, 20 mA P1_1 27 Digital I/O Port 1.1, 20 mA P1_0 28 Digital I/O Port 1.0, 20 mA VDD 29 Power (analog) 2-V–3.6-V analog power-supply connection DCPL1 30 Power (digital) 1.8-V digital power-supply decoupling. Do not use for supplying external circuits. VSS 31 Unused pin Connect to ground P1_4 32 Digital I/O Port 1.4 VSS Ground pad Ground Must be connected to solid ground as this is the main ground connection for the chip. See Pinout Diagram. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 BLOCK DIAGRAM A block diagram of the CC2543 is shown in Figure 7. The modules can be roughly divided into one of three categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related modules. In the following subsections, a short description of each module is given. See CC2543/44/45 User's Guide (SWRU283) for more details. XOSC_Q2 32-MHz CRYSTAL OSC HIGHSPEED RC-OSC DEBUG INTERFACE VDD (2 V–3.6 V) ON-CHIP VOLTAGE REGULATOR CLOCK MUX and CALIBRATION SFR Bus RESET XOSC_Q1 POWER ON RESET BROWN OUT WATCHDOG TIMER RESET_N DCOUPL SLEEP TIMER 32-kHz RC-OSC POWER MANAGEMENT CONTROLLER P2_2 PDATA P2_1 P2_0 XRAM 8051 CPU CORE IRAM P1_4 SFR RAM SRAM FLASH FLASH MEMORY ARBITRATOR P1_3 P1_2 DMA P1_1 UNIFIED P1_0 IRQ CTRL FLASH CTRL P0_7 P0_6 SRAM FIFOCTRL ANALOG COMPARATOR P0_5 P0_2 Radio Arbiter PSEUDO RANDOM NUMBER GENERATOR P0_3 AES ENCRYPTION AND DECRYPTION ΔΣ ADC AUDIO/DC RADIO REGISTERS Link Layer Engine SFR Bus P0_0 I/O CONTROLLER P0_1 ROM DEMODULATOR SYNTH P0_4 MODULATOR SDA SCL 2 I C RECEIVE TIMER 1 (16-Bit) FREQUENCY SYNTHESIZER USART 0 TRANSMIT TIMER 2 (RADIO TIMER) TIMER 3 (8-Bit) DIGITAL RF_P RF_N ANALOG TIMER 4 (8-Bit) MIXED B0301-12 Figure 7. CC2543 Block Diagram Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 15 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com BLOCK DESCRIPTIONS CPU and Memory The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR, DATA, and CODE/XDATA), a debug interface, and an 15-input extended interrupt unit. The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory. The SFR bus is drawn conceptually in Figure 7 as a common bus that connects all hardware peripherals to the memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio register bank, even though these are indeed mapped into XDATA memory space. The 1-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The 18-KB/32-KB flash block provides in-circuit programmable non-volatile program memory for the device, and maps into the CODE and XDATA memory spaces. Peripherals Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise programming. See User Guide for details on the flash controller. A versatile two-channel DMA controller is available in the system, accesses memory using the XDATA memory space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USART, timers, etc.) can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or XREG address and flash/SRAM. The interrupt controller services a total of 17 interrupt sources, divided into six interrupt groups, each of which is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (when in sleep mode, the device is in low-power mode PM1, PM2 or PM3). The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging. Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051 core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform in-circuit debugging and external flash programming elegantly. The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral modules control certain pins or whether they are under software control, and if so, whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects to the I/O pins can choose between several different I/O pin locations to ensure flexibility in various applications. The sleep timer is an ultralow-power timer that uses an internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power modes 1 or 2. A built-in watchdog timer allows the CC2543 to reset itself if the firmware hangs. When enabled by software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction. 16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 Timer 2 is a 40-bit timer used by the Radio. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which a packet ends. There are two 16-bit timer-compare registers and two 24-bit overflowcompare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts. Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter channels can be used as PWM output. USART 0 is configurable as either an SPI master/slave or a UART. It provides double buffering on both RX and TX and hardware flow control and is thus well suited to high-throughput full-duplex applications. The USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured as SPI slaves, the USART samples the input signal using SCK directly instead of using some oversampling scheme, and are thus well-suited for high data rates. The I2C module provides a digital peripheral connection with two pins and supports both master and slave operation. The ADC supports 7 bits (30 kHz bandwidth) to 12 bits (4 kHz bandwidth) of resolution. DC and audio conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling or conversion over a sequence of channels. The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware support for CCM. The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator output is mapped into the digital I/O port and can be treated by the MCU as a regular digital input. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 17 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS RX CURRENT vs TEMPERATURE TX CURRENT vs TEMPERATURE 32 24 31 Current (mA) 23 Current (mA) 3-V Supply TXPOWER Setting = 0xE5 3-V Supply Standard Gain Setting −70 dBm Input 2 Mbps, GFSK, 320 kHz deviation 22 21 19 −40 −20 0 20 40 Temperature (°C) 60 27 −40 80 20 40 Temperature (°C) Figure 9. RX SENSITIVITY vs TEMPERATURE TX POWER vs TEMPERATURE 60 80 G002 10 3-V Supply TXPOWER Setting = 0xE5 −82 8 Power Level (dBm) Sensitivity Level (dBm) 0 Figure 8. 3-V Supply Standard Gain Setting 2 Mbps, GFSK, 320 kHz deviation −84 −86 6 4 2 −88 −90 −40 −20 0 20 40 Temperature (°C) 60 0 −40 80 −20 0 G003 20 40 Temperature (°C) Figure 10. Figure 11. RX CURRENT vs SUPPLY VOLTAGE TX CURRENT vs SUPPLY VOLTAGE 24 60 80 G004 32 TA = 25°C Standard Gain Setting −70 dBm Input 2 Mbps, GFSK, 320 kHz deviation TA = 25°C TXPOWER Setting = 0xE5 31 Current (mA) 23 22 21 30 29 28 20 27 2 2.2 2.4 2.6 2.8 3 Supply Voltage (V) 3.2 3.4 3.6 2 G005 Figure 12. 18 −20 G001 −80 Current (mA) 29 28 20 19 30 2.2 2.4 2.6 2.8 3 Supply Voltage (V) 3.2 3.4 3.6 G006 Figure 13. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) RX SENSITIVITY vs SUPPLY VOLTAGE TX POWER vs SUPPLY VOLTAGE 10 TA = 25°C TXPOWER Setting = 0xE5 TA = 25°C Standard Gain Setting 2 Mbps, GFSK, 320 kHz deviation −82 8 Power Level (dBm) Sensitivity Level (dBm) −80 −84 −86 0 2 2.2 2.4 2.6 2.8 3 Supply Voltage (V) 3.2 3.4 3.6 2.2 2.4 2.6 2.8 3 Supply Voltage (V) Figure 14. Figure 15. RX SENSITIVITY vs FREQUENCY TX POWER vs FREQUENCY 3.2 3.4 3.6 G008 10 3-V Supply TA = 25°C Standard Gain Setting 2 Mbps, GFSK, 320 kHz deviation 8 Power Level (dBm) Sensitivity Level (dBm) 2 G007 −80 −82 4 2 −88 −90 6 −84 −86 6 4 2 −88 −90 2400 3-V Supply TA = 25°C TXPOWER Setting = 0xE5 2420 2440 2460 Frequency (MHz) 0 2400 2480 2420 2440 2460 Frequency (MHz) G009 Figure 16. 2480 G011 Figure 17. RX INTERFERER REJECTION (SELECTIVITY) vs INTERFERER FREQUENCY 0 −10 Rejection (dBm) −20 −30 −40 −50 3-V Supply TA = 25°C Standard Gain Setting Wanted Signal at 2440 MHz with −67 dBm Level −60 −70 −80 −90 2400 2420 2440 2460 Frequency (MHz) 2480 G010 Figure 18. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 19 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Table 2. Recommended Output Power Settings (1) (1) 20 TXPOWER Register Setting Typical Output Power (dBm) 0xE5 5 0xD5 4 0xC5 3 0xB5 2 0xA5 0 0x95 –2 0x85 –3 0x75 –4 0x65 –6 0x55 –8 0x45 –11 0x35 –13 0x25 –15 0x15 –17 0x05 –20 Measured on Texas Instruments CC2543 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz. See SWRU283 for recommended register settings. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 CC2543 www.ti.com SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 APPLICATION INFORMATION Few external components are required for the operation of the CC2543. A typical application circuit is shown in Figure 19. For suggestions of component values other than those listed in Table 3, see reference design CC2543EM. The performance stated in this data sheet is only valid for the CC2543EM reference design. To obtain similar performance, the reference design should be copied as closely as possible. C301 2-V–3.6-V Power Supply RBIAS 25 P1_2 26 P1_1 27 VDD 29 P1_0 28 VSS 31 DCPL1 30 P1_4 32 R251 Antenna (50 W) 1 P1_3 VDD 24 2 P2_1/DD VDD 23 3 P2_0 VSS 22 4 P0_7 RF_N 21 5 P0_6 6 P0_5 7 P0_4 8 P0_3 CC2543 RF_P 20 DIE ATTACH PAD VSS 19 16 XOSC_Q1 14 P2_2/DC 15 VDD 13 RESET_N 12 VDD 11 P0_0 10 P0_1 9 P0_2 VDD 18 XOSC_Q2 17 C171 C161 Power Supply Decoupling Capacitors are Not Shown Digital I/O Not Connected S0383-08 Figure 19. CC2543 Application Circuit Table 3. Overview of External Components (Excluding Balun, Crystal and Supply Decoupling Capacitors) COMPONENT DESCRIPTION C301 Decoupling capacitor for the internal 1.8V digital voltage regulator R251 Precision resistor ±1%, used for internal biasing VALUE 1 µF 56 kΩ Input/Output Matching When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2543EM, for recommended balun. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 21 CC2543 SWRS107E – APRIL 2012 – REVISED OCTOBER 2013 www.ti.com Crystal An external 32-MHz crystal with two loading capacitors is used for the 32-MHz crystal oscillator. The load capacitance seen by the 32-MHz crystal is given by: 1 + Cparasitic CL = 1 1 + C161 C171 (1) A series resistor may be used to comply with ESR requirement. On-Chip 1.8-V Voltage Regulator Decoupling The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor (C301) for stable operation. Power-Supply Decoupling and Filtering Proper power-supply decoupling must be used for optimum performance. The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application. TI provides a compact reference design that should be followed very closely. SPACER REVISION HISTORY Changes from Original (April 2012) to Revision A • Page Changed data sheet status from Product Preview to Production Data ................................................................................ 1 Changes from Revision A (April 2012) to Revision B Page • Added Comparator Characteristics specifications ................................................................................................................ 7 • Added ADC Characteristics specifications ........................................................................................................................... 8 Changes from Revision B (May 2012) to Revision C • Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ......................................................................... 7 Changes from Revision C (August 2012) to Revision D • 22 Page Changed the Pin Package From: RHM to: RHB ................................................................................................................. 13 Changes from Revision D (November 2012) to Revision E • Page Page Changed the ADC CHARACTERISTICS Test Conditions From: VDD is voltage on AVDD5 pin To: VDD is voltage from supply ........................................................................................................................................................................... 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links :CC2543 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CC2543RHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CC2543 CC2543RHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CC2543 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of