CC2662R-Q1
SWRS259C – DECEMBER 2020 – REVISED JULY 2023
CC2662R-Q1 SimpleLink™ Wireless BMS MCU
1 Features
Wireless microcontroller
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Powerful 48-MHz Arm® Cortex®-M4F processor
EEMBC CoreMark® score: 148
352KB flash program memory
256KB of ROM for protocols and library functions
8KB of cache SRAM
80KB of ultra-low leakage SRAM with parity for
high-reliability operation
2-pin cJTAG and JTAG debugging
Supports over-the-air upgrade (OTA)
Programmable radio supporting SimpleLink™
WBMS
High performance radio
•
•
–92 dBm RX sensitivity for proprietary WBMS
protocol
Output power up to +5 dBm with temperature
compensation
Regulatory compliance
•
Suitable for systems targeting compliance with
these standards:
– ETSI EN 300 328, EN 300 440 Cat. 2 and 3
– FCC CFR47 Part 15
– ARIB STD-T66
MCU peripherals
Qualified for automotive application
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Security enablers
Ultra-low power sensor controller
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Autonomous MCU with 4KB of SRAM
Sample, store, and process sensor data
Fast wake-up for low-power operation
Software defined peripherals; capacitive touch,
flow meter, LCD
AEC-Q100 qualified with the following results:
– Device temperature grade 2: –40°C to +105°C
ambient operating temperature range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C3
Functional Safety Quality-Managed
– Documentation available to aid functional safety
system design
Low power consumption
•
•
•
MCU consumption:
– 3.4 mA active mode, CoreMark®
– 71 μA/MHz running CoreMark®
– 0.94 μA standby mode, RTC, 80KB RAM
– 0.15 μA shutdown mode, wake-up on pin
Ultra low-power sensor controller consumption:
– 31.9 μA in 2 MHz mode
– 808.5 μA in 24 MHz mode
Radio consumption
– 6.9 mA RX
– 7.0 mA TX at 0 dBm
– 9.2 mA TX at +5 dBm
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Digital peripherals can route to any of 31 GPIOs
Four 32-bit or eight 16-bit general-purpose timers
12-bit ADC, 200 kSamples/s, 8 channels
8-bit DAC
Two comparators
Two UART, Two SSI, I2C, I2S
Real-time clock (RTC)
Integrated temperature and battery monitor
AES 128- and 256-bit cryptographic accelerator
ECC and RSA public key hardware accelerator
SHA2 Accelerator (full suite up to SHA-512)
True random number generator (TRNG)
Development tools and software
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CC2662RQ1-EVM-WBMS Development Kit
SimpleLink™ WBMS Software Development Kit
SmartRF™ Studio for simple radio configuration
Sensor Controller Studio for building low-power
sensing applications
SysConfig system configuration tool
Operating range
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On-chip buck DC/DC converter
1.8-V to 3.63-V single supply voltage
-40 to +105°C
Package
•
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7-mm × 7-mm RGZ VQFN48 with wettable flanks
(31 GPIOs)
RoHS-compliant package
Wireless protocol support
•
SimpleLink™ WBMS
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC2662R-Q1
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SWRS259C – DECEMBER 2020 – REVISED JULY 2023
2 Applications
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•
– Wireless battery management system (BMS)
Cable replacement
Automotive
3 Description
The SimpleLink™ 2.4 GHz CC2662R-Q1 device is an AEC-Q100 compliant wireless microcontroller (MCU)
targeting wireless automotive applications. The device is optimized for low-power wireless communication in
applications such as battery management systems (BMS) and cable replacement. The highlighted features of
this device include:
• Support for TI's SimpleLink wireless BMS (WBMS) protocol for robust, low latency and high throughput
communication.
• Functional Safety Quality-Managed classification including TI quality-managed development process and
forthcoming functional safety FIT rate calculation, FMEDA and functional safety documentation.
• AEC-Q100 qualified for Grade 2 temperature range (–40 °C to +105 °C) and is offered in a
7-mm x 7-mm VQFN package with wettable flanks.
• Low standby current of 0.94 μA with full RAM retention.
• Excellent radio link budget of 97 dBm.
The CC2662R-Q1 device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth Low
Energy, Thread, Zigbee®, Sub-1 GHz MCUs, and host MCUs that all share a common, easy-to-use development
environment and rich tool set. For more information, visit SimpleLink™ MCU platform.
Device Information(1)
(1)
2
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CC2662R1FTWRGZRQ1
VQFN (48)
7.00 mm × 7.00 mm
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum or see the TI
website.
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4 Functional Block Diagram
2.4 GHz
RF Core
cJTAG
Main CPU
256KB
ROM
ADC
ADC
Arm®
Cortex®-M4F
Processor
Up to
352KB
Flash
with 8KB
Cache
48 MHz
71 µA/MHz (3.0 V)
Up to
80KB
SRAM
with Parity
Digital PLL
DSP Modem
16KB
SRAM
Arm®
Cortex®-M0
Processor
General Hardware Peripherals and Modules
ROM
Sensor Interface
I2C and I2S
4× 32-bit Timers
Sensor Controller
2× UART
2× SSI (SPI)
8-bit DAC
32 ch. µDMA
Watchdog Timer
12-bit ADC, 200 ks/s
31 GPIOs
TRNG
2x Low-Power Comparator
AES-256, SHA2-512
Temperature and
Battery Monitor
SPI-I2C Digital Sensor IF
ECC, RSA
RTC
Capacitive Touch IF
Time-to-Digital Converter
LDO, Clocks, and References
Optional DC/DC Converter
4KB SRAM
Figure 4-1. CC2662R-Q1 Block Diagram
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SWRS259C – DECEMBER 2020 – REVISED JULY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 4
6 Device Comparison......................................................... 5
7 Terminal Configuration and Functions..........................6
7.1 Pin Diagram – RGZ Package (Top View)....................6
7.2 Signal Descriptions..................................................... 7
7.3 Connections for Unused Pins and Modules................8
8 Specifications.................................................................. 9
8.1 Absolute Maximum Ratings........................................ 9
8.2 ESD Ratings............................................................... 9
8.3 Recommended Operating Conditions.........................9
8.4 Power Supply and Modules........................................ 9
8.5 Power Consumption - Power Modes........................ 10
8.6 Power Consumption - Radio Modes......................... 11
8.7 Nonvolatile (Flash) Memory Characteristics............. 11
8.8 Thermal Resistance Characteristics......................... 11
8.9 Receive (RX) ............................................................12
8.10 Transmit (TX).......................................................... 13
8.11 Timing and Switching Characteristics..................... 13
8.12 Peripheral Characteristics.......................................18
8.13 Typical Characteristics............................................ 25
9 Detailed Description......................................................31
9.1 Overview................................................................... 31
9.2 System CPU............................................................. 31
9.3 Radio (RF Core)........................................................32
9.4 Memory..................................................................... 33
9.5 Sensor Controller...................................................... 34
9.6 Cryptography............................................................ 35
9.7 Timers....................................................................... 36
9.8 Serial Peripherals and I/O.........................................37
9.9 Battery and Temperature Monitor............................. 37
9.10 µDMA...................................................................... 37
9.11 Debug......................................................................37
9.12 Power Management................................................38
9.13 Clock Systems........................................................ 39
9.14 Network Processor..................................................39
10 Application, Implementation, and Layout................. 40
10.1 Reference Designs................................................. 40
10.2 Junction Temperature Calculation...........................41
11 Device and Documentation Support..........................42
11.1 Device Nomenclature..............................................42
11.2 Tools and Software..................................................42
11.3 Documentation Support.......................................... 44
11.4 Support Resources................................................. 44
11.5 Trademarks............................................................. 44
11.6 Electrostatic Discharge Caution.............................. 45
11.7 Glossary.................................................................. 45
12 Mechanical, Packaging, and Orderable
Information.................................................................... 46
5 Revision History
Changes from December 11, 2020 to May 19, 2023 (from Revision A (June 2022) to Revision B
(May 2023))
Page
• Changed "Radio consumption" (TX currents) in Section 1 Features .................................................................1
• Updated numbering of sections, figures, and tables throughout the data sheet................................................ 1
• Updated formatting throughout data sheet to match current documentation standards.....................................1
• Added PRODUCTION DATA.............................................................................................................................. 1
• Changed package options for CC2340R2.......................................................................................................... 5
• Changed the TYP values of the "Radio transmit current" parameter in Section 8.6 Power Consumption Radio Modes ....................................................................................................................................................11
• Updated Table 8-1 Typical TX Current and Output Power ...............................................................................27
Changes from May 19, 2023 to July 12, 2023 (from Revision B (May 2023) to Revision C (July
2023))
Page
• Updated "48MHz Arm Cortex-M4" to "Arm Cortex-M4F."................................................................................... 1
4
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6 Device Comparison
X
CC1311R3
X
X
CC1311P3
X
X
X
7 X 7 mm VQFN (48)
X
5 X 5 mm VQFN (40)
RAM +
GPIO
Cache (KB)
4 X 4 mm VQFN (24)
+20 dBm PA
Multiprotocol
Thread
ZigBee
Bluetooth® LE
Sidewalk
X
FLASH
(KB)
5 X 5 mm VQFN (32)
X
PACKAGE SIZE
4 X 4 mm VQFN (32)
CC1310
Wi-SUN®
Wireless M-Bus
Device
2.4GHz Prop.
Sub-1 GHz Prop.
RADIO SUPPORT
32-128
16-20 + 8
10-30
X
352
32 + 8
22-30
352
32 + 8
26
X
352
80 + 8
30
X
704
144 + 8
30
X
X
X
CC1312R
X
X
X
CC1312R7
X
X
X
CC1352R
X
X
X
X
X
X
X
X
352
80 + 8
28
X
CC1352P
X
X
X
X
X
X
X
X
X
352
80 + 8
26
X
CC1352P7
X
X
X
X
X
X
X
X
X
704
144 + 8
26
X
X
X
X
512
36
12-26
X
CC2340R5
(1)
X
X
X
X
X
X
CC2640R2F
X
128
20 + 8
10-31
CC2642R
X
352
80 + 8
31
X
CC2642R-Q1
X
352
80 + 8
31
X
352
32 + 8
23-31
X
X
352
32 + 8
22-26
X
X
CC2651R3
X
X
X
CC2651P3
X
X
X
X
X
X
X
CC2652R
X
X
X
X
X
352
80 + 8
31
X
CC2652RB
X
X
X
X
X
352
80 + 8
31
X
CC2652R7
X
X
X
X
X
704
144 + 8
31
X
CC2652P
X
X
X
X
X
X
352
80 + 8
26
X
CC2652P7
X
X
X
X
X
X
704
144 + 8
26
X
CC2662R-Q1
X
352
80 + 8
31
X
(1)
ZigBee and Thread support enabled by future software update
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SWRS259C – DECEMBER 2020 – REVISED JULY 2023
7 Terminal Configuration and Functions
38 DIO_25
37 DIO_24
40 DIO_27
39 DIO_26
42 DIO_29
41 DIO_28
44 VDDS
43 DIO_30
46 X48M_N
45 VDDR
48 VDDR_RF
47 X48M_P
7.1 Pin Diagram – RGZ Package (Top View)
34 VDDS_DCDC
4
33 DCDC_SW
DIO_0
5
32 DIO_22
DIO_1
6
31 DIO_21
DIO_2
7
30 DIO_20
DIO_3
8
29 DIO_19
DIO_4
9
28 DIO_18
DIO_5 10
27 DIO_17
DIO_6 11
26 DIO_16
DIO_7 12
25 JTAG_TCKC
DCOUPL 23
JTAG_TMSC 24
3
X32K_Q2
DIO_15 21
VDDS3 22
X32K_Q1
DIO_13 19
DIO_14 20
35 RESET_N
DIO_11 17
DIO_12 18
36 DIO_23
2
DIO_9 15
DIO_10 16
1
VDDS2 13
DIO_8 14
RF_P
RF_N
Figure 7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:
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Pin 10, DIO_5
Pin 11, DIO_6
Pin 12, DIO_7
Pin 24, JTAG_TMSC
Pin 26, DIO_16
Pin 27, DIO_17
The following I/O pins marked in Figure 7-1 in italics have analog capabilities:
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•
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•
•
•
•
6
Pin 36, DIO_23
Pin 37, DIO_24
Pin 38, DIO_25
Pin 39, DIO_26
Pin 40, DIO_27
Pin 41, DIO_28
Pin 42, DIO_29
Pin 43, DIO_30
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7.2 Signal Descriptions
Table 7-1. Signal Descriptions – RGZ Package
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
DCDC_SW
33
—
Power
Output from internal DC/DC converter(1)
DCOUPL
23
—
Power
1.27-V regulated digital-supply (decoupling capacitor)(2)
DIO_0
5
I/O
Digital
GPIO, Sensor Controller
DIO_1
6
I/O
Digital
GPIO, Sensor Controller
DIO_2
7
I/O
Digital
GPIO, Sensor Controller
DIO_3
8
I/O
Digital
GPIO, Sensor Controller
DIO_4
9
I/O
Digital
GPIO, Sensor Controller
DIO_5
10
I/O
Digital
GPIO, Sensor Controller, high-drive capability
DIO_6
11
I/O
Digital
GPIO, Sensor Controller, high-drive capability
DIO_7
12
I/O
Digital
GPIO, Sensor Controller, high-drive capability
DIO_8
14
I/O
Digital
GPIO
DIO_9
15
I/O
Digital
GPIO
DIO_10
16
I/O
Digital
GPIO
DIO_11
17
I/O
Digital
GPIO
DIO_12
18
I/O
Digital
GPIO
DIO_13
19
I/O
Digital
GPIO
DIO_14
20
I/O
Digital
GPIO
DIO_15
21
I/O
Digital
GPIO
DIO_16
26
I/O
Digital
GPIO, JTAG_TDO, high-drive capability
DIO_17
27
I/O
Digital
GPIO, JTAG_TDI, high-drive capability
DIO_18
28
I/O
Digital
GPIO
DIO_19
29
I/O
Digital
GPIO
DIO_20
30
I/O
Digital
GPIO
DIO_21
31
I/O
Digital
GPIO
DIO_22
32
I/O
Digital
GPIO
DIO_23
36
I/O
Digital or Analog
GPIO, Sensor Controller, analog
DIO_24
37
I/O
Digital or Analog
GPIO, Sensor Controller, analog
DIO_25
38
I/O
Digital or Analog
GPIO, Sensor Controller, analog
DIO_26
39
I/O
Digital or Analog
GPIO, Sensor Controller, analog
DIO_27
40
I/O
Digital or Analog
GPIO, Sensor Controller, analog
DIO_28
41
I/O
Digital or Analog
GPIO, Sensor Controller, analog
DIO_29
42
I/O
Digital or Analog
GPIO, Sensor Controller, analog
DIO_30
43
I/O
Digital or Analog
GPIO, Sensor Controller, analog
EGP
—
—
GND
Ground – exposed ground pad
JTAG_TMSC
24
I/O
Digital
JTAG TMSC, high-drive capability
JTAG_TCKC
25
I
Digital
JTAG TCKC
RESET_N
35
I
Digital
Reset, active low. No internal pullup resistor
RF_P
1
—
RF
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_N
2
—
RF
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
VDDR
45
—
Power
1.7-V to 1.95-V supply, must be powered from the internal DC/DC
converter or the internal Global LDO(3) (2)
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Table 7-1. Signal Descriptions – RGZ Package (continued)
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
VDDR_RF
48
—
Power
1.7-V to 1.95-V supply, must be powered from the internal DC/DC
converter or the internal Global LDO(4) (2)
VDDS
44
—
Power
1.8-V to 3.63-V main chip supply(1)
VDDS2
13
—
Power
1.8-V to 3.63-V DIO supply(1)
VDDS3
22
—
Power
1.8-V to 3.63-V DIO supply(1)
VDDS_DCDC
34
—
Power
1.8-V to 3.63-V DC/DC converter supply
X48M_N
46
—
Analog
48-MHz crystal oscillator pin 1
X48M_P
47
—
Analog
48-MHz crystal oscillator pin 2
X32K_Q1
3
—
Analog
32-kHz crystal oscillator pin 1
X32K_Q2
4
—
Analog
32-kHz crystal oscillator pin 2
(1)
(2)
(3)
(4)
For more details, see the technical reference manual listed in Section 11.3.
Do not supply external circuitry from this pin.
If internal DC/DC converter is not used, this pin is supplied internally from the Global LDO.
If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the Global LDO.
7.3 Connections for Unused Pins and Modules
Table 7-2. Connections for Unused Pins
FUNCTION
SIGNAL NAME
GPIO
DIO_n
32.768-kHz crystal
DC/DC converter(2)
(1)
(2)
8
PIN NUMBER
ACCEPTABLE PRACTICE(1)
PREFERRED
PRACTICE(1)
5–12
14–21
26–32
36–43
NC or GND
NC
NC
NC
X32K_Q1
3
X32K_Q2
4
DCDC_SW
33
NC
NC
VDDS_DCDC
34
VDDS
VDDS
NC = No connect
When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the VDDR decoupling capacitor must be connected and moved close to VDDR.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
VDDS(3)
Vin
Tstg
(1)
(2)
(3)
(4)
(5)
MIN
MAX
Supply voltage
–0.3
4.1
V
Voltage on any digital pin (4) (5)
–0.3
VDDS + 0.3, max 4.1
V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
–0.3
VDDR + 0.3, max 2.25
V
Voltage scaling enabled
–0.3
VDDS
Voltage scaling disabled, internal reference
–0.3
1.49
Voltage scaling disabled, VDDS as reference
–0.3
VDDS / 2.9
–40
150
Voltage on ADC input
Storage temperature
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ground, unless otherwise noted.
VDDS2 and VDDS3 must be at the same potential as VDDS.
Including analog capable DIO.
Injection current is not supported on any GPIO pin
8.2 ESD Ratings
VESD
(1)
(2)
(3)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1) (2)
All pins
±2000
V
Charged device model (CDM), per AEC Q100-011(3)
All pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Operating ambient temperature range
–40
105
°C
Operating supply voltage (VDDS)
1.8
3.63
V
Rising supply voltage slew rate
0
100
mV/µs
Falling supply voltage slew rate(1)
0
20
mV/µs
(1)
For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
8.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TYP
VDDS Power-on-Reset (POR) threshold
UNIT
1.1 - 1.55
V
VDDS Brown-out Detector (BOD)
Rising threshold
1.77
V
VDDS Brown-out Detector (BOD), before initial boot (1)
Rising threshold
1.70
V
VDDS Brown-out Detector (BOD)
Falling threshold
1.75
V
(1)
Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
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8.5 Power Consumption - Power Modes
When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold
150
Shutdown. No clocks running, no retention
150
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
0.94
µA
RTC running, CPU, 80KB RAM and (partial) register retention
XOSC_LF
1.09
µA
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
3.2
µA
RTC running, CPU, 80KB RAM and (partial) register retention.
XOSC_LF
3.3
µA
Idle
Supply Systems and RAM powered
RCOSC_HF
675
µA
Active
MCU running CoreMark at 48 MHz
RCOSC_HF
3.39
mA
Peripheral power
domain
Delta current with domain enabled
97.7
Serial power domain
Delta current with domain enabled
7.2
RF Core
Delta current with power domain enabled,
clock enabled, RF Core idle
µDMA
Delta current with clock enabled, module is idle
63.9
Timers
Delta current with clock enabled, module is idle(3)
81.0
I2C
Delta current with clock enabled, module is idle
10.8
I2S
Delta current with clock enabled, module is idle
27.6
SSI
Delta current with clock enabled, module is idle
UART
Delta current with clock enabled, module is idle(1)
167.5
CRYPTO (AES)
Delta current with clock enabled, module is idle(2)
25.6
PKA
Delta current with clock enabled, module is idle
84.7
TRNG
Delta current with clock enabled, module is idle
35.6
Reset and Shutdown
Standby
without cache retention
Icore
Standby
with cache retention
nA
Peripheral Current Consumption
Iperi
210.9
µA
82.9
Sensor Controller Engine Consumption
ISCE
(1)
(2)
(3)
10
Active mode
24 MHz, infinite loop
808.5
Low-power mode
2 MHz, infinite loop
31.9
µA
Only one UART running
Only one SSI running
Only one GPTimer running
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8.6 Power Consumption - Radio Modes
When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
PARAMETER
TEST CONDITIONS
Radio receive current
Radio transmit current
TYP
UNIT
2440 MHz
6.9
mA
0 dBm output power setting
2440 MHz
7.0
mA
+5 dBm output power setting
2440 MHz
9.2
mA
8.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Flash sector size
MAX
8
UNIT
KB
Supported flash erase cycles before failure, full bank(1)
30
k Cycles
Supported flash erase cycles before failure, single sector(2)
60
k Cycles
Maximum number of write operations per row before sector
erase(3)
83
Flash retention
105 °C
Flash sector erase current
Flash sector erase
30k cycles
Flash write current
Average delta current, 4 bytes at a time
Flash write time
4 bytes at a time
(3)
(4)
10.7
Zero cycles
Flash sector erase time(4)
(1)
(2)
Years at 105
°C
11.4
Average delta current
time(4)
Write
Operations
mA
10
ms
4000
ms
6.2
mA
21.6
µs
A full bank erase is counted as a single erase cycle on each sector
Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum
per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
This number is dependent on Flash aging and increases over time and erase cycles
8.8 Thermal Resistance Characteristics
PACKAGE
THERMAL
METRIC(1)
RGZ
(VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
24.2
°C/W(2)
RθJC(top)
Junction-to-case (top) thermal resistance
13.6
°C/W(2)
RθJB
Junction-to-board thermal resistance
7.8
°C/W(2)
ψJT
Junction-to-top characterization parameter
0.1
°C/W(2)
ψJB
Junction-to-board characterization parameter
7.7
°C/W(2)
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
°C/W(2)
(1)
(2)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
°C/W = degrees Celsius per watt.
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8.9 Receive (RX)
When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DC/DC
enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps
Receiver sensitivity
Differential mode. Measured at SMA connector, BER =
10–3
–92
dBm
Receiver saturation
Differential mode. Measured at SMA connector, BER =
10–3
>5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
> (–440 / 500)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–700 / 750)
ppm
Co-channel rejection(1)
Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10–3
Selectivity, ±2 MHz(1)
–7
dB
Wanted signal at –67 dBm, modulated interferer at ±2
MHz, Image frequency is at –2 MHz, BER = 10–3
8 / 4(2)
dB
Selectivity, ±4 MHz(1)
Wanted signal at –67 dBm, modulated interferer at ±4
MHz, BER = 10–3
33 / 31(2)
dB
Selectivity, ±6 MHz or more(1)
Wanted signal at –67 dBm, modulated interferer at ±6
MHz or more, BER = 10–3
37 / 32(2)
dB
Selectivity, image frequency(1)
Wanted signal at –67 dBm, modulated interferer at image
frequency, BER = 10–3
4
dB
Selectivity, image frequency
±2 MHz(1)
Note that Image frequency + 2 MHz is the Co-channel.
Wanted signal at –67 dBm, modulated interferer at ±2
MHz from image frequency, BER = 10–3
–7 / 36(2)
dB
Out-of-band blocking(3)
30 MHz to 2000 MHz
–16
dBm
Out-of-band blocking
2003 MHz to 2399 MHz
–21
dBm
Out-of-band blocking
2484 MHz to 2997 MHz
–15
dBm
Out-of-band blocking
3000 MHz to 12.75 GHz
–12
dBm
Intermodulation
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2405 and 2408 MHz respectively, at the given power
level
–38
dBm
RSSI dynamic range
63
dB
RSSI Accuracy (+/-)
±4
dB
(1)
(2)
(3)
12
Numbers given as I/C dB
X / Y, where X is +N MHz and Y is –N MHz
Excluding one exception at Fwanted / 2
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8.10 Transmit (TX)
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
5dBm output power
Differential mode, delivered to a single-ended 50 Ω load through a balun
5
dBm
Output power
programmable range
Differential mode, delivered to a single-ended 50 Ω load through a balun
26
dB
Spurious emissions and harmonics
Spurious emissions (1)
Harmonics (1)
(1)
f < 1 GHz, outside restricted bands
+5 dBm setting
< –36
dBm
f < 1 GHz, restricted bands ETSI
+5 dBm setting
< –54
dBm
f < 1 GHz, restricted bands FCC
+5 dBm setting
< –55
dBm
f > 1 GHz, including harmonics
+5 dBm setting
< –42
dBm
Second harmonic
+5 dBm setting
< –42
dBm
Third harmonic
+5 dBm setting
< –42
dBm
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Category 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
8.11 Timing and Switching Characteristics
8.11.1 Reset Timing
PARAMETER
MIN
RESET_N low duration
TYP
MAX
UNIT
1
µs
8.11.2 Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCU, Reset to Active(1)
850 - 3000
µs
MCU, Shutdown to Active(1)
850 - 3000
µs
MCU, Standby to Active
160
µs
MCU, Active to Standby
36
µs
MCU, Idle to Active
14
µs
(1)
The wakeup time is dependent on remaining charge on the VDDR capacitor when starting the device, and thus how long the device
has been in Reset or Shutdown before starting up again.
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8.11.3 Clock Specifications
8.11.3.1 48 MHz Crystal Oscillator (XOSC_HF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER
MIN
TYP
Crystal frequency
48
ESR
Equivalent series resistance
6 pF < CL ≤ 9 pF
20
ESR
Equivalent series resistance
5 pF < CL ≤ 6 pF
LM
Motional inductance, relates to the load capacitance that is used for the crystal (CL
in Farads)(5)
CL
Crystal load
capacitance(4)
(4)
(5)
60
Ω
80
Ω
H
7(3)
5
UNIT
MHz
< 0.3 × 10–24 / CL 2
Start-up time(2)
(1)
(2)
(3)
MAX
9
200
pF
µs
Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
Adjustable load capacitance is integrated within the device.
The crystal manufacturer's specification must satisfy this requirement for proper operation.
8.11.3.2 48 MHz RC Oscillator (RCOSC_HF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Frequency
48
MHz
Uncalibrated frequency accuracy
±1
%
Calibrated frequency accuracy(1)
±0.25
%
5
µs
Start-up time
(1)
Accuracy relative to the calibration source (XOSC_HF)
8.11.3.3 2 MHz RC Oscillator (RCOSC_MF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Calibrated frequency
2
MHz
Start-up time
5
µs
8.11.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
Crystal frequency
ESR
Equivalent series resistance
CL
Crystal load capacitance
(1)
TYP
MAX
32.768
6
UNIT
kHz
30
100
kΩ
7(1)
12
pF
Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.
8.11.3.5 32 kHz RC Oscillator (RCOSC_LF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
Temperature coefficient
(1)
14
TYP
32.8 (1) (2)
Calibrated frequency
±50
MAX
UNIT
kHz
ppm/C
When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
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The SIMPLELINK-WBMS-SDK does not use RCOSC_LF, but XOSC_LF.
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8.11.4 Synchronous Serial Interface (SSI) Characteristics
8.11.4.1 Synchronous Serial Interface (SSI) Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
NO.
PARAMETER
MIN
TYP
UNIT
65024
System Clocks (2)
S1
tclk_per
SSIClk cycle time
S2(1)
tclk_high
SSIClk high time
0.5
tclk_per
S3(1)
tclk_low
SSIClk low time
0.5
tclk_per
(1)
(2)
12
MAX
Refer to SSI timing diagrams Figure 8-1, Figure 8-2, and Figure 8-3.
When using the TI-provided Power driver, the SSI system clock is always 48 MHz.
S1
S2
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits output data
Figure 8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
16
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Figure 8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
8.11.5 UART
8.11.5.1 UART Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
UART rate
TYP
MAX
3
UNIT
MBaud
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8.12 Peripheral Characteristics
8.12.1 ADC
Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
Input voltage range
MIN
TYP
0
Resolution
12
Sample rate
Offset
Gain error
DNL(4)
Differential nonlinearity
INL
Integral nonlinearity
ENOB
Effective number of bits
THD
Total harmonic distortion
SINAD,
SNDR
SFDR
(1)
18
Signal-to-noise
and
distortion ratio
MAX
VDDS
UNIT
V
Bits
200
kSamples/s
Internal 4.3 V equivalent reference(2)
–0.24
LSB
reference(2)
7.14
LSB
>–1
LSB
±4
LSB
Internal 4.3 V equivalent
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
9.8
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled
9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
10.1
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
11.1
Internal reference, voltage scaling disabled,
14-bit mode, 200 kSamples/s, 600 Hz input tone (5)
11.3
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 150 Hz input tone (5)
11.6
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
–65
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
–70
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
–72
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
60
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
63
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
68
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
70
Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
73
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
75
Conversion time
Serial conversion, time-to-output, 24 MHz clock
Current consumption
Internal 4.3 V equivalent reference(2)
Current consumption
VDDS as reference
Reference voltage
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1
Reference voltage
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TI-RTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095
Reference voltage
50
Bits
dB
dB
dB
clock-cycles
0.42
mA
0.6
mA
4.3(2) (3)
V
1.48
V
VDDS as reference, input voltage scaling enabled
VDDS
V
Reference voltage
VDDS as reference, input voltage scaling disabled
VDDS /
2.82(3)
V
Input impedance
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance depends on sampling frequency and sampling
time
>1
MΩ
Using IEEE Std 1241-2010 for terminology and test methods
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(3)
(4)
(5)
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Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
Applied voltage must be within Absolute Maximum Ratings (see Section 8.1 ) at all times
No missing codes
ADC_output = ∑(4n samples) >> n,n = desired extra bits
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8.12.2 DAC
8.12.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
Resolution
8
Bits
Any load, any VREF, pre-charge OFF, DAC charge-pump ON
1.8
3.63
Any load, VREF = DCOUPL, pre-charge ON
2.6
3.63
16
VDDS
Supply voltage
FDAC
Clock frequency
Buffer OFF (internal load)
Voltage output settling time
VREF = VDDS, buffer OFF, internal load
1000
13
V
kHz
1 / FDAC
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
Differential nonlinearity
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 250 kHz
±1
Differential nonlinearity
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 16 kHz
±1.2
DNL
Offset error(2)
Load = Continuous Time
Comparator
Offset error(2)
Load = Low Power Clocked
Comparator
Max code output voltage
variation(2)
Load = Continuous Time
Comparator
Max code output voltage
variation(2)
Load = Low Power Clocked
Comparator
Output voltage range(2)
Load = Continuous Time
Comparator
20
LSB(1)
VREF = VDDS= 3.63 V
±0.67
VREF = VDDS= 3.0 V
±0.81
VREF = VDDS = 1.8 V
±1.27
VREF = DCOUPL, pre-charge ON
±3.43
VREF = DCOUPL, pre-charge OFF
±2.88
VREF = VDDS = 3.63 V
±0.77
VREF = VDDS = 3.0 V
±0.77
VREF = VDDS= 1.8 V
±3.46
VREF = DCOUPL, pre-charge ON
±3.44
VREF = DCOUPL, pre-charge OFF
±4.70
VREF = VDDS = 3.63 V
±1.61
VREF = VDDS = 3.0 V
±1.71
VREF = VDDS= 1.8 V
±2.10
VREF = DCOUPL, pre-charge ON
±6.00
VREF = DCOUPL, pre-charge OFF
±3.85
VREF =VDDS= 3.63 V
±2.92
VREF =VDDS= 3.0 V
±3.06
VREF = VDDS= 1.8 V
±3.91
VREF = DCOUPL, pre-charge ON
±7.84
VREF = DCOUPL, pre-charge OFF
±4.06
VREF = VDDS= 3.63 V, code 1
0.03
VREF = VDDS= 3.63 V, code 255
3.46
VREF = VDDS= 3.0 V, code 1
0.02
VREF = VDDS= 3.0 V, code 255
2.86
VREF = VDDS= 1.8 V, code 1
0.01
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.01
VREF = DCOUPL, pre-charge OFF, code 255
1.21
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
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LSB(1)
LSB(1)
LSB(1)
V
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Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Output voltage range(2)
Load = Low Power Clocked
Comparator
(1)
(2)
TEST CONDITIONS
MIN
TYP
VREF = VDDS= 3.63 V, code 1
0.03
VREF = VDDS= 3.63 V, code 255
3.46
VREF = VDDS= 3.0 V, code 1
0.02
VREF = VDDS= 3.0 V, code 255
2.85
VREF = VDDS = 1.8 V, code 1
0.01
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.01
VREF = DCOUPL, pre-charge OFF, code 255
1.21
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
MAX
UNIT
V
1 LSB (VREF 3.63 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 13.44 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
Includes comparator offset
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8.12.3 Temperature and Battery Monitor
8.12.3.1 Temperature Sensor
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
UNIT
2
°C
Accuracy
-40 °C to 0 °C
±4.0
°C
Accuracy
0 °C to 105 °C
±2.5
°C
4.1
°C/V
Supply voltage
(1)
coefficient(1)
The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
8.12.3.2 Battery Monitor
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Resolution
MAX
25
Range
1.8
Integral nonlinearity (max)
Accuracy
TYP
72
V
mV
22.5
mV
Offset error
-32
mV
Gain error
-1.3
%
22
VDDS = 3.0 V
mV
3.63
28
UNIT
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8.12.4 Comparators
8.12.4.1 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Input voltage range(1)
TYP
0
Offset
Measured at VDDS / 2
Decision time
Step from –10 mV to 10 mV
Current consumption
Internal reference
(1)
MIN
MAX
UNIT
VDDS
V
±5
mV
0.78
µs
8.6
µA
The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.12.4.2 Low-Power Clocked Comparator
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Input voltage range
MIN
0
Clock frequency
MAX
UNIT
VDDS
V
SCLK_LF
Internal reference voltage(1)
Using internal DAC with VDDS as reference voltage,
DAC code = 0 - 255
Offset
Measured at VDDS / 2, includes error from internal DAC
Decision time
(1)
TYP
0.024 - 2.865
Step from –50 mV to 50 mV
V
±5
mV
1
Clock
Cycle
The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage
selected. See DAC Characteristics
8.12.5 Current Source
8.12.5.1 Programmable Current Source
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Current source programmable output range (logarithmic
range)
Resolution
MIN
TYP
MAX
0.25 - 20
µA
0.25
µA
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UNIT
23
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8.12.6 GPIO
8.12.6.1 GPIO DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25 °C, VDDS = 1.8 V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
GPIO VOL at 8 mA load
IOCURR = 2, high-drive GPIOs only
1.44
GPIO VOH at 4 mA load
IOCURR = 1
GPIO VOL at 4 mA load
IOCURR = 1
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
32
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
V
0.36
1.44
V
V
0.36
V
68
110
µA
11
18.5
39
µA
IH = 1, transition voltage for input read as 0 → 1
0.72
1.08
1.17
V
IH = 1, transition voltage for input read as 1 → 0
0.54
0.72
0.87
V
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.18
0.36
0.51
V
GPIO minimum VIH
Lowest GPIO input voltage reliably interpreted as
High
1.17
GPIO maximum VIL
Highest GPIO Input voltage reliably interpreted as
Low
V
0.63
V
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
GPIO VOL at 8 mA load
IOCURR = 2, high-drive GPIOs only
GPIO VOH at 4 mA load
IOCURR = 1
GPIO VOL at 4 mA load
IOCURR = 1
2.4
V
0.6
2.4
V
V
0.6
V
TA = 25 °C, VDDS = 3.63 V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
GPIO VOL at 8 mA load
IOCURR = 2, high-drive GPIOs only
GPIO VOH at 4 mA load
IOCURR = 1
GPIO VOL at 4 mA load
IOCURR = 1
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
64
GPIO low-to-high input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.52
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 1 → 0
1.14
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.38
GPIO minimum VIH
Lowest GPIO input voltage reliably interpreted as a
High
2.47
GPIO maximum VIL
Highest GPIO input voltage reliably interpreted as a
Low
24
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2.9
V
0.6
2.9
135
V
V
0.6
V
380
µA
102
178
µA
1.90
2.21
V
1.48
1.83
V
0.42
1.07
V
264
V
1.33
V
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8.13 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Section 8.3 for device limits. Values exceeding these limits are for reference only.
8.13.1 MCU Current
Running CoreMark, SCLK_HF = 48 MHz RCOSC
80 kB RAM retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz XOSC VDDS = 3.0 V
6
12
5.5
10
8
Current [uA]
Current [mA]
5
4.5
4
6
4
3.5
2
3
2.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
0
-40
3.8
-25
-10
5
20
35
50
65
80
95
105
Temperature [ oC]
Voltage [V]
Figure 8-4. Active Mode (MCU) Current vs. Supply
Voltage (VDDS)
Figure 8-5. Standby Mode (MCU) Current vs.
Temperature
80 kbps RAM Retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz RCOSC VDDS = 3.6 V
12
10
Current [uA)
8
6
4
2
0
-40
-25
-10
5
20
35
50
65
80
95
105
Temperature [ oC]
Figure 8-6. Standby Mode (MCU) Current vs. Temperature (VDDS = 3.6 V)
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8
7.9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6
-40
11.5
11
10.5
10
9.5
Current [mA]
Current [mA]
8.13.2 RX Current
9
8.5
8
7.5
7
6.5
6
5.5
-25
-10
5
20
35
50
65
80
95
105
5
1.8
2
Temperature [ oC]
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
Figure 8-7. RX Current versus Temperature
(WBMS, 2.44 GHz)
26
2.2
Figure 8-8. RX Current versus Supply Voltage
(VDDS) (WBMS, 2.44 GHz)
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8.13.3 TX Current
9
12
8.8
11.5
8.6
11
8.4
10.5
8.2
10
Current [mA]
Current [mA]
8
7.8
7.6
7.4
7.2
7
9.5
9
8.5
8
7.5
6.8
7
6.6
6.5
6.4
6
6.2
6
-40
-25
-10
5
20
35
50
65
80
95
105
5.5
1.8
2
2.2
2.4
2.6
Temperature [ oC]
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
Figure 8-9. TX Current vs. Temperature (WBMS,
2.44 GHz, 0 dBm)
Figure 8-10. TX Current vs. Supply Voltage (VDDS)
(WBMS, 2.44 GHz, 0 dBm)
Table 8-1 shows typical TX current and output power for different output power settings.
Table 8-1. Typical TX Current and Output Power
CC2662R-Q1 at 2.4 GHz, VDDS = 3.0 V (Measured on CC2652REM-7ID-Q1)
txPower
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
0x8623
5
5.0
9.2
0x5E1A
4
4.1
8.6
0x7217
3.5
3.6
8.8
0x4867
3
3.2
8.2
0x3860
2
2.0
7.6
0x2E5C
1
1.2
7.3
0x2E59
0
0.3
7.0
0x2853
-2
-2.2
6.8
0x10D9
-5
-5.0
5.9
0x0AD1
-10
-9.5
5.3
0x0ACC
-15
-13.7
4.9
0x0AC8
-20
-18.6
4.6
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8.13.4 RX Performance
-87
-84
-85
-88
-87
-90
-88
Sensitivity [dBm]
Sensitivity [dBm]
-86
-89
-91
-92
-93
-89
-90
-91
-92
-93
-94
-94
-95
-95
-96
-96
-97
-97
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
2.464
2.472
-98
-40
2.48
-25
-10
5
20
Frequency [GHz]
35
50
65
80
95
105
Temperature [°C]
Figure 8-11. Sensitivity versus Frequency (WBMS,
2.44 GHz)
Figure 8-12. Sensitivity versus Temperature
(WBMS, 2.44 GHz)
-86
-84
-87
-86
-88
-88
Sensitivity [dBm]
Sensitivity [dBm]
-89
-90
-91
-92
-90
-92
-94
-93
-96
-94
-98
-95
-96
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
-100
1.8
2
Figure 8-13. Sensitivity versus Supply Voltage
(VDDS) (WBMS, 2.44 GHz)
28
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
Voltage [V]
Figure 8-14. Sensitivity versus Supply Voltage
(VDDS) (WBMS, 2.44 GHz, DCDC off)
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2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-40
Output Power [dBm]
Output Power [dBm]
8.13.5 TX Performance
-25
-10
5
20
35
50
65
80
95
105
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
-40
-25
-10
5
35
50
65
80
95
Figure 8-15. Output Power vs. Temperature
(WBMS, 2.44 GHz, 0dBm)
Figure 8-16. Output Power vs. Temperature
(WBMS, 2.44 GHz, +5dBm)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
1.8
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
2
2.2
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.6
2.8
3
3.2
3.4
3.6
3.8
Figure 8-18. Output Power vs. Supply Voltage
(VDDS) (WBMS, 2.44 GHz, +5dBm)
Output Power [dBm]
Figure 8-17. Output Power vs. Supply Voltage
(VDDS) (WBMS, 2.44 GHz, 0dBm)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2.4
105
Voltage [V]
Voltage [V]
Output Power [dBm]
20
Temperature [ oC]
Output Power [dBm]
Output Power [dBm]
Temperature [ oC]
2.456
2.464
2.472
2.48
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
2.464
2.472
2.48
Frequency [GHz]
Frequency [GHz]
Figure 8-19. Output Power vs. Frequency (WBMS,
0dBm)
Figure 8-20. Output Power vs. Frequency (WBMS,
+5dBm)
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8.13.6 ADC Performance
11.4
Vin = 3.0 V Sine wave, Internal reference, Fin = Fs / 10
Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode
10.2
11.1
10.15
10.1
ENOB [Bit]
ENOB [Bit]
10.8
10.5
10.2
10.05
10
9.95
9.9
9.9
9.85
9.6
0.2 0.3
0.5 0.7
1
2
3
4 5 6 7 8 10
20
9.8
30 40 50 70 100
1
Frequency [kHz]
2
4 5 6 7 8 10
70
100
200
Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s
2.5
1
2
0.5
1.5
DNL [LSB]
1.5
0
1
-0.5
0.5
-1
0
-1.5
-0.5
0
400
800
1200
1600
2000
2400
2800
3200
3600
4000
0
400
800
1200
1600
ADC Code
Vin = 1 V, Internal reference, 200 kSamples/s
1.009
1.008
1.008
1.007
1.007
Voltage [V]
1.009
1.006
1.005
1.004
1.002
1.001
1.001
10
20
30
40
4000
1.004
1.002
0
3600
1.005
1.003
-10
3200
1.006
1.003
-20
2800
Vin = 1 V, Internal reference, 200 kSamples/s
1.01
-30
2400
Figure 8-24. DNL versus ADC Code
1.01
1
-40
2000
ADC Code
Figure 8-23. INL versus ADC Code
Voltage [V]
30 40 50
Figure 8-22. ENOB versus Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s
50
60
70
80
90
100
1
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
Temperature [°C]
Figure 8-25. ADC Accuracy versus Temperature
30
20
Frequency [kHz]
Figure 8-21. ENOB versus Input Frequency
INL [LSB]
3
Figure 8-26. ADC Accuracy versus VDDS
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9 Detailed Description
9.1 Overview
Figure 4-1 shows the core modules of the CC2662R-Q1 device.
9.2 System CPU
The CC2662R-Q1 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4F system CPU, which runs the
application and the higher layers of the Wireless BMS protocol stack.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• IEEE 754-compliant single-precision Floating Point Unit (FPU)
• Memory Protection Unit (MPU) for safety-critical applications
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
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9.3 Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor
that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF Core offers a high level, command-based
API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF Core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main
CPU, which reduces power consumption and leaves more resources for the user application. Several signals are
also available to control external circuitry such as RF switches or range extenders autonomously.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
even with over-the-air (OTA) upgrades while still using the same silicon.
32
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9.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is
in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is split into up to five 16-KB blocks and can be used for both
storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by
default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors in
memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always
initialized to zeroes upon code execution from boot.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
There is a 4-KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically
used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by
the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.
The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks,
which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that
can be used for initial programming of the device.
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9.5 Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power
modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary
power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby
significantly reducing power consumption and offloading the system CPU.
The Sensor Controller Engine is user programmable with a simple programming language that has a syntax
similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential
algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable
state machines, or event routing.
The main advantages are:
• Flexibility - data can be read and processed in unlimited manners while still
• 2 MHz low-power mode enables lowest possible handling of digital sensors
• Dynamic reuse of hardware resources
• 40-bit accumulator supporting multiplication, addition and shift
• Observability and debugging options
Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces
C driver source code, which the System CPU application uses to control and exchange data with the Sensor
Controller. Typical use cases may be (but are not limited to) the following:
• Read analog sensors using integrated ADC or comparators
• Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged)
• Capacitive sensing
• Waveform generation
• Very low-power pulse counting (flow metering)
• Key scan
The Sensor Controller peripherals include the following:
• The low-power clocked comparator can be used to wake the system CPU from any state in which the
comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital
converter, and a comparator. The continuous time comparator in this block can also be used as a higheraccuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline
tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive
sensing.
• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be
triggered by many different sources including timers, I/O pins, software, and comparators.
• The analog modules can connect to up to eight different GPIOs
• Dedicated SPI Controller with up to 6 MHz clock speed
The Sensor Controller peripherals can also be controlled from the main application processor.
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9.6 Cryptography
The CC2662R-Q1 device comes with a wide set of modern cryptography-related hardware accelerators,
drastically reducing code footprint and execution time for cryptographic operations. It also has the benefit
of being lower power and improves availability and responsiveness of the system because the cryptography
operations runs in a background hardware thread.
Together with a large selection of open-source cryptography libraries provided with the Software Development
Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The
hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
• Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512
• Advanced Encryption Standard (AES) with 128 and 256 bit key lengths
• Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic
curves up to 512 bits and RSA key pair generation up to 1024 bits.
Through use of these modules and the TI provided cryptography drivers, the following capabilities are available
for an application or stack:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P224, NIST-P256, NIST-P384, NIST-P521
• Brainpool-256R1, Brainpool-384R1, Brainpool-512R1
• secp256r1
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• SHA2 based MACs
– HMAC with SHA224, SHA256, SHA384, or SHA512
• Block cipher mode of operation
– AESCCM
– AESGCM
– AESECB
– AESCBC
– AESCBC-MAC
• True random number generation
Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as
Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not part of
the TI SimpleLink SDK for the CC2662R-Q1 device.
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9.7 Timers
A large selection of timers are available as part of the CC2662R-Q1 device. These timers are:
• Real-Time Clock (RTC)
•
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the RCOSC_LF as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. The real time clock can also be read by the
Sensor Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the
RTC halts when a debugger halts the device.
General-Purpose Timers (GPTIMER)
•
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
Sensor Controller Timers
The Sensor Controller contains 3 timers:
AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on each
edge of a selected tick source. Both one-shot and periodical timer modes are available.
•
AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor
Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or
periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as
well as for PWM output or waveform generation.
Radio Timer
•
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in
the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal as the
source of SCLK_HF.
Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and
when a debugger halts the device.
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9.8 Serial Peripherals and I/O
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous
serial interfaces. The SSIs support both SPI Controller and Peripheral up to 4 MHz. The SSI modules support
configurable phase and polarity.
The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baudrate generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation
microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100 kHz and 400 kHz operation, and can serve as both Controller and Target.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in Section 7. All digital peripherals can be connected to
any digital pin on the device.
For more information, see the CC13x2, CC26x2 SimpleLink™ Wireless MCU Technical Reference Manual.
9.9 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2662R-Q1 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.10 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
•
•
•
•
Highly flexible and configurable channel operation of up to 32 channels
Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
Data sizes of 8, 16, and 32 bits
Ping-pong mode for continuous streaming of data
9.11 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
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9.12 Power Management
To minimize power consumption, the CC2662R-Q1 supports a number of power modes and power management
features (see Table 9-1).
Table 9-1. Power Modes
MODE
SOFTWARE CONFIGURABLE POWER MODES
ACTIVE
IDLE
STANDBY
SHUTDOWN
RESET PIN
HELD
CPU
Active
Off
Off
Off
Off
Flash
On
Available
Off
Off
Off
SRAM
On
On
Retention
Off
Off
Supply System
On
On
Duty Cycled
Off
Off
Register and CPU retention
Full
Full
Partial
No
No
SRAM retention
Full
Full
Full
No
No
48 MHz high-speed clock
(SCLK_HF)
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
2 MHz medium-speed clock
(SCLK_MF)
RCOSC_MF
RCOSC_MF
Available
Off
Off
32 kHz low-speed clock
(SCLK_LF)
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Off
Off
Peripherals
Available
Available
Off
Off
Off
Sensor Controller
Available
Available
Available
Off
Off
Wake-up on RTC
Available
Available
Available
Off
Off
Wake-up on pin edge
Available
Available
Available
Available
Off
Wake-up on reset pin
On
On
On
On
On
Brownout detector (BOD)
On
On
Duty Cycled
Off
Off
Power-on reset (POR)
On
On
On
Off
Off
Watchdog timer (WDT)
Available
Available
Paused
Off
Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the CPU and all of the peripherals that are currently enabled. The system clock can be any available clock
source (see Table 9-1).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor
Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need
to be reconfigured when waking up again, and the CPU continues execution from where it went into standby
mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and
the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O
pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can
differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status
register. The only state retained in this mode is the latched I/O state and the flash memory contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Interface
independently of the system CPU. This means that the system CPU does not have to wake up, for example to
perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would
otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller,
control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be
controlled by the system CPU.
Note
The power, RF and clock management for the CC2662R-Q1 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in the
TI-provided drivers that are part of the CC2662R-Q1 software development kit (SDK). Therefore, TI
highly recommends using this software framework for all application development on the device. The
complete SDK with TI-RTOS, device drivers, and examples are offered free of charge in source code.
9.13 Clock Systems
The CC2662R-Q1 device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by
the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal.
SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for
internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator
(RCOSC_MF).
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for
ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after
Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768
kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost. Note that theSDK relies on a 32.768 kHz crystal (XOSC_LF)
being used.
9.14 Network Processor
Depending on the product configuration, the CC2662R-Q1 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.
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10 Application, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC2662R-Q1
device.
Special attention must be paid to RF component placement, decoupling capacitors and DC/DC regulator
components, as well as ground connections for all of these.
CC26x2REM-7ID-Q1 Design
Files
The CC26x2REM-7ID-Q1 reference design provides schematic, layout
and production files for the characterization board used for deriving the
performance number found in this document.
CC2662RQ1-EVM-WBMS
Design Files
The CC2662RQ1-EVM-WBMS Design Files contain detailed schematics and
layouts to build application specific boards using the CC2662R-Q1 device.
Sub-1 GHz and 2.4
The antenna kit allows real-life testing to identify the optimal antenna for your
GHz Antenna Kit for
application. The antenna kit includes 16 antennas covering frequencies from
LaunchPad™ Development Kit 169 MHz to 2.4 GHz, including:
and SensorTag
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU
LaunchPad Development Kits and SensorTags.
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10.2 Junction Temperature Calculation
This section shows the different techniques for calculating the junction temperature under various operating
conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are three recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature:
T J = ψJT × P + Tcase
(1)
2. From board temperature:
T J = ψJB × P + Tboard
(2)
3. From ambient temperature:
T J = RθJA × P + TA
(3)
P is the power dissipated from the device and can be calculated by multiplying current consumption with supply
voltage. Thermal resistance coefficients are found in Section 8.8.
Example:
Using Equation 3, the temperature difference between ambient temperature and junction temperature is
calculated. In this example, we assume a simple use case where the radio is transmitting continuously at 0 dBm
output power. Let us assume the ambient temperature is 105 °C and the supply voltage is 3 V. To calculate P, we
need to look up the current consumption for Tx at 105 °C in . From the plot, we see that the current consumption
is 7.9 mA. This means that P is 7.9 mA × 3 V = 23.7 mW.
The junction temperature is then calculated as:
T J = 23.0°C W × 23.7mW + TA = 0.5°C + TA
(4)
As can be seen from the example, the junction temperature will be 0.5 °C higher than the ambient temperature
when running continuous Tx at 105 °C.
For various application use cases current consumption for other modules may have to be added to calculate the
appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral
modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the
peak power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx current
consumption.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or datecode. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, XCC2662R-Q1
is in preview; therefore, an X prefix/identification is assigned).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RGZ).
For orderable part numbers of CC2662R-Q1 devices in the RGZ (7-mm x 7-mm) package type, see the Package
Option Addendum of this document, the Device Information in Section 3, the TI website (www.ti.com), or contact
your TI sales representative.
CC2662
R
1 FTW RGZ
PREFIX
X = Experimental device
Blank = Qualified devie
R
Q1
AUTOMOTIVE Q1
Q1 = Q100
DEVICE
SimpleLink™ Ultra-Low-Power
Wireless MCU
R = Large Reel
T = Small Reel
CONFIGURATION
R = Regular
P = +20 dBm PA included
PACKAGE
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
ROM Revision
F = Flash
T = -40C to 105 C
W = Wettable flanks
Figure 11-1. Device Nomenclature
11.2 Tools and Software
The CC2662R-Q1 device is supported by a variety of software and hardware development tools.
Development Kit
CC2662RQ1-EVM-WBMS Development Kit
The SimpleLink CC2662RQ1-EVM-WBMS development kit is an easy-to-use evaluation module for Wireless
BMS evaluation board featuring BQ7961x-Q1 FuSa Compliant and SimpleLink™ CC2662R-Q1 wireless MCU.
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It contains everything needed to start developing on the SimpleLink™ CC2662R-Q1, including a XDS110 JTAG
debug probe for programming, debugging, and energy measurements.
The SimpleLink™ CC2662R-Q1 is an AEC-Q100 compliant wireless microcontroller (MCU) targeting wireless
automotive applications. The device is optimized for low-power wireless communication in applications such as
battery management systems (BMS) and cable replacement.
Software
SimpleLink™ WMBS SDK
The SimpleLink WMBS Software Development Kit (SDK) provides a complete package for the development of
wireless applications on the 2.4 GHz CC2662R-Q1 device
The SimpleLink WMBS SDK is part of TI’s SimpleLink MCU platform, offering a single development environment
that delivers flexible hardware, software and tool options for customers developing wired and wireless
applications. For more information about the SimpleLink MCU Platform, visit http://www.ti.com/simplelink.
Development Tools
Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get started faster
than ever before. Code Composer Studio combines the advantages of the Eclipse® software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™ software (application
energy usage profiling). A real-time object viewer plugin is available for TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS debuggers included
on a LaunchPad Development Kit.
SmartRF™ Studio
SmartRF™ Studio is a Windows® application that can be used to evaluate and configure SimpleLink Wireless
MCUs from Texas Instruments. The application will help designers of RF systems to easily evaluate the radio
at an early stage in the design process. It is especially useful for generation of configuration register values
and for practical testing and debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF device. Features of the
SmartRF Studio include:
•
•
•
•
Link tests - send and receive packets between nodes
Antenna and radiation tests - set the radio in continuous wave TX and RX states
Export radio configuration code for use with the TI SimpleLink SDK RF driver
Custom GPIO configuration for signaling and control of external switches
Sensor Controller Studio
Sensor Controller Studio is used to write, test and debug code for the Sensor Controller peripheral. The tool
generates a Sensor Controller Interface driver, which is a set of C source files that are compiled into the System
CPU application. These source files also contain the Sensor Controller binary image and allow the System CPU
application to control and exchange data with the Sensor Controller. Features of the Sensor Controller Studio
include:
•
•
Ready-to-use examples for several common use cases
Full toolchain with built-in compiler and assembler for programming in a C-like programming language
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•
Provides rapid development by using the integrated sensor controller task testing and debugging
functionality, including visualization of sensor data and verification of algorithms
CCS UniFlash
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs. UniFlash has a GUI,
command line, and scripting interface. CCS UniFlash is available free of charge.
11.2.1 SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of
wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering
flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use it throughout your entire portfolio. Learn more on ti.com/simplelink.
11.3 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder on ti.com/product/CC2662R-Q1. In the upper right corner, click on Alert me to
register and receive a weekly digest of any product information that has changed. For change details, review the
revision history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
Errata
CC2662R-Q1 Silicon Errata
The silicon errata describes the known exceptions to the functional specifications for each silicon revision of the
device and description on how to recognize a device revision.
Application Reports
All application reports for the CC2662R-Q1 device are found on the device product folder at: ti.com/product/
CC2662R-Q1.
Technical Reference Manual (TRM)
CC13x2, CC26x2 SimpleLink™ Wireless MCU TRM
The TRM provides a detailed description of all modules and peripherals available in the device family.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.
Wi-Fi® is a registered trademark of Wi-Fi Alliance.
Arm Thumb® is a registered trademark of Arm Limited (or its subsidiaries).
Eclipse® is a registered trademark of Eclipse Foundation.
Windows® is a registered trademark of Microsoft Corporation.
All trademarks are the property of their respective owners.
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
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12-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CC2662R1FTWRGZRQ1
ACTIVE
VQFN
RGZ
48
4000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
CC2662 Q1
R1F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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