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CC3100
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
CC3100 SimpleLink™ Wi-Fi® Network Processor,
Internet-of-Things Solution for MCU Applications
1 Device Overview
1.1
Features
1
• CC3100 SimpleLink Wi-Fi Consists of Wi-Fi
Network Processor and Power-Management
Subsystems
• Wi-Fi CERTIFIED™ Chip
• Wi-Fi Network Processor Subsystem
– Featuring Wi-Fi Internet-On-a-Chip™
– Dedicated ARM MCU
Completely Offloads Wi-Fi and Internet
Protocols from the External Microcontroller
– Wi-Fi Driver and Multiple Internet Protocols in
ROM
– 802.11 b/g/n Radio, Baseband, and Medium
Access Control (MAC), Wi-Fi Driver, and
Supplicant
– TCP/IP Stack
• Industry-Standard BSD Socket Application
Programming Interfaces (APIs)
• 8 Simultaneous TCP or UDP Sockets
• 2 Simultaneous TLS and SSL Sockets
– Powerful Crypto Engine for Fast, Secure Wi-Fi
and Internet Connections with 256-Bit AES
Encryption for TLS and SSL Connections
– Station, AP, and Wi-Fi Direct® Modes
– WPA2 Personal and Enterprise Security
– SimpleLink Connection Manager for
Autonomous and Fast Wi-Fi Connections
– SmartConfig™ Technology, AP Mode, and
WPS2 for Easy and Flexible Wi-Fi Provisioning
– TX Power
• 18.0 dBm @ 1 DSSS
• 14.5 dBm @ 54 OFDM
•
•
•
•
– RX Sensitivity
• –95.7 dBm @ 1 DSSS
• –74.0 dBm @ 54 OFDM
– Application Throughput
• UDP: 16 Mbps
• TCP: 13 Mbps
Host Interface
– Interfaces with 8-, 16-, and 32-Bit MCU or
ASICs Over SPI or UART Interface
– Low External Host Driver Footprint: Less Than
7KB of Code Memory and 700 B of RAM
Memory Required for TCP Client Application
Power-Management Subsystem
– Integrated DC-DC Supports a Wide Range of
Supply Voltage:
• VBAT Wide-Voltage Mode: 2.1 to 3.6 V
• Preregulated 1.85-V Mode
– Advanced Low-Power Modes
• Hibernate with RTC: 4 µA
• Low-Power Deep Sleep (LPDS): 115 µA
• RX Traffic (MCU Active): 53 mA @
54 OFDM
• TX Traffic (MCU Active): 223 mA @
54 OFDM, Maximum Power
• Idle Connected: 690 µA @ DTIM = 1
Clock Source
– 40.0-MHz Crystal with Internal Oscillator
– 32.768-kHz Crystal or External RTC Clock
Package and Operating Temperature
– 0.5-mm Pitch, 64-Pin, 9-mm × 9-mm QFN
– Ambient Temperature Range: –40°C to 85°C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC3100
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
1.2
•
www.ti.com
Applications
For Internet-of-Things applications, such as:
– Cloud Connectivity
– Home Automation
– Home Appliances
– Access Control
– Security Systems
– Smart Energy
1.3
–
–
–
–
–
Internet Gateway
Industrial Control
Smart Plug and Metering
Wireless Audio
IP Network Sensor Nodes
Description
Connect any low-cost, low-power microcontroller (MCU) to the Internet of Things (IoT). The CC3100
device is the industry's first Wi-Fi CERTIFIED chip used in the wireless networking solution. The CC3100
device is part of the new SimpleLink Wi-Fi family that dramatically simplifies the implementation of Internet
connectivity. The CC3100 device integrates all protocols for Wi-Fi and Internet, which greatly minimizes
host MCU software requirements. With built-in security protocols, the CC3100 solution provides a robust
and simple security experience. Additionally, the CC3100 device is a complete platform solution including
various tools and software, sample applications, user and programming guides, reference designs and the
TI E2E™ support community. The CC3100 device is available in an easy-to-layout QFN package.
The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a-Chip and contains an additional
dedicated ARM MCU that completely offloads the host MCU. This subsystem includes an 802.11 b/g/n
radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit
encryption. The CC3100 device supports Station, Access Point, and Wi-Fi Direct modes. The device also
supports WPA2 personal and enterprise security and WPS 2.0. This subsystem includes embedded
TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols.
The power-management subsystem includes integrated DC-DC converters supporting a wide range of
supply voltages. This subsystem enables low-power consumption modes, such as the hibernate with RTC
mode requiringabout 4 μA of current.
The CC3100 device can connect to any 8, 16, or 32-bit MCU over the SPI or UART Interface. The device
driver minimizes the host memory footprint requirements requiring less than 7KB of code memory and 700
B of RAM memory for a TCP client application.
Device Information (1)
PART NUMBER
CC3100R11MRGCR/T
(1)
2
PACKAGE
BODY SIZE
QFN (64)
9.0 mm x 9.0 mm
For all available packages, see the orderable addendum at the end of the datasheet.
Device Overview
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1.4
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
Functional Block Diagram
Figure 1-1 shows the CC3100 hardware overview.
RAM
WiFi Driver
TCP/IP & TLS/SSL
Stacks
ROM
Crypto Engine
ARM Processor
MAC Processor
UART
DC2DC
BAT Monitor
Oscillators
SYSTEM
Synthesizer
PA
HOST I/F
SPI
Baseband
Radio
LNA
SWAS031-A
Figure 1-1. CC3100 Hardware Overview
Figure 1-2 shows an overview of the CC3100 embedded software.
User Application
SimpleLink Driver
SPI or UART Driver
External Microcontroller
Internet Protocols
TLS/SSL
Embedded Internet
TCP/IP
Supplicant
Wi-Fi Driver
Wi-Fi MAC
Embedded Wi-Fi
Wi-Fi Baseband
Wi-Fi Radio
ARM Processor (Wi-Fi Network Processor)
SWAS031-B
Figure 1-2. CC3100 Software Overview
Device Overview
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CC3100
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
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Table of Contents
1
2
3
Device Overview ......................................... 1
4.12
External Interfaces
1.1
Features .............................................. 1
4.13
Host UART .......................................... 23
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
5.1
Overview
1.4
Functional Block Diagram ............................ 3
5.2
Functional Block Diagram ........................... 27
Revision History ......................................... 4
Terminal Configuration and Functions .............. 5
5.3
Wi-Fi Network Processor Subsystem ............... 27
5.4
Power-Management Subsystem .................... 28
Pin Attributes ......................................... 5
5.5
Low-Power Operating Modes ....................... 29
............................................ 8
Absolute Maximum Ratings .......................... 8
Handling Ratings ..................................... 8
Power-On Hours ...................................... 8
Recommended Operating Conditions ................ 8
Brown-Out and Black-Out ............................ 9
Electrical Characteristics (3.3 V, 25°C) ............. 10
WLAN Receiver Characteristics .................... 10
WLAN Transmitter Characteristics .................. 10
Current Consumption ............................... 11
Thermal Characteristics for RGC Package ......... 13
Timing and Switching Characteristics ............... 13
5.6
Memory .............................................. 29
3.1
4
5
Specifications
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
..................................
22
Detailed Description ................................... 26
............................................
26
6
Applications and Implementation ................... 31
7
Device and Documentation Support ............... 35
6.1
8
Application Information .............................. 31
7.1
Device Support ...................................... 35
7.2
Documentation Support ............................. 36
7.3
Community Resources .............................. 36
7.4
Trademarks.......................................... 36
7.5
Electrostatic Discharge Caution ..................... 36
7.6
Glossary ............................................. 36
Mechanical Packaging and Orderable
Information .............................................. 37
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2014) to Revision D
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
Page
Added Wi-Fi CERTIFIED ............................................................................................................ 1
Changed TCP value from 12 Mbps in Section 1.1, Features .................................................................. 1
Changed part number in Device Information table from CC3100 .............................................................. 2
Changed pin 19 from NC and pin 18 from reserved in Figure 3-1 ............................................................. 5
Changed pin 19 from NC in Table 3-1 ............................................................................................. 6
Added to pin 2 (nHIB) description in Table 3-1 ................................................................................... 6
Changed pins 8 and 14 to active low .............................................................................................. 6
Changed pin 15 to active high ..................................................................................................... 6
Added note in Section 4.4, Recommended Operating Conditions, on avoiding the PA auto-protect feature ............ 8
Added Section 4.5, Brown-Out and Black-Out ................................................................................... 9
Added Table 4-1 ..................................................................................................................... 9
Added VIL (nRESET pin) and corresponding note in Section 4.6, Electrical Characteristics (3.3 V, 25°C) ............ 10
Added note on RX current measurement in Section 4.9 Current Consumption. ........................................... 11
Changed Thib_min description from "minimum pulse width of nHIB = 0" in Table 4-4 ...................................... 16
Added footnote in Table 4-4 to ensure that the nHIB pulse width is kept above the minimum requirement. .......... 16
Changed frequency accuracy from ±20 ppm in Table 4-5 .................................................................... 18
Added 4.11.3.6, WLAN Filter Requirements .................................................................................... 19
Added note on asserting nCS (active low signal) in Table 4-10 .............................................................. 20
Changed HOST_SPI_CS to HOST_SPI_nCS in Table 4-13 .................................................................. 23
Changed H_IRQ to HOST_INTR(IRQ) in Figure 4-17 ......................................................................... 24
Changed TCP of item 17 from 12 Mbps in Table 5-1 .......................................................................... 28
Changed part number of item 13 from XCC3100RTD in Table 6-1 ......................................................... 32
Added note following Table 6-1 ................................................................................................... 32
Changed part number of item 13 from XCC3100RTD in Table 6-2 .......................................................... 34
Added note following Table 6-2 ................................................................................................... 34
Revision History
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3 Terminal Configuration and Functions
SOP1
VDD_PA_IN
37
LDO_IN1
38
SOP0
39
DCDC_ANA_SW
40
VIN_DCDC_ANA
41
DCDC_PA_SW_P
42
VIN_DCDC_PA
43
DCDC_PA_OUT
44
DCDC_PA_SW_N
45
VIN_DCDC_DIG
46
DCDC_DIG_SW
47
DCDC_ANA2_SW_N
48
DCDC_ANA2_SW_P
VDD_ANA1
VDD_ANA2
Figure 3-1 shows pin assignments for the 64-pin QFN package.
36
35
34
33
VDD_RAM
49
32
nRESET
UART1_nRTS
50
31
RF_BG
RTC_XTAL_P
51
30
RESERVED
RTC_XTAL_N
52
29
RESERVED
NC
53
28
NC
VIN_IO2
54
27
NC
UART1_TX
55
26
NC
VDD_DIG2
56
25
LDO_IN2
UART1_RX
57
24
VDD_PLL
TEST_58
58
23
WLAN_XTAL_P
TEST_59
59
22
WLAN_XTAL_N
TEST_60
60
21
SOP2/TCXO_EN
UART1_nCTS
61
20
NC
TEST_62
62
19
RESERVED
NC
63
18
NC
NC
64
17
NC
HOST_SPI_MISO
HOST_SPI_nCS
VDD_DIG1
VIN_IO1
11
12
13
14
15
16
NC
10
HOSTINTR
9
FLASH_SPI_CS
8
FLASH_SPI_MISO
7
FLASH_SPI_CLK
6
FLASH_SPI_MOSI
5
HOST_SPI_CLK
4
HOST_SPI_MOSI
NC
3
RESERVED
2
FORCE_AP
1
nHIB
CC3100
Figure 3-1. QFN 64-Pin Assignments (Top View)
3.1
Pin Attributes
Table 3-1 describes the CC3100 pins.
NOTE
If an external device drives a positive voltage to signal pads when the CC3100 device is not
powered, DC current is drawn from the other device. If the drive strength of the external
device is adequate, an unintentional wakeup and boot of the CC3100 device can occur. To
prevent current draw, TI recommends one of the following:
• All devices interfaced to the CC3100 device must be powered from the same power rail
as the CC3100 device.
• Use level-shifters between the CC3100 device and any external devices fed from other
independent rails.
• The nRESET pin of the CC3100 device must be held low until the VBAT supply to the
device is driven and stable.
Terminal Configuration and Functions
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SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
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Table 3-1. Pin Attributes
PIN
(1)
6
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE
DESCRIPTION
1
NC
Hi-Z
N/A
2
nHIB
Hi-Z
I
3
Reserved
Hi-Z
NA
4
FORCE_AP
Hi-Z
I
For forced AP mode, pull to high on the board
using 100k resistor. Otherwise, pull down to
ground using 100k resistor. (1)
5
HOST_SPI_CLK
Hi-Z
I
Host interface SPI clock
6
HOST_SPI_MOSI
Hi-Z
I
Host interface SPI data input
7
HOST_SPI_MISO
Hi-Z
O
Host interface SPI data output
8
HOST_SPI_nCS
Hi-Z
I
Host interface SPI chip select (active low)
9
VDD_DIG1
Hi-Z
Power
Digital core supply (1.2 V)
10
VIN_IO1
Hi-Z
Power
I/O supply
11
FLASH_SPI_CLK
Hi-Z
O
Serial flash interface: SPI clock
12
FLASH_SPI_MOSI
Hi-Z
O
Serial flash interface: SPI data out
13
FLASH _SPI_MISO
(active high)
Hi-Z
I
Serial flash interface: SPI data in
14
FLASH _SPI_nCS
Hi-Z
O
Serial flash interface: SPI chip select (active
low)
15
HOST_INTR
Hi-Z
O
Interrupt output (active high)
16
NC
Hi-Z
N/A
Unused; leave unconnected.
17
NC
Hi-Z
N/A
Unused; leave unconnected.
18
NC
Hi-Z
N/A
Unused; leave unconnected.
19
Reserved
Hi-Z
N/A
Connect 100K pull-down to ground.
20
NC
Hi-Z
N/A
Unused; leave unconnected.
21
SOP2/TCXO_EN
Hi-Z
O
22
WLAN_XTAL_N
Hi-Z
Analog
Connect the WLAN 40-MHz XTAL here.
23
WLAN_XTAL_P
Hi-Z
Analog
Connect the WLAN 40-MHz XTAL here.
24
VDD_PLL
Hi-Z
Power
Internal PLL power supply (1.4 V nominal)
25
LDO_IN2
Hi-Z
Power
Input to internal LDO
26
NC
Hi-Z
N/A
Unused; leave unconnected.
27
NC
Hi-Z
N/A
Unused; leave unconnected.
28
NC
Hi-Z
N/A
Unused; leave unconnected.
29
Reserved
Hi-Z
O
Reserved for future use
30
Reserved
Hi-Z
O
Reserved for future use
31
RF_BG
Hi-Z
RF
2.4-GHz RF TX/RX
32
nRESET
Hi-Z
I
RESET input for the device. Active low input.
Use RC circuit (100k || 0.1 µF) for power on
reset.
33
VDD_PA_IN
Hi-Z
Power
Power supply for the RF power amplifier (PA)
34
SOP1
Hi-Z
N/A
Add 100K pulldown to ground.
35
SOP0
Hi-Z
N/A
Add 100K pulldown to ground.
36
LDO_IN1
Hi-Z
Power
Input to internal LDO
37
VIN_DCDC_ANA
Hi-Z
Power
Power supply for the DC-DC converter for
analog section
Unused; leave unconnected.
Hibernate signal input to the NWP (active low).
This is connected to the MCU GPIO. If the
GPIO from the MCU can float while the MCU
enters low power, consider adding a pull-up
resistor on the board to avoid floating.
Reserved for future use
Enable signal for external TCXO. Add 10k
pulldown to ground.
Using a configuration file stored on flash, the vendor can optionally block any possibility of bringing up AP using the FORCE_AP pin.
Terminal Configuration and Functions
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SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
Table 3-1. Pin Attributes (continued)
PIN
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE
DESCRIPTION
38
DCDC_ANA_SW
Hi-Z
Power
Analog DC-DC converter switch output
39
VIN_DCDC_PA
Hi-Z
Power
PA DC-DC converter input supply
40
DCDC_PA_SW_P
Hi-Z
Power
PA DC-DC converter switch output +ve
41
DCDC_PA_SW_N
Hi-Z
Power
PA DC-DC converter switch output –ve
42
DCDC_PA_OUT
Hi-Z
Power
PA DC-DC converter output. Connect the
output capacitor for DC-DC here.
43
DCDC_DIG_SW
Hi-Z
Power
Digital DC-DC converter switch output
44
VIN_DCDC_DIG
Hi-Z
Power
Power supply input for the digital DC-DC
converter
45
DCDC_ANA2_SW_P
Hi-Z
Power
Analog2 DC-DC converter switch output +ve
46
DCDC_ANA2_SW_N
Hi-Z
Power
Analog2 DC-DC converter switch output –ve
47
VDD_ANA2
Hi-Z
Power
Analog2 power supply input
48
VDD_ANA1
Hi-Z
Power
Analog1 power supply input
49
VDD_RAM
Hi-Z
Power
Power supply for the internal RAM
50
UART1_nRTS
Hi-Z
O
51
RTC_XTAL_P
Hi-Z
Analog
32.768 kHz XTAL_P/external CMOS level
clock input
52
RTC_XTAL_N
Hi-Z
Analog
32.768 kHz XTAL_N/100k external pullup for
external clock
53
NC
Hi-Z
N/A
54
VIN_IO2
Hi-Z
Power
55
UART1_TX
Hi-Z
O
56
VDD_DIG2
Hi-Z
Power
57
UART1_RX
Hi-Z
I
UART host interface. Connect to test point on
prototype for flash programming.
58
TEST_58
N/A
Test signal. Connect to an external test point.
59
TEST_59
N/A
Test signal. Connect to an external test point.
UART host interface
Unused. Leave unconnected.
I/O power supply. Same as battery voltage.
UART host interface. Connect to test point on
prototype for flash programming.
Digital power supply (1.2 V)
60
TEST_60
Hi-Z
O
Test signal. Connect to an external test point.
61
UART1_nCTS
Hi-Z
I
UART host interface
62
TEST_62
Hi-Z
O
Test signal. Connect to an external test point.
63
NC
Hi-Z
I/O
Leave unconnected
64
NC
Hi-Z
I/O
Leave unconnected
65
GND
Power
Ground tab used as thermal and electrical
ground
Terminal Configuration and Functions
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4 Specifications
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over
process and voltage, unless otherwise indicated.
4.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
VBAT and VIO
VIO-VBAT (differential)
PINS
MIN
MAX
UNIT
37, 39, 44
–0.5
3.8
V
0.0
V
10, 54
Digital inputs
–0.5
VIO + 0.5
V
RF pins
–0.5
2.1
V
Analog pins (XTAL)
–0.5
2.1
V
Operating temperature range (TA )
–40
+85
°C
4.2
Handling Ratings
Tstg
VESD
(1)
(2)
4.3
MIN
MAX
UNIT
–55
+125
°C
–2000
+2000
V
–500
+500
V
Storage temperature range
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins (1)
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Power-On Hours
CONDITIONS
POH
17,500 (1)
TAmbient up to 85°C, assuming 20% active mode and 80% sleep mode
(1)
4.4
The CC3100 device can be operated reliably for 10 years.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
PINS
CONDITIONS
(1) (2)
(3) (4)
MIN
TYP
MAX
UNIT
VBAT, VIO (shorted to VBAT)
10, 37, 39,
44, 54
Direct battery connection
2.1
3.3
3.6
V
VBAT, VIO (shorted to VBAT)
10, 37, 39,
44, 54
Preregulated 1.85 V
1.76
1.85
1.9
V
20
°C/minute
Ambient thermal slew
–20
(1)
(2)
Operating temperature is limited by crystal frequency variation.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the transmission.
(3)
(4)
To ensure WLAN performance, ripple on the 2.1- to 3.3-V supply must be less than ±300 mV.
To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV).
8
Specifications
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4.5
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
Brown-Out and Black-Out
The device enters a brown-out condition whenever the input voltage dips below VBROWN (see Figure 4-1 and
Figure 4-2). This condition must be considered during design of the power supply routing, especially if operating
from a battery. High-current operations (such as a TX packet) cause a dip in the supply voltage, potentially
triggering a brown-out. The resistance includes the internal resistance of the battery, contact resistance of the
battery holder (4 contacts for a 2 x AA battery) and the wiring and PCB routing resistance.
Figure 4-1. Brown-Out and Black-Out Levels (1 of 2)
Figure 4-2. Brown-Out and Black-Out Levels (2 of 2)
In the brown-out condition, all sections of the device shut down except for the Hibernate module (including the
32-kHz RTC clock), which remains on. The current in this state can reach approximately 400 µA.
The black-out condition is equivalent to a hardware reset event in which all states within the device are lost.
Table 4-1 lists the brown-out and black-out voltage levels.
Table 4-1. Brown-Out and Black-out Voltage Levels
VOLTAGE LEVEL
UNIT
Vbrownout
CONDITION
2.1
V
Vblackout
1.67
V
Specifications
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4.6
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Electrical Characteristics (3.3 V, 25°C)
PARAMETER
TEST
CONDITIONS
MIN
NOM
MAX
4
UNIT
CIN
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
pF
VIL
Low-level input voltage
–0.5
IIH
High-level input current
5
nA
IIL
Low-level input current
5
nA
VOH
High-level output voltage
(VDD = 3.0 V)
VOL
Low-level output voltage
(VDD = 3.0 V)
IOH
High-level source current, VOH = 2.4
6
mA
IOL
Low-level sink current, VOH = 0.4
6
mA
VDD + 0.5 V
0.35 × VDD
2.4
V
V
V
0.4
V
Pin Internal Pullup and Pulldown (25°C)
PARAMETER
TEST
CONDITIONS
MIN
IOH
Pull-Up current, VOH = 2.4
(VDD = 3.0 V)
5
IOL
Pull-Down current, VOL = 0.4
(VDD = 3.0 V)
5
VIL
nRESET (1)
(1)
4.7
NOM
MAX
10
UNIT
µA
µA
0.6
V
The nRESET pin must be held below 0.6 V for the device to register a reset.
WLAN Receiver Characteristics
TA = +25°C, VBAT = 2.1 to 3.6 V. Parameters measured at SoC pin on channel 7 (2442 MHz)
Parameter
Condition (Mbps)
Sensitivity
(8% PER for 11b rates, 10% PER for
11g/11n rates)(10% PER) (1)
Typ
–95.7
2 DSSS
–93.6
11 CCK
–88.0
6 OFDM
–90.0
9 OFDM
–89.0
18 OFDM
–86.0
36 OFDM
–80.5
54 OFDM
–74.0
MCS0 (GF) (2)
–89.0
MCS7 (GF) (2)
–71.0
802.11b
–4.0
802.11g
–10.0
Maximum input level
(10% PER)
(1)
(2)
Min
1 DSSS
Max
Units
dBm
Sensitivity is 1-dB worse on channel 13 (2472 MHz).
Sensitivity for mixed mode is 1-dB worse.
4.8
WLAN Transmitter Characteristics
10
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TA = +25°C, VBAT = 2.1 to 3.6 V. Parameters measured at SoC pin on channel 7 (2442 MHz). (1)
Condition (2)
Parameter
2 DSSS
18.0
11 CCK
18.3
6 OFDM
17.3
9 OFDM
17.3
18 OFDM
17.0
36 OFDM
16.0
54 OFDM
14.5
MCS7 (MM)
13.0
Transmit center frequency accuracy
(2)
Typ
18.0
Maximum RMS output power measured at
1 dB from IEEE spectral mask or EVM
(1)
Min
1 DSSS
–25
Max
Units
dBm
25
ppm
Channel-to-channel variation is up to 2 dB. The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission
limits.
In preregulated 1.85-V mode, maximum TX power is 0.25 to 0.75 dB lower for modulations higher than 18 OFDM.
4.9
Current Consumption
TA = +25°C, VBAT = 3.6 V
TEST CONDITIONS (1)
PARAMETER
1 DSSS
TX
6 OFDM
54 OFDM
MIN
TYP (3) MAX UNIT
TX power level = 0
272
TX power level = 4
188
TX power level = 0
248
TX power level = 4
179
TX power level = 0
223
TX power level = 4
160
1 DSSS
RX (4)
(2)
53
54 OFDM
53
Idle connected (5)
0.690
LPDS
0.115
Hibernate
(6)
Peak calibration current
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
(7) (4)
mA
VBAT = 3.3 V
450
VBAT = 2.1 V
670
VBAT = 1.85 V
700
µA
mA
TX power level = 0 implies maximum power (see Figure 4-3 through Figure 4-5). TX power level = 4 implies output power backed off
approximately 4 dB.
The CC3100 system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
External serial-flash-current consumption is not included.
The RX current is measured with a 1-Mbps throughput rate.
DTIM = 1
For the 1.85-V mode, the Hibernate current is higher by 50 µA across all operating modes because of leakage into the PA and analog
power inputs.
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms . Calibration is performed sparingly,
typically when coming out of Hibernate and only if temperature has changed by more than 20°C or the time elapsed from prior
calibration is greater than 24 hours.
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1 DSSS
19.00
280.00
Color by
17.00
264.40
TX Power (dBm)
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
TX Power (dBm)
15.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Note: The area enclosed in the circle represents a significant reduction in current when transitioning from TX power
level 3 to 4. In the case of lower range requirements (14 dbm output power), TI recommends using TX power level 4
to reduce the current.
Figure 4-3. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 4-4. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
12
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54 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 4-5. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
4.10 Thermal Characteristics for RGC Package
AIR FLOW
PARAMETER
0 lfm (C/W)
150 lfm (C/W)
250 lfm (C/W)
500 lfm (C/W)
θja
23
14.6
12.4
10.8
Ψjt
0.2
0.2
0.3
0.1
Ψjb
2.3
2.3
2.2
2.4
θjc
6.3
θjb
2.4
4.11 Timing and Switching Characteristics
4.11.1 Power Supply Sequencing
For proper operation of the CC3100 device, perform the recommended power-up sequencing as follows:
1. Tie VBAT (pins 37, 39, 44) and VIO (pins 54 and 10) together on the board.
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100K ||
0.1 µF, RC = 10 ms).
3. For an external RTC clock, ensure that the clock is stable before RESET is deasserted (high).
For timing diagrams, see Section 4.11.2, Reset Timing.
4.11.2 Reset Timing
4.11.2.1 nRESET (32K XTAL)
Figure 4-6 shows the reset timing diagram for the 32K XTAL first-time power-up and reset removal.
Specifications
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Figure 4-6. First-Time Power-Up and Reset Removal Timing Diagram (32K XTAL)
Table 4-2 describes the timing requirements for the 32K XTAL first-time power-up and reset removal.
Table 4-2. First-Time Power-Up and Reset Removal Timing Requirements (32K XTAL)
Item
Name
Description
T1
Supply settling time
Depends on
application board
power supply, decap,
and so on
T2
Hardware wakeup
time
T3
Initialization time
14
Min
Typ
Max
3 ms
25 ms
32-kHz XTAL settling
+ firmware
initialization time +
radio calibration
Specifications
1.35 s
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4.11.2.2 nRESET (External 32K)
Figure 4-7 shows the reset timing diagram for the external 32K first-time power-up and reset removal.
Figure 4-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32K)
Table 4-3 describes the timing requirements for the external 32K first-time power-up and reset removal.
Table 4-3. First-Time Power-Up and Reset Removal Timing Requirements (External 32K)
Item
Name
Description
T1
Supply settling time
Depends on
application board
power supply, decap,
and so on
T2
Hardware wakeup
time
T3
Initialization time
Min
Typ
Max
3 ms
25 ms
Firmware initialization
time + radio
calibration
250 ms
Specifications
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4.11.2.3 Wakeup from Hibernate
Figure 4-8 shows the timing diagram for wakeup from the hibernate state.
Figure 4-8. nHIB Timing Diagram
NOTE
The 32.768-kHz XTAL is kept enabled by default when the chip goes to hibernate in response to
nHIB being pulled low.
Table 4-4 describes the timing requirements for nHIB.
Table 4-4. nHIB Timing Requirements
Item
Name
Description
Min
Thib_min
Minimum hibernate
time
Minimum pulse width
of nHIB being low (1)
10 ms
Twake_from_hib
Hardware wakeup
time plus firmware
initialization time
See
(2)
.
Typ
Max
50 ms
(1)
Ensure that the nHIB pulse width is kept above the minimum requirement under all conditions (such as power up, MCU reset, and so
on).
(2)
If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.
4.11.3 Clock Specifications
The CC3100 device requires two separate clocks for its operation:
• A slow clock running at 32.768 kHz is used for the RTC.
• A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.
The device features internal oscillators that enable the use of cheaper crystals rather than dedicated TCXOs for
these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system and reduce
overall cost.
16
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4.11.3.1 Slow Clock Using Internal Oscillator
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock
frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P
(pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance.
Figure 4-9 shows the crystal connections for the slow clock.
51
RTC_XTAL_P
10 pF
GND
32.768 kHz
RTC_XTAL_N
52
10 pF
GND
SWAS031-028
Figure 4-9. RTC Crystal Connections
4.11.3.2 Slow Clock Using an External Clock
When an RTC clock oscillator is present in the system, the CC3100 device can accept this clock directly as an
input. The clock is fed on the RTC_XTAL_P line and the RTC_XTAL_N line is held to VIO. The clock must be a
CMOS-level clock compatible with VIO fed to the device.
Figure 4-10 shows the external RTC clock input connection.
RTC_XTAL_P
32.768 kHz
VIO
Host system
100 K
RTC_XTAL_N
SWAS031-029
Figure 4-10. External RTC Clock Input
4.11.3.3 Fast Clock (Fref) Using an External Crystal
The CC3100 device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The
XTAL is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading
capacitors.
Figure 4-11 shows the crystal connections for the fast clock.
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23
WLAN_XTAL_P
6.2 pF
GND
40 MHz
WLAN_XTAL_N
22
6.2 pF
GND
SWAS031-030
Figure 4-11. Fast Clock Crystal Connections
4.11.3.4 Fast Clock (Fref) Using an External Oscillator
The CC3100 device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the clock
is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external TCXO/XO
can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the
LDO improves noise on the TCXO power supply.
Figure 4-12 shows the connection.
Vcc
XO (40MHz)
CC3200
EN
TCXO_EN
82 pF
WLAN_XTAL_P
OUT
WLAN_XTAL_N
SWAS031-087
Figure 4-12. External TCXO Input
Table 4-5 lists the external Fref clock requirements.
Table 4-5. External Fref Clock Requirements (–40°C to +85°C)
Characteristics
Condition
Sym
Min
Frequency
Typ
Max
40.00
Frequency accuracy (Initial + temp + aging)
±25
Frequency input duty cycle
45
Vpp
0.7
50
Unit
MHz
ppm
55
%
1.2
Vpp
Clock voltage limits
Sine or clipped
sine wave, AC
coupled
Phase noise @ 40 MHz
@ 1 kHz
–125
dBc/Hz
@ 10 kHz
–138.5
dBc/Hz
–143
dBc/Hz
@ 100 kHz
Input impedance
Resistance
12
Capacitance
18
KΩ
7
Specifications
pF
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4.11.3.5 Input Clocks/Oscillators
Table 4-6 lists the RTC crystal requirements.
Table 4-6. RTC Crystal Requirements
CHARACTERISTICS
CONDITION
SYM
MIN
TYP
MAX
UNIT
Initial + temp + aging
±150
ppm
32.768 kHz, C1 = C2 = 10 pF
70
kΩ
MAX
UNIT
±150
ppm
100
ns
80
%
Frequency
32.768
Frequency accuracy
Crystal ESR
kHz
Table 4-7 lists the external RTC digital clock requirements.
Table 4-7. External RTC Digital Clock Requirements
CHARACTERISTICS
CONDITION
SYM
MIN
TYP
Frequency
32768
Hz
Frequency accuracy
(Initial + temp + aging)
Input transition time tr/tf (10% to 90%)
tr/tf
Frequency input duty cycle
Slow clock input voltage limits
20
Square wave, DC coupled
50
Vih
0.65 × VIO
VIO
V
Vil
0
0.35 × VIO
V peak
Input impedance
1
MΩ
5
pF
MAX
UNIT
Table 4-8 lists the WLAN fast-clock crystal requirements.
Table 4-8. WLAN Fast-Clock Crystal Requirements
CHARACTERISTICS
CONDITION
SYM
MIN
TYP
Frequency
40
Frequency accuracy
Crystal ESR
MHz
Initial + temp + aging
40 MHz, C1 = C2 = 6.2 pF
40
50
±25
ppm
60
Ohm
4.11.3.6 WLAN Filter Requirements
The device requires an external bandpass filter to meet the various emission standards, including FCC. Table 49 presents the attenuation requirements for the bandpass filter. TI recommends using the same filter used in the
reference design to ease the process of certification.
Table 4-9. WLAN Filter Requirements
Parameter
Return loss
Insertion loss
(1)
Frequency (MHz)
2412 to 2484
(1)
Requirements
Min
Typ
Max
10
2412 to 2484
Units
dB
1
1.5
dB
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
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Table 4-9. WLAN Filter Requirements (continued)
Parameter
Requirements
Frequency (MHz)
Attenuation
Reference Impendence
Min
Typ
800 to 830
30
45
1600 to 1670
20
25
3200 to 3300
30
48
4000 to 4150
45
50
4800 to 5000
20
25
5600 to 5800
20
25
6400 to 6600
20
35
7200 to 7500
35
45
7500 to 10000
20
25
2412 to 2484
Filter type
Max
Units
dB
Ω
50
Bandpass
4.11.4 Interfaces
This section describes the interfaces that are supported by the CC3100 device:
• Host SPI
• Flash SPI
• Host UART
4.11.4.1 Host SPI Interface Timing
I2
CLK
I6
I7
MISO
I9
I8
MOSI
SWAS032-017
Figure 4-13. Host SPI Interface Timing
Table 4-10. Host SPI Interface Timing Parameters
Parameter
Number
I1
(1)
(2)
20
Parameter
F
(1)
Parameter Name
Min
Max
Unit
Clock frequency @ VBAT = 3.3 V
20
MHz
Clock frequency @ VBAT ≤ 2.1 V
12
I2
tclk (2)
Clock period
I3
tLP
Clock low period
25
ns
I4
tHT
Clock high period
25
ns
50
I5
D
Duty cycle
45
I6
tIS
RX data setup time
4
4
I7
tIH
RX data hold time
I8
tOD
TX data output delay
ns
55
%
ns
ns
20
The timing parameter has a maximum load of 20 pf at 3.3 V.
Ensure that nCS (active-low signa)l is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge.
Specifications
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Table 4-10. Host SPI Interface Timing Parameters (continued)
Parameter
Number
Parameter (1)
Parameter Name
I9
tOH
TX data hold time
Min
Max
Unit
24
ns
4.11.4.2 Flash SPI Interface Timing
I2
CLK
I6
I7
MISO
I8
I9
MOSI
SWAS032-017
Figure 4-14. Flash SPI Interface Timing
Specifications
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Table 4-11. Flash SPI Interface Timing Parameters
Parameter
Number
Parameter
Parameter Name
Min
Max
Unit
I1
F
Clock frequency
20
MHz
I2
tclk
Clock period
I3
tLP
Clock low period
25
ns
I4
tHT
Clock high period
25
ns
50
ns
I5
D
Duty cycle
45
I6
tIS
RX data setup time
1
55
ns
%
I7
tIH
RX data hold time
2
ns
I8
tOD
TX data output delay
8.5
ns
I9
tOH
TX data hold time
8
ns
4.12 External Interfaces
4.12.1 SPI Flash Interface
The external serial flash stores the user profiles and firmware patch updates. The CC3100 device acts as
a master in this case; the SPI serial flash acts as the slave device. This interface can work up to a speed
of 20 MHz.
Figure 4-15 shows the SPI flash interface.
CC3100 (master)
Serial flash
FLASH_SPI_CLK
SPI_CLK
FLASH_SPI_nCS
SPI_CS
FLASH_SPI_MISO
SPI_MISO
FLASH_SPI_MOSI
SPI_MOSI
SWAS031-026
Figure 4-15. SPI Flash Interface
Table 4-12 lists the SPI flash interface pins.
Table 4-12. SPI Flash Interface
Pin Name
Description
FLASH_SPI_CLK
Clock (up to 20 MHz) CC3100 device to serial flash
FLASH_SPI_CS
CS (active low) signal from CC3100 device to serial flash
FLASH_SPI_MISO
Data from serial flash to CC3100 device
FLASH_SPI_MOSI
Data from CC3100 device to serial flash
4.12.2 SPI Host Interface
The device interfaces to an external host using the SPI interface. The CC3100 device can interrupt the
host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can
work up to a speed of 20 MHz.
Figure 4-16 shows the SPI host interface.
22
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CC3100 (slave)
MCU
HOST_SPI_CLK
SPI_CLK
HOST_SPI_nCS
SPI_nCS
HOST_SPI_MISO
SPI_MISO
HOST_SPI_MOSI
SPI_MOSI
HOST_INTR
INTR
nHIB
GPIO
SWAS031-027
Figure 4-16. SPI Host Interface
Table 4-13 lists the SPI host interface pins.
Table 4-13. SPI Host Interface
Pin Name
Description
HOST_SPI_CLK
Clock (up to 20 MHz) from MCU host to CC3100 device
HOST_SPI_nCS
CS (active low) signal from MCU host to CC3100 device
HOST_SPI_MOSI
Data from MCU host to CC3100 device
HOST_INTR
Interrupt from CC3100 device to MCU host
HOST_SPI_MISO
Data from CC3100 device to MCU host
nHIB
Active-low signal that commands the CC3100 device to enter hibernate mode (lowest power
state)
4.13 Host UART
The SimpleLink device requires the UART configuration described in Table 4-14.
Table 4-14. SimpleLink UART Configuration
Property
Supported CC3100 Configuration
Baud rate
115200 bps, no auto-baud rate detection, can be changed by the host up to 3 Mbps using a special command
Data bits
8 bits
Flow control
CTS/RTS
Parity
None
Stop bits
1
Bit order
LSBit first
Host interrupt polarity
Active high
Host interrupt mode
Rising edge or level 1
Endianness
Little-endian only (1)
(1)
The SimpleLink device does not support automatic detection of the host length while using the UART interface.
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4.13.1 5-Wire UART Topology
Figure 4-17 shows the typical 5-wire UART topology comprised of 4 standard UART lines plus one IRQ
line from the device to the host controller to allow efficient low power mode.
HOST MCU
UART
RTS
RTS
CTS
CTS
TX
TX
RX
RX
HOST_INTR(IRQ)
CC3100 SL
UART
HOST_INTR(IRQ)
SWAS031-088
Figure 4-17. Typical 5-Wire UART Topology
This is the typical and recommended UART topology because it offers the maximum communication
reliability and flexibility between the host and the SimpleLink device.
4.13.2 4-Wire UART Topology
The 4-wire UART topology eliminates the host IRQ line (see Figure 4-18). Using this topology requires
one of the following conditions to be met:
• Host is always awake or active.
• Host goes to sleep but the UART module has receiver start-edge detection for auto wakeup and does
not lose data.
HOST MCU
UART
RTS
RTS
CTS
CTS
TX
TX
RX
RX
X
H_IRQ
CC3100 SL
UART
H_IRQ
SWAS031-089
Figure 4-18. 4-Wire UART Configuration
4.13.3 3-Wire UART Topology
The 3-wire UART topology requires only the following lines (see Figure 4-19):
• RX
• TX
• CTS
RTS
RTS
X
CTS
CTS
HOST MCU
UART
TX
TX
RX
RX
H_IRQ
X
CC3100 SL
UART
H_IRQ
SWAS031-090
Figure 4-19. 3-Wire UART Topology
Using this topology requires one of the following conditions to be met:
• Host always stays awake or active.
24
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•
•
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Host goes to sleep but the UART module has receiver start-edge detection for auto wakeup and does
not lose data.
Host can always receive any amount of data transmitted by the SimpleLink device because there is no
flow control in this direction.
Because there is no full flow control, the host cannot stop the SimpleLink device to send its data; thus, the
following parameters must be carefully considered:
• Max baud rate
• RX character interrupt latency and low-level driver jitter buffer
• Time consumed by the user's application
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5 Detailed Description
5.1
Overview
5.1.1
Device Features
5.1.1.1
•
•
•
•
•
•
5.1.1.2
•
•
•
•
5.1.1.3
•
•
•
5.1.1.4
•
•
•
26
WLAN
802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station
with CCK and OFDM rates in the 2.4-GHz ISM band
Auto-calibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna
without requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in an NVMEM allows
automatic fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators
SmartConfig technology: A 1-step, 1-time process to connect a CC3100-enabled device to the home
wireless network, removing dependency on the I/O capabilities of the host MCU; thus, it is usable by
deeply embedded applications.
802.11 transceiver mode: Allows transmitting and receiving of proprietary data through a socket
without adding MAC or PHY headers. This mode provides the option to select the working channel,
rate, and transmitted power. The receiver mode works together with the filtering options.
Network Stack
Integrated IPv4 TCP/IP stack with BSD socket APIs for simple Internet connectivity with any MCU,
microprocessor, or ASIC
Support of eight simultaneous TCP, UDP, or RAW sockets
Built-in network protocols: ARP, ICMP, DHCP client, and DNS client for easy connection to the local
network and the Internet
Service discovery: Multicast DNS service discovery lets a client advertise its service without a
centralized server. After connecting to the access point, the CC3100 device provides critical
information, such as device name, IP, vendor, and port number.
Host Interface and Driver
Interfaces over a 4-wire serial peripheral interface (SPI) with any MCU or a processor at a clock speed
of 20 MHz.
Interfaces over UART with any MCU with a baud rate up to 3 Mbps. A low footprint driver is provided
for TI MCUs and is easily ported to any processor or ASIC.
Simple APIs enable easy integration with any single-threaded or multithreaded application.
System
Works from a single preregulated power supply or connects directly to a battery
Ultra-low leakage when disabled (hibernate mode) with a current of less than 4 µA with the RTC
running
Integrated clock sources
Detailed Description
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Product Folder Links: CC3100
CC3100
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5.2
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
Functional Block Diagram
Figure 5-1 shows the functional block diagram of the CC3100 SimpleLink Wi-Fi solution.
VCC
SPI
FLASH
32-kHz
XTAL
40-MHz
XTAL
32 kHz
MCU
CC3100
Network processor
nHIB
HOST_INTR
SPI/UART
SWAS031-018
Figure 5-1. Functional Block Diagram
5.3
Wi-Fi Network Processor Subsystem
The Wi-Fi network processor subsystem includes a dedicated ARM MCU to completely offload the host
MCU along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast,
secure WLAN and Internet connections with 256-bit encryption. The CC3100 device supports station, AP,
and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0.
The Wi-Fi network processor includes an embedded IPv4 TCP/IP stack.
Table 5-1 summarizes the NWP features.
Table 5-1. Summary of Features Supported by the NWP Subsystem
Item
Domain
Category
Feature
1
TCP/IP
Network Stack
IPv4
Details
2
TCP/IP
Network Stack
TCP/UDP
3
TCP/IP
Protocols
DHCP
4
TCP/IP
Protocols
ARP
5
TCP/IP
Protocols
DNS/mDNS
DNS Address resolution and local server
6
TCP/IP
Protocols
IGMP
Up to IGMPv3 for multicast management
7
TCP/IP
Applications
mDNS
Support multicast DNS for service publishing over IP
8
TCP/IP
Applications
mDNS-SD
9
TCP/IP
Applications
Web Sever/HTTP Server
10
TCP/IP
Security
TLS/SSL
TLS v1.2 (client/server)/SSL v3.0
11
TCP/IP
Security
TLS/SSL
For the supported Cipher Suite, go to SimpleLink Wi-Fi
CC3100 SDK.
12
TCP/IP
Sockets
RAW Sockets
User-defined encapsulation at WLAN MAC/PHY or IP
layers
13
WLAN
Connection
Policies
Allows management of connection and reconnection
policy
14
WLAN
MAC
Promiscuous mode
Baseline IPv4 stack
Base protocols
Client and server mode
Support ARP protocol
Service discovery protocol over IP in local network
URL static and dynamic response with template.
Filter-based Promiscuous mode frame receiver
Detailed Description
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Product Folder Links: CC3100
27
CC3100
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
www.ti.com
Table 5-1. Summary of Features Supported by the NWP Subsystem (continued)
Item
Domain
Category
Feature
15
WLAN
Performance
Initialization time
16
WLAN
Performance
Throughput
UDP = 16 Mbps
17
WLAN
Performance
Throughput
TCP = 13 Mbps
18
WLAN
Provisioning
WPS2
19
WLAN
Provisioning
AP Config
20
WLAN
Provisioning
SmartConfig
21
WLAN
Role
Station
802.11bgn Station with legacy 802.11 power save
22
WLAN
Role
Soft AP
802.11 bg single station with legacy 802.11 power
save
23
WLAN
Role
P2P
P2P operation as GO
24
WLAN
Role
P2P
P2P operation as CLIENT
25
WLAN
Security
STA-Personal
26
WLAN
Security
STA-Enterprise
WPA2 enterprise security
27
WLAN
Security
STA-Enterprise
EAP-TLS
28
WLAN
Security
STA-Enterprise
EAP-PEAPv0/TLS
29
WLAN
Security
STA-Enterprise
EAP-PEAPv1/TLS
30
WLAN
Security
STA-Enterprise
EAP-PEAPv0/MSCHAPv2
31
WLAN
Security
STA-Enterprise
EAP-PEAPv1/MSCHAPv2
32
WLAN
Security
STA-Enterprise
EAP-TTLS/EAP-TLS
33
WLAN
Security
STA-Enterprise
EAP-TTLS/MSCHAPv2
34
WLAN
Security
AP-Personal
WPA2 personal security
5.4
Details
From enable to first connection to open AP less than
50 ms
Enrollee using push button or PIN method.
AP mode for initial product configuration (with
configurable Web page and beacon Info element)
Alternate method for initial product configuration
WPA2 personal security
Power-Management Subsystem
The CC3100 power-management subsystem contains DC-DC converters to accommodate the differing
voltage or current requirements of the system.
• Digital DC-DC
– Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
• ANA1 DC-DC
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the ANA1 DC-DC converter is bypassed.
• PA DC-DC
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the PA DC-DC converter is bypassed.
In preregulated 1.85-V mode, the ANA1 DC-DC and PA DC-DC converters are bypassed. The CC3100
device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage supply
range. The internal power management, including DC-DC converters and LDOs, generates all of the
voltages required for the device to operate from a wide variety of input sources. For maximum flexibility,
the device can operate in the modes described in the following sections.
5.4.1
VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the device is powered directly by the battery. All other voltages
required to operate the device are generated internally by the DC-DC converters. This scheme is the most
common mode for the device as it supports wide-voltage operation from 2.1 to 3.6 V (for electrical
connections, see Section 6.1.1, Typical Application – CC3100 Wide-Voltage Mode).
28
Detailed Description
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC3100
CC3100
www.ti.com
5.4.2
SWAS031D – JUNE 2013 – REVISED FEBRUARY 2015
Preregulated 1.85 V
The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at the pins 10,
25, 33, 36, 37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V
supply. This mode provides the lowest BOM count version in which inductors used for PA DC-DC and
ANA1 DC-DC (2.2 and 1 µH) and a capacitor (22 µF) can be avoided. For electrical connections, see
Section 6.1.2, Typical Application – CC3100 Preregulated 1.85-V Mode.
In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following
characteristics:
• Load current capacity ≥900 mA.
• Line and load regulation with
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