CC3230S, CC3230SF
SWRS226B – FEBRUARY 2020 – REVISED MAY 2021
CC3230S and CC3230SF SimpleLink™ Wi-Fi® 2.4GHz Wireless MCU with Coexistence
1 Features
•
•
•
•
•
•
•
•
•
Multiple-core architecture, system-on-chip (SoC)
Multilayered security features, help developers
protect identities, data, and software IP
Low-power modes for battery powered application
Coexistence with BLE radios (CC13x2/CC26x2)
Network-assisted roaming
Industrial temperature: –40°C to +85°C
Wi-Fi CERTIFIED® by the Wi-Fi Alliance®
Application microcontroller subsystem:
– Arm® Cortex®-M4 core at 80 MHz
– User-dedicated memory
• 256KB of RAM
• Optional 1MB of executable flash
– Rich set of peripherals and timers
– 27 I/O pins with flexible multiplexing options
• UART, I2S, I2C, SPI, SD, ADC,
8-bit parallel interface
• Timers and PWM
Wi-Fi network processor subsystem:
– Wi-Fi® core:
• 802.11b/g/n 2.4 GHz
• Modes:
– Access Point (AP)
– Station (STA)
– Wi-Fi Direct®
• Security:
– WEP
– WPA™/ WPA2™ PSK
– WPA2 Enterprise
– WPA3™ Personal
– WPA3™ Enterprise
– Internet and application protocols:
• HTTPs server, mDNS, DNS-SD, DHCP
• IPv4 and IPv6 TCP/IP stack
• 16 BSD sockets (fully secured TLS v1.2 and
SSL 3.0)
– Built-in power management subsystem:
• Configurable low-power profiles (always,
intermittent, tag)
• Advanced low-power modes
• Integrated DC/DC regulators
•
•
•
•
•
•
•
•
Multilayered security features:
– Separate execution environments
– Networking security
– Device identity and key
– Hardware accelerator cryptographic engines
(AES, DES, SHA/MD5, CRC)
– Application-level security (encryption,
authentication, access control)
– Initial secure programming
– Software tamper detection
– Secure boot
– Certificate signing request (CSR)
– Unique per device key pair
Application throughput:
– UDP: 16 Mbps, TCP: 13 Mbps
– Peak: 72 Mbps
Power-Management Subsystem:
– Integrated DC/DC converters support a wide
range of supply voltage:
• VBAT wide-voltage mode: 2.1 V to 3.6 V
• VIO is always tied with VBAT
– Advanced low-power modes:
• Shutdown: 1 µA, hibernate: 4.5 µA
• Low-power deep sleep (LPDS): 120 µA
• Idle connected (MCU in LPDS): 710 µA
• RX traffic (MCU active): 59 mA
• TX traffic (MCU active): 223 mA
Wi-Fi TX power:
– 18.0 dBm at 1 DSSS
– 14.5 dBm at 54OFDM
Wi-Fi RX sensitivity:
– –96 dBm at 1 DSSS
– –74.5 dBm at 54 OFDM
Clock source:
– 40.0-MHz crystal with internal oscillator
– 32.768-kHz crystal or external RTC
RGK package
– 64-pin, 9-mm × 9-mm very thin quad flat
nonleaded (VQFN) package, 0.5-mm pitch
Device supports SimpleLink™ MCU Platform
developer's ecosystem
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC3230S, CC3230SF
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SWRS226B – FEBRUARY 2020 – REVISED MAY 2021
2 Applications
•
For Internet of Things applications, such as:
– Building and home automation:
• HVAc systems & thermostat
• Video surveillance, video doorbells, and lowpower camera
• Building security systems & e-locks
• Smoke detector
• Water leak detector
– Appliances
• Smart home remote control
– Asset tracking
– Factory automation
– Medical and healthcare
• CPAP
– Grid infrastructure
3 Description
The SimpleLink™ Wi-Fi® CC3230x wireless MCU comes in two variants: CC3230S and C3230SF.
• The CC3230S includes 256KB of RAM, IoT networking security, device identity/keys, as well as, MCU level
security features such as file system encryption, user IP (MCU image) encryption, secure boot and debug
security.
• The CC3230SF builds on the CC3230S and integrates a user-dedicated 1MB of executable flash in addition
to the 256KB of RAM.
Simplify your IoT design with a Wi-Fi CERTIFIED™ wireless microcontroller (MCU). The SimpleLink™ Wi-Fi®
CC3230x device family is a system-on-chip (SoC) solution that integrates two processors within a single chip,
including:
• Application processor: Arm® Cortex®-M4 MCU with a user-dedicated 256KB of RAM and an optional 1MB of
executable flash
• Network processor to run all Wi-Fi and internet logical layers. This ROM-based subsystem completely
offloads the host MCU and includes an 802.11b/g/n 2.4 GHz radio, baseband, and MAC with a powerful
hardware cryptography engine
These devices introduce new capabilities that further simplify the connectivity of things to the internet. The main
new features include
• Bluetooth® Low Energy and Wi-Fi 2.4-GHz radio coexistence (CC13x2/CC26x2)
• Antenna selection
• Up to 16 concurrent secure sockets
• Certificate sign request (CSR)
• Online certificate status protocol (OCSP)
• Wi-Fi Alliance® certified IoT power-saving features (such as BSS max idle, DMS, and proxy ARP)
• Hostless mode for offloading template packet transmissions
• Network-assisted roaming
The CC3230x device family is part of the SimpleLink™ MCU platform—a common, easy-to-use development
environment based on a single-core software development kit (SDK) with a rich tool set and reference
designs. The E2E™ community supports Wi-Fi, Bluetooth® low energy, Sub-1 GHz, and host MCUs. For more
information, visit www.ti.com/simplelink or www.ti.com/simplelinkwifi.
Device Information(1)
PACKAGE
BODY SIZE (NOM)
CC3230SM2RGKR
PART NUMBER
VQFN (64)
9.00 mm × 9.00 mm
CC3230SF12RGKR
VQFN (64)
9.00 mm × 9.00 mm
(1)
2
For all available packages, see Section 12.
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4 Functional Block Diagrams
CC3230x Functional Block Diagram shows the functional block diagram of the CC3230x SimpleLink Wi-Fi
solution.
SPI
Flash
VCC Wide voltage
(2.1 to 3.6V)
SPI
Peripheral
I2C
Peripheral
GSPI
I2C
SSPI
32.768-kHz
Crystal
BLE / 2.4 Wi-Fi
Antenna
RF_BG
CC3230x
BLE
Device
40-MHz
Crystal
Wi-Fi /
BLE RF
Switch
2.4-GHz
BPF
SPDT
RF
Switch
COEX_IO
GPIO/
PWM
Parallel
Port
I2S
ANT_SEL_IO
BLE / 2.4 Wi-Fi
Antenna
Miscellaneous
Peripherals
Camera
sensor
Audio
codec
When using the antenna selection feature (dual antenna), an SPDT switch and 2 GPIO lines are required.
Figure 4-1. CC3230x Functional Block Diagram
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CC3230x Functional Block Diagram shows the hardware overview for the CC3230x device.
Figure 4-2. CC320x Hardware Overview
4
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Figure 4-3 shows an overview of the embedded software in the CC3230x device.
Customer Application
NetApp
BSD Socket
Wi-Fi®
6LPSOH/LQNΠ0&8 'ULYHU $3,V
Host Interface
Network Apps
WLAN Security
and Management
TCP/IP Stack
WLAN MAC and PHY
Figure 4-3. CC3230x Embedded Software Overview
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 6
6 Device Comparison......................................................... 7
6.1 Related Products........................................................ 8
7 Terminal Configuration and Functions..........................9
7.1 Pin Diagram................................................................ 9
7.2 Pin Attributes.............................................................10
7.3 Signal Descriptions................................................... 19
7.4 Pin Multiplexing.........................................................27
7.5 Drive Strength and Reset States for Analog and
Digital Multiplexed Pins............................................... 29
7.6 Pad State After Application of Power to Device,
Before Reset Release................................................. 29
7.7 Connections for Unused Pins................................... 30
8 Specifications................................................................ 31
8.1 Absolute Maximum Ratings...................................... 31
8.2 ESD Ratings............................................................. 31
8.3 Power-On Hours (POH)............................................ 31
8.4 Recommended Operating Conditions.......................32
8.5 Current Consumption Summary (CC3230S)............ 32
8.6 Current Consumption Summary (CC3230SF).......... 33
8.7 TX Power Control......................................................34
8.8 Brownout and Blackout Conditions........................... 37
8.9 Electrical Characteristics for GPIO Pins................... 38
8.10 Electrical Characteristics for Pin Internal Pullup
and Pulldown...............................................................39
8.11 WLAN Receiver Characteristics..............................40
8.12 WLAN Transmitter Characteristics..........................40
8.13 WLAN Transmitter Out-of-Band Emissions.............41
8.14 BLE/2.4 GHz Radio Coexistence and WLAN
Coexistence Requirements......................................... 41
8.15 Thermal Resistance Characteristics for RGK
Package...................................................................... 42
8.16 Timing and Switching Characteristics..................... 42
9 Detailed Description......................................................61
9.1 Overview................................................................... 61
9.2 Arm® Cortex®-M4 Processor Core Subsystem.........61
9.3 Wi-Fi® Network Processor Subsystem..................... 62
9.4 Security..................................................................... 64
9.5 Power-Management Subsystem...............................66
9.6 Low-Power Operating Mode..................................... 67
9.7 Memory..................................................................... 68
9.8 Restoring Factory Default Configuration...................71
9.9 Boot Modes...............................................................72
9.10 Hostless Mode........................................................ 73
10 Applications, Implementation, and Layout............... 74
10.1 Application Information........................................... 74
10.2 PCB Layout Guidelines...........................................82
11 Device and Documentation Support..........................86
11.1 Third-Party Products Disclaimer............................. 86
11.2 Tools and Software..................................................86
11.3 Firmware Updates...................................................88
11.4 Device Nomenclature..............................................89
11.5 Documentation Support.......................................... 90
11.6 Support Resources................................................. 91
11.7 Trademarks............................................................. 92
11.8 Electrostatic Discharge Caution.............................. 92
11.9 Glossary.................................................................. 92
12 Mechanical, Packaging, and Orderable
Information.................................................................... 93
12.1 Package Option Addendum.................................... 93
5 Revision History
Changes from September 28, 2020 to May 13, 2021 (from Revision A (September 2020) to
Revision B (May 2021))
Page
• Added "WPA3 Enterprise" to Section 1 ..............................................................................................................1
• Added "WPA3 personal and enterprise" to Table 6-1 ........................................................................................ 7
• Changed footnote in Section 9.3 ..................................................................................................................... 62
• Added "WPA3 personal and enterprise" to Section 9.3 ................................................................................... 62
• Added "WPA3 Enterprise" to "WLAN features".................................................................................................62
• Changed table note for Table 9-1 .................................................................................................................... 63
• Added "WPA3 personal and enterprise" to Table 9-1 ...................................................................................... 63
• Added standard sections to Section 11 ........................................................................................................... 86
6
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6 Device Comparison
Table 6-1 lists the features supported across different CC3x3x devices.
Table 6-1. Comparison of Device Features
DEVICE
FEATURE
CC3130
CC3135
CC3230S
CC3230SF
CC3235S
CC3235SF
Classification
Network Processor
Network Processor
Wireless microcontroller
Wireless microcontroller
Wireless
microcontroller
Wireless
microcontroller
Standard
802.11b/g/n
802.11a/b/g/n
802.11b/g/n
802.11b/g/n
802.11a/b/g/n
802.11a/b/g/n
TCP/IP stack
IPv4, IPv6
IPv4, IPv6
IPv4, IPv6
IPv4, IPv6
IPv4, IPv6
IPv4, IPv6
Sockets
16
16
16
16
16
16
9-mm × 9-mm VQFN
9-mm × 9-mm
VQFN
9-mm × 9-mm
VQFN
Package
9-mm × 9-mm VQFN
9-mm × 9-mm VQFN
9-mm × 9-mm VQFN
Flash
—
—
—
1MB
—
1MB
RAM
—
—
256KB
256KB
256KB
256KB
ON-CHIP APPLICATION MEMORY
RF FEATURES
Frequency
2.4 GHz
2.4 GHz, 5 GHz
2.4 GHz
2.4 GHz
2.4 GHz, 5 GHz
2.4 GHz, 5 GHz
Coexistence with
Yes
BLE Radio
Yes
Yes
Yes
Yes
Yes
Secure boot
—
—
Yes
Yes
Yes
Yes
FIPS 140-2
Level 1
Certification(1)
No
Yes
No
No
Yes
Yes
File system
File system
security
security
Secure key
Secure key
storage
storage
SECURITY FEATURES
Enhanced
application level
security
File system security
File system security
File system security
File system security
Secure key storage
Secure key storage
Secure key storage
Secure key storage
Software tamper
Software tamper
Software tamper
Software tamper
detection
detection
detection
detection
Cloning protection
Cloning protection
Cloning protection
Cloning protection
Initial secure
Initial secure
Initial secure
Initial secure
programming
programming
programming
programming
Wi-Fi level of
security
detection
detection
Cloning
Cloning
protection
protection
Initial secure
Initial secure
programming
programming
WEP, WPS, WPA / WPA2 PSK, WPA2 (802.1x), WPA3 personal and enterprise
Additional
networking
security
Unique device identity
Trusted root-certificate catalog
TI Root-of-trust public key
Online certificate status protocol (OCSP)
Certificate signing request (CSR)
Unique per-device key pair
Hardware
acceleration
Hardware crypto engines
(1)
Software tamper Software tamper
For exact status of FIPS certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.
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6.1 Related Products
For information about other devices in this family of products or related products, see the links that follow.
The SimpleLink™ MCU This portfolio offers a single development environment that delivers flexible hardware,
Portfolio
software, and tool options for customers developing wired and wireless applications.
With 100 percent code reuse across host MCUs, Wi-Fi®, Bluetooth® low energy,
Sub-1 GHz devices and more, choose the MCU or connectivity standard that fits your
design. A one-time investment with the SimpleLink™ software development kit (SDK)
allows you to reuse often, opening the door to create unlimited applications.
8
SimpleLink™ Wi-Fi®
Family
This device platform offers several Internet-on-a chip™ solutions, which address
the need of battery-operated, security-enabled products. Texas Instruments offers a
single-chip wireless microcontroller and a wireless network processor that can be
paired with any MCU, allowing developers to design new Wi-Fi® products or upgrade
existing products with Wi-Fi® capabilities.
BoosterPack™ Plug-in
Module
Extend the functionality of the TI LaunchPad™ Development Kit with the
BoosterPack™ Plug-in Module. The application-specific BoosterPack Plug-in Module
allows you to explore a broad range of applications, including capacitive touch,
wireless sensing, LED Lighting control, and more. Stack multiple BoosterPack Plugin Modules onto a single LaunchPad Development Kit to further enhance the
functionality of your design.
Reference Designs
Find reference designs leveraging the best in TI technology – from analog and power
management to embedded processors.
The SimpleLink™ WiFi® SDK
The SDK contains drivers for the CC3230 programmable MCU, sample applications,
and documentation required to start development with CC3230x solutions.
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7 Terminal Configuration and Functions
7.1 Pin Diagram
37
VDD_PA_IN
38
SOP1
39
LDO_IN1
40
SOP0
41
VIN_DCDC_ANA
42
VIN_DCDC_PA
43
DCDC_ANA_SW
44
DCDC_PA_SW_P
45
DCDC_PA_OUT
DCDC_DIG_SW
46
DCDC_PA_SW_N
VIN_DCDC_DIG
47
DCDC_ANA2_SW_N
VDD_ANA2
48
DCDC_ANA2_SW_P
VDD_ANA1
Top View Pin Assignment for 64-Pin VQFN shows pin assignments for the 64-pin VQFN package.
36
35
34
33
VDD_RAM
49
32
nRESET
GPIO0
50
31
RF_BG
ANTSEL2
RTC_XTAL_P
51
30
RTC_XTAL_N
52
29
ANTSEL1
GPIO30
53
28
NC
VIN_IO2
54
27
NC
GPIO1
55
26
NC
VDD_DIG2
56
25
LDO_IN2
GPIO2
57
24
VDD_PLL
GPIO3
58
23
WLAN_XTAL_P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GPIO22
TDI
TDO
FLASH_SPI_CS
GPIO28
17
FLASH_SPI_DIN
18
64
FLASH_SPI_DOUT
63
GPIO9
VIN_IO1
GPIO8
FLASH_SPI_CLK
TCK
VDD_DIG1
TMS
19
GPIO17
20
62
GPIO16
61
GPIO7
GPIO15
GPIO6
GPIO14
SOP2
GPIO12
WLAN_XTAL_N
21
GPIO13
22
60
GPIO10
59
GPIO11
GPIO4
GPIO5
NC = No internal connection
Figure 7-1. Top View Pin Assignment for 64-Pin VQFN
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7.2 Pin Attributes
The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in
the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of
hardware configuration (at device reset) and register control.
Note
TI highly recommends using SysConfig to obtain the desired pinout. In addition refer to the user guide
within the SimpleLink™ CC32XX Software Development Kit (SDK)
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does
not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used.
Section 7.2.1 and Table 7-1 list the pin descriptions and attributes. Table 7-2 lists the signal descriptions. Table
7-3 presents an overall view of pin multiplexing. All pin multiplexing options are configurable using the pin mux
registers.
The following special considerations apply:
•
•
•
•
•
All I/Os support drive strengths of 2, 4, and 6 mA. The drive strength is individually configurable for each pin.
All I/Os support 10-µA pullup and pulldown resistors.
The VIO and VBAT supplies must be tied together at all times.
By default, all I/Os float in the Hibernate state. However, the default state can be changed by software.
All digital I/Os are nonfail-safe.
Note
If an external device drives a positive voltage to the signal pads and the CC3230x device is not
powered, DC is drawn from the other device. If the drive strength of the external device is adequate,
an unintentional wakeup and boot of the CC3230x device can occur. To prevent current draw, TI
recommends any one of the following conditions:
• All devices interfaced to the CC3230x device must be powered from the same power rail as the
chip.
• Use level shifters between the device and any external devices fed from other independent rails.
• The nRESET pin of the CC3230x device must be held low until the VBAT supply to the device is
driven and stable.
• All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the
TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.
The ADC inputs are tolerant up to 1.8 V (see Section 8.16.6.6.1 for more details about the usable
range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to
prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the
digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter
disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For
more information, see Section 7.5.
10
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7.2.1 Pin Descriptions
PINS
NO.
NAME
TYPE
DESCRIPTION
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
1
GPIO10
I/O
General-purpose input or output
No
No
No
2
GPIO11
I/O
General-purpose input or output
Yes
No
No
3
GPIO12
I/O
General-purpose input or output
No
No
No
4
GPIO13
I/O
General-purpose input or output
Yes
No
No
5
GPIO14
I/O
General-purpose input or output
No
No
No
6
GPIO15
I/O
General-purpose input or output
No
No
No
7
GPIO16
I/O
General-purpose input or output
No
No
No
8
GPIO17
I/O
General-purpose input or output
Yes
No
No
9
VDD_DIG1
Power
Internal digital core voltage
N/A
N/A
N/A
10
VIN_IO1
Power
I/O power supply (same as
battery voltage)
N/A
N/A
N/A
11
FLASH_SPI_CLK
O
Serial flash interface: SPI clock
N/A
N/A
N/A
N/A
N/A
N/A
12
FLASH_SPI_DOUT
O
Serial flash interface: SPI data
out
13
FLASH_SPI_DIN
I
Serial flash interface: SPI data in
N/A
N/A
N/A
N/A
N/A
N/A
14
FLASH_SPI_CS
O
Serial flash interface: SPI chip
select
15
GPIO22
I/O
General-purpose input or output
No
No
No
16
TDI
I/O
JTAG interface: data input
No
No
Muxed with
JTAG TDI
17
TDO
I/O
JTAG interface: data output
Yes
No
Muxed with
JTAG TDO
18
GPIO28
I/O
General-purpose input or output
No
No
No
19
TCK
I/O
JTAG / SWD interface: clock
No
No
Muxed with
JTAG/
SWD-TCK
20
TMS
I/O
JTAG / SWD interface: mode
select or SWDIO
No
No
Muxed with
JTAG/
SWD-TMSC
21(2)
SOP2
O
Configuration sense-on-power
No
No
No
22
WLAN_XTAL_N
Analog
40-MHz XTAL
N/A
N/A
N/A
23
WLAN_XTAL_P
Analog
40-MHz XTAL or TCXO clock
input
N/A
N/A
N/A
24
VDD_PLL
Power
Internal analog voltage
N/A
N/A
N/A
Power
Analog RF supply from analog
DCDC output
N/A
N/A
N/A
25
LDO_IN2
26
NC
—
No Connect
N/A
N/A
N/A
27
NC
—
No Connect
N/A
N/A
N/A
28
NC
—
No Connect
N/A
N/A
N/A
29(1)
ANTSEL1
O
Antenna selection control
No
No
No
30(1)
ANTSEL2
O
Antenna selection control
No
No
No
31
RF_BG
RF
RF BG band: 2.4 GHz TX, RX
N/A
N/A
N/A
32
nRESET
I
Master chip reset input. Active
low input.
N/A
N/A
N/A
33
VDD_PA_IN
Power
RF power amplifier (PA) input
from PA DC-DC output
N/A
N/A
N/A
34
SOP1
Configuration sense-on-power 1
N/A
N/A
N/A
I
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PINS
NO.
NAME
TYPE
I
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
Configuration sense-on-power 0
N/A
N/A
N/A
DESCRIPTION
35
SOP0
36
LDO_IN1
Power
Analog RF supply from analog
DCDC output
N/A
N/A
N/A
37
VIN_DCDC_ANA
Power
Analog DC-DC supply input
(same as battery voltage)
N/A
N/A
N/A
38
DCDC_ANA_SW
Power
Analog DC/DC converter
switching node
N/A
N/A
N/A
39
VIN_DCDC_PA
Power
PA DC/DC converter input supply
(same as battery voltage)
N/A
N/A
N/A
40
DCDC_PA_SW_P
Power
PA DC/DC converter +ve
switching node
N/A
N/A
N/A
41
DCDC_PA_SW_N
Power
PA DC/DC converter –ve
switching node
N/A
N/A
N/A
42
DCDC_PA_OUT
Power
PA DC/DC converter output.
N/A
N/A
N/A
N/A
N/A
N/A
43
DCDC_DIG_SW
Power
Digital DC/DC converter switching
node
44
VIN_DCDC_DIG
Power
Digital DC/DC converter supply
input (same as battery voltage)
N/A
N/A
N/A
45(4)
DCDC_ANA2_SW_P
I/O
Analog2 DCDC converter +ve
switching node
No
User configuration
not required (3)
No
46
DCDC_ANA2_SW_N
Power
Analog2 DC-DC converter -ve
switching node
N/A
N/A
N/A
47
VDD_ANA2
Power
Analog2 DC-DC output
N/A
N/A
N/A
N/A
N/A
N/A
48
VDD_ANA1
Power
Analog1 power supply fed by
ANA2 DC-DC output
49
VDD_RAM
Analog
SRAM LDO output
N/A
N/A
N/A
50
GPIO0
I/O
General-purpose input or output
No
User configuration
not required (3)
No
51
RTC_XTAL_P
Analog
32.768-kHz XTAL_P or external
CMOS level clock input
N/A
N/A
N/A
52(5)
RTC_XTAL_N
Analog
32.768-kHz XTAL_N
N/A
User configuration
not required (3) (7)
No
53
GPIO30
I/O
General-purpose input or output
No
User configuration
not required (3)
No
54
VIN_IO2
Analog
Chip supply voltage (VBAT)
N/A
N/A
N/A
55
GPIO1
56
VDD_DIG2
57(6)
GPIO2
I/O
58(6)
GPIO3
59(6)
General-purpose input or output
No
No
No
Internal digital core voltage
N/A
N/A
N/A
Analog input (1.5V max) or
general-purpose input or output
Wake-up source
See (8)
No
I/O
Analog input (1.5V max) or
general-purpose input or output
No
See (8)
No
GPIO4
I/O
Analog input (1.5V max) or
general-purpose input or output
Wake-up source
See (8)
No
60(6)
GPIO5
I/O
Analog input (1.5V max) or
general-purpose input or output
No
See (8)
No
61
GPIO6
I/O
General-purpose input or output
No
No
No
62
GPIO7
I/O
General-purpose input or output
No
No
No
63
GPIO8
I/O
General-purpose input or output
No
No
No
64
GPIO9
I/O
General-purpose input or output
No
No
No
12
I/O
Analog
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PINS
NO.
NAME
GND_TAB
(1)
TYPE
—
DESCRIPTION
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
N/A
N/A
N/A
Thermal pad and electrical
ground
This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3230x device
between two antennas. These pins must not be used for other functionalities.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
Device firmware automatically enables the digital path during ROM boot.
Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the
CC3230SF device. For the CC3230S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level
configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some
applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,
the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to
automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent
false detection, TI recommends using pin 52 for output-only functions.
This pin is shared by the ADC inputs and digital I/O pad cells.
To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.
Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always
connected and must be made Hi-Z before enabling the ADC switch.
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Table 7-1. Pin Attributes
PIN
NO.
1
2
3
SIGNAL
DIRECTION
LPDS(3)
GPIO10 (PN)
0
I/O
Hi-Z, Pull, Drive
I2C_SCL
1
I/O (open drain)
Hi-Z, Pull, Drive
GT_PWM06
3
O
Hi-Z, Pull, Drive
7
O
1
SDCARD_CLK
6
O
0
GT_CCP01
12
I
Hi-Z, Pull, Drive
GPIO11 (PN)
0
I/O
Hi-Z, Pull, Drive
I2C_SDA
1
I/O (open drain)
Hi-Z, Pull, Drive
GT_PWM07
3
O
Hi-Z, Pull, Drive
UART1_TX
pXCLK(XVCLK)
SIGNAL
TYPE(2)
PAD STATES
PIN MUX
ENCODING
SIGNAL NAME(1)
I/O
4
O
0
6
I/O (open drain)
Hi-Z, Pull, Drive
UART1_RX
7
I
Hi-Z, Pull, Drive
GT_CCP02
12
I
Hi-Z, Pull, Drive
MCAFSX
13
O
Hi-Z, Pull, Drive
GPIO12 (PN)
0
I/O
Hi-Z, Pull, Drive
McACLK
3
O
Hi-Z, Pull, Drive
pVS(VSYNC)
4
I
Hi-Z, Pull, Drive
5
I/O (open drain)
Hi-Z, Pull, Drive
UART0_TX
7
O
1
GT_CCP03
12
I
Hi-Z, Pull, Drive
SDCARD_CMD
I2C_SCL
I/O
I/O
Hib(4)
nRESET = 0
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
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Table 7-1. Pin Attributes (continued)
PIN
NO.
4
SIGNAL NAME(1)
SIGNAL
TYPE(2)
0
I/O
I2C_SDA
5
I/O (open drain)
4
I
UART0_RX
7
I
GT_CCP04
12
I
GPIO14 (PN)
0
I/O
5
I/O (open drain)
7
I/O
pDATA8(CAM_D4)
4
I
GT_CCP05
12
I
pHS(HSYNC)
I/O
6
7
8
GSPI_CLK
I/O
GPIO15 (PN)
0
I/O
I2C_SDA
5
I/O (open drain)
7
I/O
4
I
GSPI_MISO
pDATA9(CAM_D5)
I/O
LPDS(3)
Hib(4)
nRESET = 0
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
GT_CCP06
13
I
SDCARD_ DATA0
8
I/O
GPIO16 (PN)
0
I/O
Hi-Z, Pull, Drive
GSPI_MOSI
7
I/O
Hi-Z, Pull, Drive
4
I
Hi-Z, Pull, Drive
5
O
1
pDATA10(CAM_D6)
UART1_TX
I/O
GT_CCP07
13
I
Hi-Z, Pull, Drive
SDCARD_CLK
8
O
0
GPIO17 (PN)
0
I/O
UART1_RX
5
I
7
I/O
4
I
GSPI_CS
I/O
pDATA11 (CAM_D7)
SDCARD_ CMD
8
I/O
9
VDD_DIG1 (PN)
—
N/A
N/A
N/A
N/A
N/A
10
VIN_IO1
—
N/A
N/A
N/A
N/A
N/A
11
FLASH_SPI_CLK
O
N/A
O
Hi-Z, Pull,
Drive(5)
Hi-Z, Pull,
Drive
Hi-Z
12
FLASH_SPI_DOUT
O
N/A
O
Hi-Z, Pull,
Drive(5)
Hi-Z, Pull,
Drive
Hi-Z
13
FLASH_SPI_DIN
I
N/A
I
Hi-Z, Pull,
Drive(5)
Hi-Z
Hi-Z
14
FLASH_SPI_CS
O
N/A
O
1
Hi-Z, Pull,
Drive
Hi-Z
0
I/O
I/O
7
O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
GT_CCP04
5
I
TDI (PN)
1
I
GPIO23
0
I/O
2
O
1
Hi-Z, Pull,
Drive
Hi-Z
9
I/O (open drain)
Hi-Z, Pull, Drive
GPIO22 (PN)
15
16
McAFSX
UART1_TX
I2C_SCL
14
PAD STATES
SIGNAL
DIRECTION
GPIO13 (PN)
I2C_SCL
5
PIN MUX
ENCODING
I/O
Hi-Z, Pull, Drive
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Table 7-1. Pin Attributes (continued)
PIN
NO.
SIGNAL NAME(1)
SIGNAL
TYPE(2)
18
19
20
LPDS(3)
Hib(4)
nRESET = 0
Hi-Z, Pull, Drive
Driven high
in SWD;
driven low in
4-wire JTAG
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Driven low
Hi-Z
1
O
GPIO24
0
I/O
5
O
2
I
I2C_SDA
9
I/O (open drain)
GT_CCP06
4
I
McAFSX
6
O
0
I/O
1
I
8
O
1
I/O
0
I/O
0
O
Hi-Z, Pull, Drive
9
O
Hi-Z, Pull, Drive
2
O
Hi-Z, Pull, Drive
TCXO_EN
N/A
O
0
SOP2 (PN)
See (9)
I
Hi-Z, Pull, Drive
UART1_RX
GPIO28 (PN)
TCK (PN)
GT_PWM03
TMS (PN)
GPIO29
I/O
I/O
I/O
I/O
GPIO25
GT_PWM02
21(6)
PAD STATES
SIGNAL
DIRECTION
TDO (PN)
PWM0
17
PIN MUX
ENCODING
McAFSX
O
22
WLAN_XTAL_N
—
N/A
N/A
N/A
N/A
N/A
23
WLAN_XTAL_P
—
N/A
N/A
N/A
N/A
N/A
24
VDD_PLL
—
N/A
N/A
N/A
N/A
N/A
25
LDO_IN2
—
N/A
N/A
N/A
N/A
N/A
26
NC
—
N/A
N/A
N/A
N/A
N/A
27
NC
—
N/A
N/A
N/A
N/A
N/A
28
NC
—
N/A
N/A
N/A
N/A
N/A
29(12)
ANTSEL1
O
0
O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
30(12)
ANTSEL2
O
0
O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
31
RF_BG
—
N/A
N/A
N/A
N/A
N/A
32
nRESET
—
N/A
N/A
N/A
N/A
N/A
33
VDD_PA_IN
—
N/A
N/A
N/A
N/A
N/A
34
SOP1
—
N/A
N/A
N/A
N/A
N/A
35
SOP0
—
N/A
N/A
N/A
N/A
N/A
36
LDO_IN1
—
N/A
N/A
N/A
N/A
N/A
37
VIN_DCDC_ANA
—
N/A
N/A
N/A
N/A
N/A
38
DCDC_ANA_SW
—
N/A
N/A
N/A
N/A
N/A
39
VIN_DCDC_PA
—
N/A
N/A
N/A
N/A
N/A
40
DCDC_PA_SW_P
—
N/A
N/A
N/A
N/A
N/A
41
DCDC_PA_SW_N
—
N/A
N/A
N/A
N/A
N/A
42
DCDC_PA_OUT
—
N/A
N/A
N/A
N/A
N/A
43
DCDC_DIG_SW
—
N/A
N/A
N/A
N/A
N/A
44
VIN_DCDC_DIG
—
N/A
N/A
N/A
N/A
N/A
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Table 7-1. Pin Attributes (continued)
PIN
NO.
PIN MUX
ENCODING
SIGNAL
DIRECTION
GPIO31
0
I/O
UART0_RX
9
I
12
O
2
I
McAXR0
6
I/O
GSPI_CLK
7
I/O
SIGNAL NAME(1)
McAFSX
45(7)
UART1_RX
SIGNAL
TYPE(2)
I/O
Hib(4)
nRESET = 0
Hi-Z
Hi-Z
Hi-Z
DCDC_ANA2_SW_P
(PN)
—
See (8)
N/A
N/A
N/A
N/A
46
DCDC_ANA2_SW_N
—
N/A
N/A
N/A
N/A
N/A
47
VDD_ANA2
—
N/A
N/A
N/A
N/A
N/A
48
VDD_ANA1
—
N/A
N/A
N/A
N/A
N/A
49
VDD_RAM
—
N/A
N/A
N/A
N/A
N/A
GPIO0 (PN)
0
I/O
Hi-Z, Pull, Drive
UART0_CTS
12
I
Hi-Z, Pull, Drive
McAXR1
6
I/O
Hi-Z, Pull, Drive
GT_CCP00
7
I
Hi-Z, Pull, Drive
9
I/O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
UART1_RTS
10
O
1
UART0_RTS
3
O
1
McAXR0
4
I/O
Hi-Z, Pull, Drive
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
O
2
O
4
O
Hi-Z, Pull,
Drive
Hi-Z
UART0_RTS
6
O
1
GSPI_MOSI
8
O
Hi-Z, Pull, Drive
GPIO30 (PN)
0
I/O
Hi-Z, Pull, Drive
UART0_TX
9
O
1
2
O
3
O
Hi-Z, Pull,
Drive
Hi-Z
N/A
N/A
Hi-Z, Pull,
Drive
Hi-Z
50
GSPI_CS
51
RTC_XTAL_P
I/O
—
RTC_XTAL_N (PN)
GPIO32
52(10)
McACLK
McAXR0
McACLK
53
McAFSX
54
O
I/O
4
I
7
I/O
N/A
N/A
N/A
0
I/O
Hi-Z, Pull, Drive
3
O
1
4
I
Hi-Z, Pull, Drive
UART1_TX
6
O
1
GT_CCP01
7
I
Hi-Z, Pull, Drive
N/A
N/A
N/A
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
—
UART0_TX
pCLK (PIXCLK)
56
VDD_DIG2
I/O
—
ADC_CH0
GPIO2 (PN)
57(11)
Hi-Z, Pull, Drive
GSPI_MISO
VIN_IO2
55
Hi-Z, Pull, Drive
GT_CCP05
GPIO1 (PN)
UART0_RX
UART1_RX
GT_CCP02
16
PAD STATES
LPDS(3)
Analog input
(up to 1.5 V)
or digital I/O
N/A
N/A
See (8)
I
0
I/O
3
I
6
I
7
I
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Table 7-1. Pin Attributes (continued)
PIN
NO.
SIGNAL NAME(1)
SIGNAL
TYPE(2)
PIN MUX
ENCODING
ADC_CH1
58(11)
GPIO3 (PN)
UART1_TX
See
Analog input
(up to 1.5 V)
or digital I/O
pDATA7 (CAM_D3)
59(11)
UART1_RX
pDATA6 (CAM_D2)
GPIO5 (PN)
60(11)
pDATA5 (CAM_D1)
McAXR1
61
62
63
(4)
(5)
(6)
(7)
(8)
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
N/A
N/A
N/A
I
Hi-Z, Pull, Drive
(8)
I
0
I/O
6
I
I
(8)
I
0
I/O
4
I
6
I/O
7
I
GPIO6 (PN)
0
I/O
Hi-Z, Pull, Drive
UART0_RTS
5
O
1
pDATA4 (CAM_D0)
4
I
3
I
UART0_CTS
6
I
GT_CCP06
7
I
GPIO7 (PN)
0
I/O
McACLKX
13
O
3
O
UART0_RTS
10
O
UART0_TX
11
O
GPIO8 (PN)
0
I/O
SDCARD_IRQ
6
I
7
O
UART1_CTS
UART1_RTS
McAFSX
I/O
I/O
I/O
GT_CCP06
12
I
GPIO9 (PN)
0
I/O
3
O
6
I/O
McAXR0
7
I/O
GT_CCP00
12
I
N/A
N/A
SDCARD_DATA0
GND_TAB
(1)
(2)
(3)
Hi-Z
1
GT_CCP05
GT_PWM05
64
Hi-Z, Pull,
Drive
Hi-Z, Pull, Drive
O
See
Analog input
(up to 1.5 V)
or digital I/O
nRESET = 0
6
4
ADC_CH3
Hib(4)
I/O
See
Analog input
(up to 1.5 V)
or digital I/O
I
LPDS(3)
0
4
ADC_CH2
GPIO4 (PN)
(8)
PAD STATES
SIGNAL
DIRECTION
I/O
—
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
1
Signals names with (PN) denote the default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak
pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
Pin 45 is used by an internal DC/DC (ANA2_DCDC). For the CC3230S device, pin 45 can be used as GPIO_31 if a supply is provided
on pin 47.
For details on proper use, see Section 7.5.
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(9)
This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode.
For this reason, the pin must be output only when used for digital functions.
(10) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level
configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some
applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,
the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to
automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent
false detection, TI recommends using pin 52 for output-only functions.
(11) This pin is shared by the ADC inputs and digital I/O pad cells.
(12) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3230x device
between two antennas. These pins must not be used for other functionalities.
18
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7.3 Signal Descriptions
Table 7-2. Signal Descriptions
FUNCTION
ADC
Antenna
selection
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
ADC_CH0
57
I/O
I
ADC channel 0 input (maximum of 1.5 V)
ADC_CH1
58
I/O
I
ADC channel 1 input (maximum of 1.5 V)
ADC_CH2
59
I/O
I
ADC channel 2 input (maximum of 1.5 V)
ADC_CH3
60
I
I
ADC channel 3 input (maximum of 1.5 V)
GPIO10
1
I/O
O
GPIO11
2
I/O
O
GPIO12
3
I/O
O
GPIO13
4
I/O
O
GPIO14
5
I/O
O
GPIO15
6
I/O
O
GPIO16
7
I/O
O
GPIO17
8
I/O
O
GPIO22
15
I/O
O
GPIO28
18(2)
I/O
O
GPIO25
21
O
O
ANTSEL1
29
O
O
SIGNAL NAME
ANTSEL2
30
O
O
45(2) (1)
I/O
O
GPIO0
50
I/O
O
GPIO32
52(2)
I/O
O
GPIO30
53(2)
I/O
O
GPIO3
58
I/O
O
GPIO4
59
I/O
O
GPIO5
60
I/O
O
GPIO6
61
I/O
O
GPIO8
63
I/O
O
GPIO9
64
I/O
O
GPIO31
DESCRIPTION
Antenna selection control
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Table 7-2. Signal Descriptions (continued)
FUNCTION
BLE/2.4 GHz
radio
coexistence
Clock
20
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
GPIO10
1
I/O
I/O
GPIO11
2
I/O
O
GPIO12
3
I/O
I/O
GPIO13
4
I/O
I/O
GPIO14
5
I/O
I/O
GPIO15
6
I/O
I/O
GPIO16
7
I/O
I/O
GPIO17
8
I/O
O
GPIO22
15
I/O
I/O
GPIO28
18(2)
I/O
I/O
SIGNAL NAME
DESCRIPTION
GPIO25
21
O
O
GPIO31
45(2) (1)
I/O
I/O
GPIO0
50
I/O
I/O
GPIO32
52(2)
I/O
I/O
GPIO30
53(2)
I/O
I/O
GPIO3
58
I/O
O
GPIO4
59
I/O
O
GPIO5
60
I/O
I/O
GPIO6
61
I/O
I/O
GPIO8
63
I/O
I/O
GPIO9
64
I/O
I/O
WLAN_XTAL_N
22
—
—
40-MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P
23
—
—
40-MHz crystal or TCXO clock input
RTC_XTAL_P
51
—
—
Connect 32.768-kHz crystal or force external CMOS
level clock
RTC_XTAL_N
52
—
—
Connect 32.768-kHz crystal or connect 100-kΩ resistor
to supply voltage
Coexistence inputs and outputs
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Table 7-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
HM_IO
Hostless mode
JTAG / SWD
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
1
I/O
I/O
2
I/O
O
3
I/O
I/O
4
I/O
I/O
5
I/O
I/O
6
I/O
I/O
7
I/O
I/O
8
I/O
O
15
I/O
I/O
18(2)
I/O
I/O
21
O
O
45(2) (1)
I/O
I/O
50
I/O
I/O
52(2)
I/O
I/O
53(2)
I/O
I/O
58
O
O
59
O
O
60
I/O
I/O
61
I/O
I/O
63
I/O
I/O
I/O
DESCRIPTION
Hostless mode inputs and outputs
64
I/O
TDI
16
I/O
I
JTAG TDI. Reset default pinout.
TDO
17
I/O
O
JTAG TDO. Reset default pinout.
TCK
19
I/O
I
JTAG/SWD TCK. Reset default pinout.
TMS
20
I/O
I/O
JTAG/SWD TMS. Reset default pinout.
I/O
I/O (open drain)
I2C clock data
I/O
I/O (open drain)
I2C data
1
I2C_SCL
3
5
16
I2C
2
I2C_SDA
4
6
17
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Table 7-2. Signal Descriptions (continued)
FUNCTION
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
GT_PWM06
1
I/O
O
Pulse-width modulated O/P
GT_CCP01
1
I/O
I
Timer capture port
GT_PWM07
2
I/O
O
Pulse-width modulated O/P
GT_CCP02
2
I/O
I
GT_CCP03
3
I/O
I
4
I/O
I
15
I/O
I
5
I/O
I
6
I/O
I
17
I/O
I
61
I/O
I
63
I/O
I
GT_CCP07
7
I/O
I
PWM0
17
I/O
O
GT_PWM03
19
I/O
O
GT_PWM02
21
O
O
SIGNAL NAME
GT_CCP04
GT_CCP05
GT_CCP06
Timers
Timer capture ports
Pulse-width modulated outputs
50
I/O
I
64
I/O
I
GT_CCP05
53
I/O
I
GT_CCP01
55
I/O
I
GT_CCP02
57
I/O
I
GT_CCP05
60
I
I
Timer capture port Input
GT_PWM05
64
I/O
O
Pulse-width modulated output
GT_CCP00
22
DESCRIPTION
Timer capture ports
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Table 7-2. Signal Descriptions (continued)
FUNCTION
GPIO
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
GPIO10
1
I/O
I/O
GPIO11
2
I/O
I/O
GPIO12
3
I/O
I/O
GPIO13
4
I/O
I/O
GPIO14
5
I/O
I/O
GPIO15
6
I/O
I/O
GPIO16
7
I/O
I/O
GPIO17
8
I/O
I/O
GPIO22
15
I/O
I/O
GPIO23
16
I/O
I/O
GPIO24
17
I/O
I/O
GPIO28
18
I/O
I/O
GPIO29
20
I/O
I/O
GPIO25
21
O
O
GPIO31
45(1)
I/O
I/O
GPIO0
50
I/O
I/O
GPIO32
52
I/O
O
GPIO30
53
I/O
I/O
GPIO1
55
I/O
I/O
GPIO2
57
I/O
I/O
GPIO3
58
I/O
I/O
GPIO4
59
I/O
I/O
GPIO5
60
I/O
I/O
GPIO6
61
I/O
I/O
GPIO7
62
I/O
I/O
GPIO8
63
I/O
I/O
GPIO9
64
I/O
I/O
SIGNAL NAME
DESCRIPTION
General-purpose inputs or outputs
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Table 7-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
I/O
O
3
I/O
O
52
O
O
53
I/O
O
50
I/O
I/O
I2S audio port data 1 (RX/TX)
60
I
I/O
I2S audio port data 1 (RX and TX)
45(1)
I/O
I/O
50
I/O
I/O
52
O
O
I2S audio port data (only output mode is supported on
pin 52)
64
I/O
I/O
I2S audio port data (RX and TX)
62
I/O
O
I2S audio port clock
I/O
O
SD card clock data
2
I/O
I/O (open drain)
8
I/O
I/O
I/O
I/O
DESCRIPTION
2
15
17
MCAFSX
21
I2S audio port frame sync
45(1)
53
63
McASP
I2S or PCM
McACLK
McAXR1
McAXR0
McACLKX
SDCARD_CLK
Multimedia card
(MMC or SD)
SDCARD_CMD
SDCARD_DATA0
7
6
64
I2S audio port data 0 (RX and TX)
SD card command line
SD card data
SDCARD_IRQ
63
I/O
I
Interrupt from SD card(3)
pXCLK (XVCLK)
2
I/O
O
Free clock to parallel camera
pVS (VSYNC)
3
I/O
I
Parallel camera vertical sync
pHS (HSYNC)
4
I/O
I
Parallel camera horizontal sync
pDATA8 (CAM_D4)
5
I/O
I
Parallel camera data bit 4
pDATA9 (CAM_D5)
6
I/O
I
Parallel camera data bit 5
7
I/O
I
Parallel camera data bit 6
Parallel interface pDATA10 (CAM_D6)
(8-bit π)
pDATA11 (CAM_D7)
24
1
I2S audio port clock outputs
8
I/O
I
Parallel camera data bit 7
pCLK (PIXCLK)
55
I/O
I
Pixel clock from parallel camera sensor
pDATA7 (CAM_D3)
58
I/O
I
Parallel camera data bit 3
pDATA6 (CAM_D2)
59
I/O
I
Parallel camera data bit 2
pDATA5 (CAM_D1)
60
I
I
Parallel camera data bit 1
pDATA4 (CAM_D0)
61
I/O
I
Parallel camera data bit 0
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Table 7-2. Signal Descriptions (continued)
FUNCTION
Power
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
VDD_DIG1
9
—
—
Internal digital core voltage
VIN_IO1
10
—
—
Device supply voltage (VBAT)
VDD_PLL
24
—
—
Internal analog voltage
LDO_IN2
25
—
—
Internal analog RF supply from analog DC/DC output
VDD_PA_IN
33
—
—
Internal PA supply voltage from PA DC/DC output
LDO_IN1
36
—
—
Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA
37
—
—
Analog DC/DC input (connected to device input supply
[VBAT])
DCDC_ANA_SW
38
—
—
Internal analog DC/DC switching node
VIN_DCDC_PA
39
—
—
PA DC/DC input (connected to device input supply
[VBAT])
DCDC_PA_SW_P
40
—
—
Internal PA DC/DC switching node
DCDC_PA_SW_N
41
—
—
Internal PA DC/DC switching node
DCDC_PA_OUT
42
—
—
Internal PA buck converter output
DCDC_DIG_SW
43
—
—
Internal digital DC/DC switching node
VIN_DCDC_DIG
44
—
—
Digital DC/DC input (connected to device input supply
[VBAT])
DCDC_ANA2_SW_P
45(1)
—
—
Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N
46
—
—
Internal analog to DC/DC converter –ve switching node
VDD_ANA2
47
—
—
Internal analog to DC/DC output
VDD_ANA1
48
—
—
Internal analog supply fed by ANA2 DC/DC output
VDD_RAM
49
—
—
Internal SRAM LDO output
VIN_IO2
54
—
—
Device supply voltage (VBAT)
Internal digital core voltage
SIGNAL NAME
DESCRIPTION
VDD_DIG2
56
—
—
Reset
nRESET
32
I
I
RF
RF_BG
31
I/O
I/O
5
I/O
I/O
45(1)
I/O
I/O
6
I/O
I/O
53
I/O
I/O
8
I/O
I/O
50
I/O
I/O
7
I/O
I/O
52
O
O
FLASH_SPI_CLK
11
O
O
Clock to SPI serial flash (fixed default)
FLASH_SPI_DOUT
12
O
O
Data to SPI serial flash (fixed default)
FLASH_SPI_DIN
13
I
I
Data from SPI serial flash (fixed default)
FLASH_SPI_CS
14
O
O
Device select to SPI serial flash (fixed default)
GSPI_CLK
GSPI_MISO
SPI
GSPI_CS
GSPI_MOSI
FLASH SPI
Global master device reset (active low)
WLAN analog RF 802.11 b/g/n bands
General SPI clock
General SPI MISO
General SPI device select
General SPI MOSI
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Table 7-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
UART1_TX
UART1_RX
UART1_RTS
UART
UART1_CTS
UART0_TX
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
1
I/O
O
7
I/O
O
16
I/O
O
55
I/O
O
58
I/O
O
2
I/O
I
8
I/O
I
17
I/O
I
45(1)
I/O
I
57
I/O
I
59
I/O
I
50
I/O
O
62
I/O
O
61
I/O
I
3
I/O
O
53
I/O
O
55
I/O
O
62
I/O
O
DESCRIPTION
UART TX data
UART1 TX data
UART RX data
UART1 RX data
UART1 request-to-send (active low)
UART1 clear-to-send (active low)
UART0 TX data
4
I/O
I
45(1)
I/O
I
57
I/O
I
UART0 RX data
I/O
I
UART0 clear-to-send input (active low)
50
I/O
O
52
O
O
61
I/O
O
62
I/O
O
21(4)
O
I
Sense-on-power 2
Sense-On-Power SOP1
34
I
I
Configuration sense-on-power 1
SOP0
35
I
I
Configuration sense-on-power 0
UART0_RX
UART0_CTS
UART0_RTS
SOP2
(1)
(2)
(3)
(4)
26
50
61
UART0 RX data
UART0 request-to-send (active low)
Pin 45 is used by an internal DC/DC (ANA2_DCDC). For the CC3230S device, pin 45 can be used as GPIO_31 if a supply is provided
on pin 47.
LPDS retention unavailable.
Future support.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
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7.4 Pin Multiplexing
Table 7-3. Pin Multiplexing
Digital Function (XXX Field Encoding)(1)
ANALOG OR SPECIAL FUNCTION
Register
Address
Register
Name
Pin
0x4402
E0C8
GPIO_PAD_
CONFIG_10
0x4402
E0CC
BLE COEX
JTAG
Hostless
Mode
1
—
GPIO_PAD_
CONFIG_11
2
0x4402
E0D0
GPIO_PAD_
CONFIG_12
3
0x4402
E0D4
GPIO_PAD_
CONFIG_13
4
—
Y
Y
Y
GPIO13
—
0x4402
E0D8
GPIO_PAD_
CONFIG_14
5
—
Y
Y
Y
GPIO14
0x4402
E0DC
GPIO_PAD_
CONFIG_15
6
—
Y
Y
Y
0x4402
E0E0
GPIO_PAD_
CONFIG_16
7
—
Y
Y
0x4402
E0E4
GPIO_PAD_
CONFIG_17
8
—
Y(5)
0x4402
E0F8
GPIO_PAD_
CONFIG_22
15
—
0x4402
E0FC
GPIO_PAD_
CONFIG_23
16
0x4402
E100
GPIO_PAD_
CONFIG_24
0x4402
E140
GPIO_PAD_
CONFIG_40
0x4402
E110
GPIO_PAD_
CONFIG_28
CC_COEX
_SW_OUT
CC_COEX
_BLE_IN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Y
Y
Y
GPIO10
I2C_
SCL
—
GT_
PWM06
—
—
SDCARD_
CLK
UART1_
TX
—
—
—
—
GT_
CCP01
—
—
Y(5)
Y
—
GPIO11
I2C_
SDA
—
GT_
PWM07
pXCLK
(XVCLK)
—
SDCARD_
CMD
UART1_
RX
—
—
—
—
GT_
CCP02
MCAFSX
—
Y
Y
Y
GPIO12
—
—
McACLK
pVS
(VSYNC)
I2C_
SCL
—
UART0_
TX
—
—
—
—
GT_
CCP03
—
—
—
pHS
(HSYNC)
I2C_
SDA
—
UART0_
RX
—
—
—
—
GT_
CCP04
—
—
—
—
pDATA8
(CAM_D4)
I2C_
SCL
—
GSPI_
CLK
—
—
—
—
GT_
CCP05
—
GPIO15
—
—
—
pDATA9
(CAM_D5)
I2C_
SDA
—
GSPI_
MISO
SDCARD_
DATA0
—
—
—
—
GT_
CCP06
Y
GPIO16
—
—
—
pDATA10
(CAM_D6)
UART1_
TX
—
GSPI_
MOSI
SDCARD_
CLK
—
—
—
—
GT_
CCP07
Y
—
GPIO17
—
—
—
pDATA11
(CAM_D7)
UART1_
RX
—
GSPI_
CS
SDCARD_
CMD
—
—
—
—
—
Y
Y
Y
GPIO22
—
—
—
—
GT_
CCP04
—
McAFSX
—
—
—
—
—
—
Muxed
with
JTAG
—
—
—
GPIO23
TDI
UART1_
TX
—
—
—
—
—
—
I2C_
SCL
—
—
—
—
17
Muxed
with
JTAG
TDO
—
—
—
GPIO24
TDO
UART1_
RX
—
GT_
CCP06
PWM0
McAFSX
—
—
I2C_
SDA
—
—
—
—
18
—
Y(4)
Y(4)
Y(4)
GPIO28
—
—
—
—
—
—
—
—
—
—
—
—
—
19
Muxed
with
JTAG
or
SWD
and
TCK
—
—
—
—
TCK
—
—
—
—
—
—
GT_
PWM03
—
—
—
—
—
—
—
—
GPIO29
TMS
—
—
—
—
—
—
—
—
—
—
—
—
0x4402
E114
GPIO_PAD_
CONFIG_29
20
Muxed
with
JTAG
or
SWD
and
TMSC
0x4402
E104
GPIO_PAD_
CONFIG_25
21(2)
—
Y(5)
Y
—
GPIO25
—
McAFSX
—
—
—
—
—
—
GT_
PWM02
—
—
—
—
0x4402
E108
GPIO_PAD_
CONFIG_26
29
—
—
—
—
ANTSEL
1(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
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Table 7-3. Pin Multiplexing (continued)
Digital Function (XXX Field Encoding)(1)
ANALOG OR SPECIAL FUNCTION
Register
Address
Register
Name
Pin
0x4402
E10C
GPIO_PAD_
CONFIG_27
0x4402
E11C
JTAG
Hostless
Mode
30
—
GPIO_PAD_
CONFIG_31
45(4) (3)
0x4402
E0A0
GPIO_PAD_
CONFIG_0
0x4402
E120
BLE COEX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
—
ANTSEL
2(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
GPIO31
—
UART1_
RX
—
—
—
McAXR0
GSPI_CL
K
—
UART0_
RX
—
—
McAFSX
—
Y
Y
Y
GPIO0
—
—
UART0_
RTS
McAXR0
—
McAXR1
GT_
CCP00
—
GSPI_
CS
UART1_
RTS
—
UART0_
CTS
—
—
Y(4)
Y(4)
Y(4)
GPIO32
—
McACLK
—
McAXR0
—
UART0_
RTS
—
GSPI_
MOSI
—
—
—
—
—
-—
Y(4)
Y(4)
Y(4)
GPIO30
—
McACLK
McAFSX
GT_
CCP05
—
—
GSPI_
MISO
—
UART0_
TX
—
—
—
—
—
—
UART0_
TX
pCLK
(PIXCLK)
—
UART1_
TX
GT_
CCP01
—
—
—
—
—
—
GPIO2
—
—
UART0_
RX
—
—
UART1_
RX
GT_
CCP02
—
—
—
—
—
—
GPIO3
—
—
—
pDATA7
(CAM_D3)
—
UART1_
TX
—
—
—
—
—
—
—
—
—
pDATA6
(CAM_D2)
—
UART1_
RX
—
—
—
—
—
—
—
—
—
—
pDATA5
(CAM_D1)
—
McAXR1
GT_
CCP05
—
—
—
—
—
—
—
—
UART1_
CTS
pDATA4
(CAM_D0)
UART0_
RTS
UART0_
CTS
GT_
CCP06
—
—
—
—
—
—
—
—
UART1_
RTS
—
—
—
—
—
—
UART0_
RTS
UART0_
TX
—
McACLKX
GPIO8
—
—
—
—
—
SDCARD_
IRQ
McAFSX
—
—
—
—
GT_
CCP06
—
GPIO9
—
—
GT_
PWM05
—
—
SDCARD_
DATA0
McAXR0
—
—
—
—
GT_
CCP00
—
CC_COEX
_SW_OUT
CC_COEX
_BLE_IN
—
—
—
Y
50
—
GPIO_PAD_
CONFIG_32
52
0x4402
E118
GPIO_PAD_
CONFIG_30
53
0x4402
E0A4
GPIO_PAD_
CONFIG_1
55
—
—
—
—
GPIO1
0x4402
E0A8
GPIO_PAD_
CONFIG_2
57
—
—
—
—
0x4402
E0AC
GPIO_PAD_
CONFIG_3
58
—
Y(5)
Y
—
0x4402
E0B0
GPIO_PAD_
CONFIG_4
59
—
Y(5)
Y
—
GPIO4
—
0x4402
E0B4
GPIO_PAD_
CONFIG_5
60
—
Y
Y
Y
GPIO5
0x4402
E0B8
GPIO_PAD_
CONFIG_6
61
—
Y
Y
Y
GPIO6
0x4402
E0BC
GPIO_PAD_
CONFIG_7
62
—
—
—
—
GPIO7
0x4402
E0C0
GPIO_PAD_
CONFIG_8
63
—
Y
Y
Y
0x4402
E0C4
GPIO_PAD_
CONFIG_9
64
-—
Y
Y
Y
(1)
(2)
(3)
(4)
(5)
28
Pin mux encodings with (RD) denote the default encoding after reset release.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During
hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
Pin 45 is used by an internal DC/DC (ANA2_DCDC). For the CC3230S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
LPDS retention unavailable.
Output Only
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7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
Table 7-4 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-time
power up and reset (nRESET pulled low).
Table 7-4. Drive Strength and Reset States for Analog and Digital Multiplexed Pins
Pin
Board-Level Configuration and
Use
Default State at First Power Up
or Forced Reset
State After Configuration of Analog
Maximum
Switches (ACTIVE, LPDS, and HIB Effective Drive
Power Modes)
Strength (mA)
29
Connected to the enable pin of the
Analog is isolated. The digital I/O cell Determined by the I/O state, as are
RF switch (ANTSEL1). Other use is
is also isolated.
other digital I/Os.
not recommended.
4
30
Connected to the enable pin of the
Analog is isolated. The digital I/O cell Determined by the I/O state, as are
RF switch (ANTSEL2). Other use is
is also isolated.
other digital I/Os.
not recommended.
4
45
VDD_ANA2 (pin 47) must be
shorted to the input supply rail.
Otherwise, the pin is driven by the
ANA2 DC/DC.
Analog is isolated. The digital I/O cell Determined by the I/O state, as are
is also isolated.
other digital I/Os.
4
50
Generic I/O
Analog is isolated. The digital I/O cell Determined by the I/O state, as are
is also isolated.
other digital I/Os.
4
52
The pin must have an external
pullup of 100 kΩ to the supply rail
Analog is isolated. The digital I/O cell Determined by the I/O state, as are
and must be used in output signals is also isolated.
other digital I/Os.
only.
4
53
Generic I/O
Analog is isolated. The digital I/O cell Determined by the I/O state, as are
is also isolated.
other digital I/Os.
4
57
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell is Determined by the I/O state, as are
also isolated.
other digital I/Os.
4
58
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell is Determined by the I/O state, as are
also isolated.
other digital I/Os.
4
59
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell is Determined by the I/O state, as are
also isolated.
other digital I/Os.
4
60
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell is Determined by the I/O state, as are
also isolated.
other digital I/Os.
4
7.6 Pad State After Application of Power to Device, Before Reset Release
When a stable power is applied to the CC3230x device for the first time or when supply voltage is restored to
the proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is undefined
in the period starting from the release of nRESET and until DIG_DCDC powers up. This period is less than
approximately 10 ms. During this period, pads can be internally pulled weakly in either direction. If a certain set
of pins is required to have a definite value during this pre-reset period, an appropriate pullup or pulldown resistor
must be used at the board level. The recommended value of this external pull is 2.7 kΩ.
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7.7 Connections for Unused Pins
All unused pin should be configured as stated in Table 7-5.
Table 7-5. Connections for Unused Pins
FUNCTION
SIGNAL DESCRIPTION
GPIO
General-purpose input or
output
No Connect
NC
SOP
Reset
30
ACCEPTABLE PRACTICE
PREFERRED PRACTICE
Wake up I/O source should not be
floating during hibernate.
All the I/O pins will float while in
Hibernate and Reset states. Ensure
pullup and pulldown resistors are
available on board to maintain the
state of the I/O.
Leave unused GPIOs as NC
Unused pin, leave as NC.
Unused pin, leave as NC
Configuration sense-onpower
Ensure pulldown resistors are
available on unused SOP pins
100-kΩ Pull down resistor
on SOP0 and SOP1. 2.7kΩ pull down on SOP2
RESET input for the device
Never leave the reset pin floating
RTC_XTAL_N
When using an external oscillator,
add a 100-kΩ pullup resistor to VIO
WLAN_XTAL_N
When using an external oscillator,
connect to ground if unused
JTAG interface
Leave as NC if unused
Clock
JTAG
PIN
NUMBER
26, 27, 28
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8 Specifications
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over
process and voltage, unless otherwise indicated.
8.1 Absolute Maximum Ratings
All measurements are referenced at the device pins unless otherwise indicated. All specifications are over process and
overvoltage unless otherwise indicated.
Over operating free-air temperature range (unless otherwise noted)(1) (2)
VBAT and VIO
Supply voltage
Pins: 37, 39, 44
VIO – VBAT (differential)
Pins: 10, 54
MAX
–0.5
3.8
UNIT
V
VBAT and VIO should be tied
together
Digital inputs
RF pins
Analog pins, Crystal
MIN
Pins: 22, 23, 51, 52
V
–0.5
VIO + 0.5
V
–0.5
2.1
V
–0.5
2.1
V
Operating temperature, TA
–40
85
°C
Storage temperature, Tstg
–55
125
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
8.2 ESD Ratings
VALUE
VESD
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Power-On Hours (POH)
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's
standard terms and conditions for TI semiconductor products.
OPERATING CONDITION
TA up to 85°C(1)
(1)
POWER-ON HOURS [POH]
(hours)
87,600
The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device
can be in any other state.
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8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2)
Supply voltage
VBAT, VIO
(shorted to VBAT)
Pins: 10, 37, 39, 44, 54
Direct battery
connection(3)
MIN
TYP
MAX
2.1(4)
3.3
3.6
Ambient thermal slew
(1)
(2)
(3)
(4)
–20
UNIT
V
20 °C/minute
Operating temperature is limited by crystal frequency variation.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the
transmission.
To ensure WLAN performance, ripple on the supply must be less than ±300 mV.
The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also
2.1 V, and care must be taken when operating at the minimum specified voltage.
8.5 Current Consumption Summary (CC3230S)
Table 8-1. Current Consumption Summary (CC3230S)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (5)
PARAMETER
1 DSSS
TX
MCU ACTIVE
6 OFDM
NWP ACTIVE
54 OFDM
RX
272
TX power level = 4
190
TX power level = 0
248
TX power level = 4
182
TX power level = 0
223
TX power level = 4
160
1 DSSS
6 OFDM
54 OFDM
NWP idle
59
TX power level = 0
269
TX power level = 4
187
TX power level = 0
245
TX power level = 4
179
TX power level = 0
220
TX power level = 4
157
1 DSSS
56
54 OFDM
56
connected(3)
6 OFDM
NWP ACTIVE
54 OFDM
MCU LPDS
RX
NWP LPDS(2)
TX power level = 0
266
TX power level = 4
184
TX power level = 0
242
TX power level = 4
176
TX power level = 0
217
TX power level = 4
154
1 DSSS
53
54 OFDM
53
120 µA at 64KB
135 µA at 256KB
NWP idle connected(3)
32
mA
12.2
1 DSSS
TX
mA
15.3
NWP ACTIVE
RX
MAX UNIT
59
54 OFDM
1 DSSS
MCU SLEEP
TYP(6)
TX power level = 0
NWP idle connected(3)
TX
MIN
135
mA
µA
710
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Table 8-1. Current Consumption Summary (CC3230S) (continued)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (5)
PARAMETER
MCU SHUTDOWN
MCU shutdown
MCU HIBERNATE
MCU hibernate
Peak calibration current(4)
(1)
(2)
(3)
(4)
(5)
(6)
MIN
TYP(6)
MAX UNIT
1
µA
4.5
µA
VBAT = 3.6 V
420
VBAT = 3.3 V
450
VBAT = 2.1 V
670
mA
TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power
backed off approximately 4 dB.
LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The
CC3230x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 µA.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is
performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.
There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further
details, see CC31xx, CC32xx SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
The CC3230x system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
Typical numbers assume a VSWR of 1.5:1.
8.6 Current Consumption Summary (CC3230SF)
Table 8-2. Current Consumption Summary (CC3230SF)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (5)
PARAMETER
1 DSSS
TX
MCU ACTIVE
6 OFDM
NWP ACTIVE
54 OFDM
RX
NWP idle
286
TX power level = 4
202
TX power level = 0
255
TX power level = 4
192
TX power level = 0
232
TX power level = 4
174
1 DSSS
74
54 OFDM
74
6 OFDM
NWP ACTIVE
54 OFDM
RX
MAX UNIT
mA
25.2
1 DSSS
MCU SLEEP
TYP(5)
TX power level = 0
connected(3)
TX
MIN
TX power level = 0
282
TX power level = 4
198
TX power level = 0
251
TX power level = 4
188
TX power level = 0
228
TX power level = 4
170
1 DSSS
54 OFDM
NWP idle connected(3)
mA
70
70
21.2
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Table 8-2. Current Consumption Summary (CC3230SF) (continued)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (5)
PARAMETER
1 DSSS
6 OFDM
TX
NWP active
54 OFDM
MCU LPDS
RX
TYP(5)
TX power level = 0
266
TX power level = 4
184
TX power level = 0
242
TX power level = 4
176
TX power level = 0
217
TX power level = 4
154
1 DSSS
53
54 OFDM
53
120 µA at 64KB
135 µA at 256KB
NWP LPDS(2)
MIN
NWP idle connected(3)
135
MAX UNIT
mA
µA
710
MCU
SHUTDOWN
MCU shutdown
1
µA
MCU
HIBERNATE
MCU hibernate
4.5
µA
Peak calibration
(1)
current(4)
VBAT = 3.6 V
420
VBAT = 3.3 V
450
VBAT = 2.1 V
670
mA
TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power
backed off approximately 4 dB.
LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The
CC3230x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 µA.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,
typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be
controlled by a configuration file in the serial flash.
Typical numbers assume a VSWR of 1.5:1.
(2)
(3)
(4)
(5)
8.7 TX Power Control
The CC3230x has several options for modifying the output power of the device when required. It is possible
to lower the overall output power at a global level using the global TX power level setting. In addition, the
2.4 GHz band allows the user to enter additional back-offs 1, per channel, region 2and modulation rates 3,
via Image creator (see the UniFlash CC3x20, CC3x35 SimpleLink™ Wi-Fi® and Internet-on-a chip™ Solution
ImageCreator and Programming Tool User's Guide for more details).
Figure 8-1, Figure 8-2, and Figure 8-3 show TX power and IBAT versus TX power level settings for the CC3230S
device at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the CC3230SF device, the IBAT
current has an increase of approximately 10 mA to 15 mA depending on the transmitted rate. The TX power
level will remain the same.
1
2
3
34
The back-off range is between -6 dB to +6 dB in 0.25dB increments.
FCC/ISED, ETSI (Europe), and Japan are supported.
Back-off rates are grouped into 11b rates, high modulation rates (MCS7, 54 OFDM and 48 OFDM), and lower modulation rates (all
other rates).
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In Figure 8-1, the area enclosed in the circle represents a significant reduction in current during transition from
TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends
using TX power level 4 to reduce the current.
1 DSSS
19.00
280.00
Color by
17.00
264.40
TX Power (dBm)
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
TX Power (dBm)
15.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
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54 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
15
Figure 8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
36
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8.8 Brownout and Blackout Conditions
The device enters a brownout condition when the input voltage drops below Vbrownout (see Figure 8-4 and Figure
8-5). This condition must be considered during design of the power supply routing, especially when operating
from a battery. High-current operations, such as a TX packet or any external activity (not necessarily related
directly to networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The
resistance includes the internal resistance of the battery, the contact resistance of the battery holder (four
contacts for 2× AA batteries), and the wiring and PCB routing resistance.
Note
When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during
HIBERNATE state.
Figure 8-4. Brownout and Blackout Levels (1 of 2)
Figure 8-5. Brownout and Blackout Levels (2 of 2)
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In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the
Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout
condition is equivalent to a hardware reset event in which all states within the device are lost.
Table 8-3 lists the brownout and blackout voltage levels.
Table 8-3. Brownout and Blackout Voltage Levels
CONDITION
VOLTAGE LEVEL
UNIT
Vbrownout
2.1
V
Vblackout
1.67
V
8.9 Electrical Characteristics for GPIO Pins
8.9.1 Electrical Characteristics: GPIO Pins Except 29, 30, 50, 52, and 53
TA = 25°C, VBAT = 2.1 V to 3.3 V.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
V
VIL
Low-level input voltage
–0.5
0.35 × VDD
V
IIH
High-level input current
5
nA
IIL
Low-level input current
5
nA
VOH
VOL
IOH
IOL
(1)
38
High-level output voltage
Low-level output voltage
High-level
source
current
4
UNIT
CIN
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
V
2-mA drive
2
4-mA drive
4
6-mA drive
6
2-mA drive
2
Low-level
4-mA drive
sink current
6-mA drive
pF
4
mA
mA
6
TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk
of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
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8.9.2 Electrical Characteristics: GPIO Pins 29, 30, 50, 52, and 53
TA = 25°C, VBAT = 2.1 V to 3.6 V.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
V
VIL
Low-level input voltage
–0.5
0.35 × VDD
V
IIH
High-level input current
50
nA
IIL
Low-level input current
50
nA
VOH
VOL
IOH
IOL
VIL
(1)
7
UNIT
CIN
High-level output voltage
Low-level output voltage
High-level
source current,
VOH = 2.4
Low-level sink
current
pF
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O
drive strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O
drive strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
V
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O
drive strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O
drive strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O
drive strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
V
2-mA
drive
1.5
4-mA
drive
2.5
6-mA
drive
3.5
2-mA
drive
1.5
4-mA
drive
2.5
6-mA
drive
3.5
mA
mA
nRESET
0.6
V
TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk
of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
8.10 Electrical Characteristics for Pin Internal Pullup and Pulldown
Table 8-4. Electrical Characteristics for Pin Internal Pullup and Pulldown
TA = 25°C, VBAT = 3.0 V.
PARAMETER
IOH
TEST CONDITIONS
Pullup current, VOH = 2.4 (VDD = 3.0 V)
MIN
5
TYP
MAX
10
UNIT
µA
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Table 8-4. Electrical Characteristics for Pin Internal Pullup and Pulldown (continued)
TA = 25°C, VBAT = 3.0 V.
PARAMETER
IOL
TEST CONDITIONS
MIN
Pulldown current, VOL = 0.4 (VDD = 3.0
V)
TYP
MAX
5
UNIT
µA
8.11 WLAN Receiver Characteristics
Table 8-5. WLAN Receiver Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).
PARAMETER
TEST CONDITIONS (Mbps)
Sensitivity
(8% PER for 11b rates, 10% PER for 11g/11n
rates)(2)
TYP
1 DSSS
–96.0
2 DSSS
–94.0
11 CCK
–88.0
6 OFDM
–90.5
9 OFDM
–90.0
18 OFDM
–86.5
36 OFDM
–80.5
54 OFDM
–74.5
MCS7
Maximum input level
(10% PER)
(1)
(2)
MIN
(GF)(1)
MAX
UNIT
dBm
–71.5
802.11b
–4.0
802.11g
–10.0
dBm
Sensitivity for mixed mode is 1-dB worse.
Sensitivity is 1-dB worse on channel 13 (2472 MHz).
8.12 WLAN Transmitter Characteristics
Table 8-6. WLAN Transmitter Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 6 (2437 MHz).(1) (2)
PARAMETER
Operating frequency
Maximum RMS output power measured at 1
dB from IEEE spectral mask or EVM
Transmit center frequency accuracy
(1)
(2)
(3)
(4)
40
TEST CONDITIONS
range(3) (4)
MIN
TYP
2412
1 DSSS
18.0
2 DSSS
18.0
11 CCK
18.3
6 OFDM
17.3
9 OFDM
17.3
18 OFDM
17.0
36 OFDM
16.0
54 OFDM
14.5
MCS7
13.0
–25
MAX
UNIT
2472
MHz
dBm
25
ppm
The OFDM and MCS7 edge channels (2412 and 2462 MHz) have reduced TX power to meet FCC emission limits.
Power of 802.11b rates are reduced to meet ETSI requirements in Europe.
Channels 1 (2142 MHz) through 11 (2462 MHz) are supported for FCC.
Channels 1 (2142 MHz) through 13 (2472MHz) are supported for Europe and Japan. Note that channel 14 is not supported for Japan.
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8.13 WLAN Transmitter Out-of-Band Emissions
The device requires an external band-pass filter to meet the various emission standards, including FCC. Section
8.13.1 presents the minimum attenuation requirements for the band-pass filter. TI recommends using the same
filter used in the reference design to ease the process of certification.
8.13.1 WLAN Filter Requirements
PARAMETER
FREQUENCY (MHz)
Return loss
2412 to 2484
Insertion loss(1)
2412 to 2484
Attenuation
Reference impendence
Filter type
(1)
MIN
TYP
MAX
1
1.5
10
UNIT
dB
804 to 828
30
42
1608 to 1656
20
23
3216 to 3312
30
49
4020 to 4140
40
52
4824 to 4968
20
30
5628 to 5796
20
27
6432 to 6624
20
42
7200 to 7500
35
44
7500 to 10000
20
30
2412 to 2484
dB
dB
50
Ω
Bandpass
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
8.14 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
For proper BLE/2.4 GHz radio coexistence, the following requirements needs to met:
Table 8-7. COEX Isolation Requirement
PARAMETER
Port-to-port isolation
(1)
(2)
Band
MIN
Single antenna
20(1)
Dual antenna Configuration
20(2)
TYP
MAX
UNIT
dB
WLAN/BLE switch used must provide a minimum of 20 dB isolation between ports.
For dual antenna configuration antenna placement must be such that isolation between the BLE and WLAN ports is at least 20 dB.
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8.15 Thermal Resistance Characteristics for RGK Package
THERMAL METRICS(1)
°C/W(2) (3)
AIR FLOW (m/s)(4)
RΘJC
Junction-to-case
6.3
0.0051
RΘJB
Junction-to-board
2.4
0.0051
RΘJA
Junction-to-free air
RΘJMA
PsiJT
Junction-to-package top
PsiJB
(1)
(2)
(3)
Junction-to-board
0.0051
0.765
12.4
1.275
10.8
2.55
0.2
0.0051
0.2
0.765
0.3
1.275
0.1
2.55
2.3
0.0051
2.3
0.765
2.2
1.275
2.4
2.55
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
(4)
Junction-to-moving air
23
14.6
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70°C is assumed.
m/s = meters per second.
8.16 Timing and Switching Characteristics
8.16.1 Power Supply Sequencing
For proper operation of the CC3230x device, perform the recommended power-up sequencing as follows:
1. Tie the following pins together on the board:
• VBAT (pins 37, 39, and 44)
• VIO (pins 54 and 10)
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100 K
||, 0.01 µF, RC = 1 ms).
3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).
For timing diagrams, see Section 8.16.3.
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8.16.2 Device Reset
When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must follow
one of the following alternatives to ensure the reset is properly applied:
•
•
A negative reset pulse (on pin 32) of at least 200-ms duration
If the 200-ms pulse duration cannot be ensured, a pulldown resistor of 2 MΩ must be connected to pin 52
(RTC_XTAL_N). If implemented, a shorter pulse of at least 100 µs can be used.
To ensure a proper reset sequence, the user must call the sl_stop function prior to toggling the reset. When a
reset is required, it is preferable to use the software reset instead of an external trigger.
8.16.3 Reset Timing
8.16.3.1 nRESET (32-kHz Crystal)
Figure 8-6 shows the reset timing diagram for the 32-kHz crystal first-time power-up and reset removal.
T1
T2
T3
T4
HW INIT
FW INIT
APP CODE
LOAD
VBAT
VIO
nRESET
STATE
POWER
RESET
OFF
APP CODE
EXECUTION
32-kHz
RTC CLK
Figure 8-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal)
Section 8.16.3.2 describes the timing requirements for the 32-kHz clock crystal first-time power-up and reset
removal.
8.16.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
ITEM
NAME
DESCRIPTION
MIN
nReset timing after VBAT and VIO
supply are stable
NOM
T1
nReset timing
T2
Hardware wake-up time
T3
Time taken by ROM
firmware to initialize
hardware
Includes 32.768-kHz XOSC settling
time
App code load time for
CC3230S
CC3230S
Image size (KB) × 1.7 ms
App code integrity check
time for CC3230SF
CC3230SF
Image size (KB) × 0.06 ms
T4
MAX
UNIT
1
ms
25
ms
1.1
s
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8.16.3.3 nRESET (External 32-kHz Clock)
Figure 8-7 shows the reset timing diagram for the external 32-kHz clock first-time power-up and reset removal.
T1
T2
T3
T4
RESET
HW INIT
FW INIT
APP CODE
LOAD
VBAT
VIO
nRESET
STATE
POWER
OFF
APP CODE
EXECUTION
32-kHz
RTC CLK
Figure 8-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32-kHz Clock)
Section 8.16.3.3.1 describes the timing requirements for the external 32-kHz clock first-time power-up and reset
removal.
8.16.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Clock)
ITEM
NAME
DESCRIPTION
MIN
nReset timing after VBAT and
VIO supply are stable
NOM
T1
nReset time
T2
Hardware wake-up time
T3
Time taken by ROM firmware to
initialize hardware
CC3230S
10.3
CC3230SF
17.3
App code load time
CC3230S
Image size (KB) × 1.7 ms
App code integrity check time
CC3230SF
Image size (KB) × 0.06 ms
T4
44
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MAX
UNIT
1
ms
25
ms
ms
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8.16.4 Wakeup From HIBERNATE Mode
Note
The 32.768-kHz crystal is enabled by default when the chip goes into HIBERNATE mode.
Table 8-8 lists the software hibernate timing requirements.
Table 8-8. Software Hibernate Timing Requirements
ITEM
NAME
DESCRIPTION
THIB_MIN
Minimum hibernate time
Twake_from_hib (1)
Hardware wakeup time plus
firmware initialization time
T_APP_CODE_LOAD
App code load time
(1)
(2)
MIN
TYP
MAX
10
UNIT
ms
50(2)
CC3230S
Image size (KB) × 1.7 ms
CC3230SF
Image size (KB) × 0.06 ms
ms
ms
Twake_from_hib can be 200 ms on rare occasions when calibration is performed. Calibration is performed sparingly, typically when exiting
Hibernate and only if temperature has changed by more than 20°C or more than 24 hours have elapsed since a prior calibration.
Wake-up time can extend to 75 ms if a patch is downloaded from the serial Flash.
Figure 8-8 shows the timing diagram for wakeup from HIBERNATE mode.
Application software requests
entry to hibernate moade
THIB_MIN
Twake_from_hib
TAPP_CODE_LOAD
VBAT
nRESET
STATE
ACTIVE
Hibernate
HW WAKEUP
FW INIT
APP CODE
LOAD
EXECUTION
32-kHz
RTC CLK
Figure 8-8. Wakeup From HIBERNATE Timing Diagram
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8.16.5 Clock Specifications
The CC3230x device requires two separate clocks for operation:
•
•
A slow clock running at 32.768 kHz is used for the RTC.
A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.
The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated
TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system
and to reduce overall cost.
8.16.5.1 Slow Clock Using Internal Oscillator
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock
frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P
(pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.
Figure 8-9 shows the crystal connections for the slow clock.
51
RTC_XTAL_P
10 pF
GND
32.768 kHz
RTC_XTAL_N
52
10 pF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 8-9. RTC Crystal Connections
Table 8-9 lists the RTC crystal requirements.
Table 8-9. RTC Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
Frequency
TYP
MAX
UNIT
±150
ppm
32.768
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
32.768 kHz
46
MIN
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70
kΩ
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8.16.5.2 Slow Clock Using an External Clock
When an RTC oscillator is present in the system, the CC3230x device can accept this clock directly as an
input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock must be a
CMOS-level clock compatible with VIO fed to the device.
Figure 8-10 shows the external RTC input connection.
RTC_XTAL_P
32.768 kHz
VIO
Host system
100 kΩ
RTC_XTAL_N
Copyright © 2018, Texas Instruments Incorporated
Figure 8-10. External RTC Input
Section 8.16.5.2.1 lists the external RTC digital clock requirements.
8.16.5.2.1 External RTC Digital Clock Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
Frequency accuracy
(initial plus temperature plus aging)
tr, tf
Vil
Slow clock input voltage limits
MAX
±150
ppm
100
20%
Square wave, DC coupled
50%
ns
80%
0.65 × VIO
VIO
0
0.35 × VIO
1
Input impedance
UNIT
Hz
Input transition time tr, tf (10% to 90%)
Frequency input duty cycle
Vih
TYP
32768
V
Vpeak
MΩ
5
pF
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8.16.5.3 Fast Clock (Fref) Using an External Crystal
The CC3230x device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The
crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading
capacitors.
Figure 8-11 shows the crystal connections for the fast clock.
23
WLAN_XTAL_P
6.2 pF
GND
40 MHz
WLAN_XTAL_N
22
6.2 pF
GND
SWAS031-030
A.
The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for
information on frequency tuning.
Figure 8-11. Fast Clock Crystal Connections
Section 8.16.5.3.1 lists the WLAN fast-clock crystal requirements.
8.16.5.3.1 WLAN Fast-Clock Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
Frequency
TYP
MAX
40
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
40 MHz
48
MIN
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UNIT
MHz
±20
ppm
60
Ω
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8.16.5.4 Fast Clock (Fref) Using an External Oscillator
The CC3230x device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the
clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external
TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the
system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the
LDO improves noise on the TCXO power supply.
Figure 8-12 shows the connection.
VCC
XO (40 MHz)
CC3230x
TCXO_EN
EN
82 pF
WLAN_XTAL_P
OUT
WLAN_XTAL_N
Figure 8-12. External TCXO Input
Section 8.16.5.4.1 lists the external Fref clock requirements.
8.16.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
Frequency accuracy (initial plus temperature
plus aging)
Clock voltage limits
45%
Sine or clipped sine wave, AC coupled
0.7
at 1 kHz
Phase noise at 40 MHz
55%
1.2
–143
12
Capacitance
Vpp
–138.5 dBc/Hz
at 100 kHz
Input impedance
ppm
–125
at 10 kHz
Resistance
50%
UNIT
MHz
±20
Frequency input duty cycle
Vpp
MAX
40.00
kΩ
7
pF
8.16.6 Peripherals Timing
This section describes the peripherals that are supported by the CC3230x device:
•
•
•
•
•
•
•
•
•
•
SPI
I2S
GPIOs
I2C
IEEE 1149.1 JTAG
ADC
Camera Parallel Port
UART
SD Host
Timers
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8.16.6.1 SPI
8.16.6.1.1 SPI Master
The CC3230x microcontroller includes one SPI module that can be configured as a master or slave device. The
SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable timing control
between chip select and external clock generation; and a programmable delay before the first SPI word is
transmitted. Slave mode does not include a dead cycle between two successive words.
Figure 8-13 shows the timing diagram for the SPI master.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 8-13. SPI Master Timing Diagram
Section 8.16.6.1.1.1 lists the timing parameters for the SPI master.
8.16.6.1.1.1 SPI Master Timing Parameters
PARAMETER
NUMBER
MIN
F(1)
Clock frequency
Tclk (1)
Clock period
33.3
D(1)
Duty cycle
45%
T6
tIS (1)
RX data setup time
1
T7
tIH
(1)
RX data hold time
2
T8
tOD (1)
T9
(1)
T2
(1)
50
tOH
TX data output delay
TX data hold time
MAX
UNIT
30
MHz
ns
55%
ns
ns
8.5
ns
8
ns
Timing parameter assumes a maximum load of 20 pF.
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8.16.6.1.2 SPI Slave
Figure 8-14 shows the timing diagram for the SPI slave.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 8-14. SPI Slave Timing Diagram
Section 8.16.6.1.2.1 lists the timing parameters for the SPI slave.
8.16.6.1.2.1 SPI Slave Timing Parameters
PARAMETER
NUMBER
MIN
F(1)
MAX
Clock frequency at VBAT = 3.3 V
20
Clock frequency at VBAT ≤ 2.1 V
12
UNIT
MHz
Tclk (1)
Clock period
D(1)
Duty cycle
T6
tIS (1)
RX data setup time
4
ns
T7
tIH (1)
RX data hold time
4
ns
T2
(1)
T8
tOD
T9
tOH (1)
(1)
50
45%
ns
55%
TX data output delay
20
ns
TX data hold time
24
ns
Timing parameter assumes a maximum load of 20 pF at 3.3 V.
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8.16.6.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit
and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A
fractional divider is available for bit-clock generation.
8.16.6.2.1 I2S Transmit Mode
Figure 8-15 shows the timing diagram for the I2S transmit mode.
T2
T1
T3
McACLKX
T4
T4
McAFSX
McAXR0/1
Figure 8-15. I2S Transmit Mode Timing Diagram
Section 8.16.6.2.1.1 lists the timing parameters for the I2S transmit mode.
8.16.6.2.1.1 I2S Transmit Mode Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
MHz
T1
fclk (1)
Clock frequency
9.216
T2
tLP (1)
Clock low period
1/2 fclk
ns
T3
tHT
(1)
Clock high period
1/2 fclk
ns
T4
tOH (1)
TX data hold time
22
ns
(1)
52
Timing parameter assumes a maximum load of 20 pF.
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8.16.6.2.2 I2S Receive Mode
Figure 8-16 shows the timing diagram for the I2S receive mode.
T2
T1
T3
McACLKX
T5
T4
McAFSX
McAXR0/1
Figure 8-16. I2S Receive Mode Timing Diagram
Section 8.16.6.2.2.1 lists the timing parameters for the I2S receive mode.
8.16.6.2.2.1 I2S Receive Mode Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
T1
fclk (1)
Clock frequency
9.216
MHz
T2
tLP (1)
Clock low period
1/2 fclk
ns
T3
tHT
(1)
Clock high period
1/2 fclk
ns
T4
tOH (1)
RX data hold time
0
ns
T5
tOS (1)
RX data setup time
15
ns
(1)
Timing parameter assumes a maximum load of 20 pF.
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8.16.6.3 GPIOs
All digital pins of the device can be used as general-purpose input/output (GPIO) pins. The GPIO module
consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24
programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown
strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.
Note
Unless otherwise stated, GPIO specifications also applies to pins configured as COEX IOs and
network scripter interface
Figure 8-17 shows the GPIO timing diagram.
VDD
80%
20%
tGPIOF
tGPIOR
SWAS031-067
Figure 8-17. GPIO Timing Diagram
8.16.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
Section 8.16.6.3.1.1 lists the GPIO output transition times for Vsupply = 3.3 V.
8.16.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V)(1) (2)
DRIVE
STRENGTH (mA)
2(3)
4(3)
6
(1)
(2)
(3)
DRIVE STRENGTH
CONTROL BITS
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
2MA_EN=1
4MA_EN=1
tr
tf
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
8.0
9.3
10.7
8.2
9.5
11.0
ns
6.6
7.1
7.6
4.7
5.2
5.8
ns
3.2
3.5
3.7
2.3
2.6
2.9
ns
Vsupply = 3.3 V, T = 25°C, total pin load = 30 pF
The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.
The 2-mA and 4-mA drive strength does not apply to the COEX I/O pins. Pins configured as COEX lines are invariably driven at 6 mA.
8.16.6.3.2 GPIO Input Transition Time Parameters
Section 8.16.6.3.2.1 lists the input transition time parameters.
8.16.6.3.2.1 GPIO Input Transition Time Parameters
tr
tf
54
Input transition time (tr, tf), 10% to 90%
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MIN
MAX
UNIT
1
3
ns
1
3
ns
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8.16.6.4 I2C
The CC3230x microcontroller includes one I2C module operating with standard (100 kbps) or fast
(400 kbps) transmission speeds.
Figure 8-18 shows the I2C timing diagram.
T2
T6
T5
I2CSCL
T1
T4
T7
T8
T3
T9
I2CSDA
Figure 8-18. I2C Timing Diagram
Section 8.16.6.4.1 lists the I2C timing parameters.
8.16.6.4.1 I2C Timing Parameters(3)
PARAMETER
NUMBER
T2
MIN
tLP
Clock low period
MAX
See (1)
UNIT
System clock
T3
tSRT
SCL/SDA rise time
T4
tDH
Data hold time
T5
tSFT
SCL/SDA fall time
T6
tHT
Clock high time
See (1)
System clock
T7
tDS
Data setup time
tLP/2
System clock
T8
tSCSR
Start condition setup time
36
System clock
T9
tSCS
Stop condition setup time
24
System clock
(1)
(2)
(3)
See
(2)
ns
N/A
3
ns
This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal
value programmed in this register.
Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of an external pullup resistor. Rise time
depends on the value of the external signal capacitance and external pullup register.
All timing is with 6-mA drive and 20-pF load.
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8.16.6.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control
the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the
IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
Figure 8-19 shows the JTAG timing diagram.
T2
T3
T4
TCK
T7
TMS
T8
TMS Input Valid
T9
TDI
TMS Input Valid
T10
T9
TDI Input Valid
T10
TDI Input Valid
T1
T11
TDO
T8
T7
TDO Output Valid
TDO Output Valid
Figure 8-19. JTAG Timing Diagram
Section 8.16.6.5.1 lists the JTAG timing parameters.
8.16.6.5.1 JTAG Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
15
MHz
T1
fTCK
Clock frequency
T2
tTCK
Clock period
1 / fTCK
ns
T3
tCL
Clock low period
tTCK / 2
ns
T4
tCH
Clock high period
tTCK / 2
ns
T7
tTMS_SU
TMS setup time
1
ns
T8
tTMS_HO
TMS hold time
16
ns
T9
tTDI_SU
TDI setup time
1
ns
T10
tTDI_HO
TDI hold time
16
ns
T11
tTDO_HO
TDO hold time
56
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8.16.6.6 ADC
Figure 8-20 shows the ADC clock timing diagram.
Repeats Every 16 µs
Internal Ch
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
EXT CHANNEL 0
SAR Conversion
16 cycles
INTERNAL CHANNEL
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
EXT CHANNEL 1
SAR Conversion
16 cycles
INTERNAL CHANNEL
Figure 8-20. ADC Clock Timing Diagram
Section 8.16.6.6.1 lists the ADC electrical specifications. See the CC32xx ADC Appnote wiki for further
information on using the ADC and for application-specific examples.
8.16.6.6.1 ADC Electrical Specifications
PARAMETER
Nbits
DESCRIPTION
TEST CONDITIONS and
ASSUMPTIONS
MIN
Number of bits
TYP
12
INL
Integral nonlinearity
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
DNL
Differential nonlinearity
Worst-case deviation of any step
from ideal
Input range
LSB
–1
4
LSB
0
1.4
V
100
Ω
Input capacitance
ADC Pin 57
Input impedance
10
MHz
12
pF
2.15
ADC Pin 58
0.7
ADC Pin 59
2.12
ADC Pin 60
1.17
Number of channels
kΩ
4
Fsample
Sampling rate of each pin
F_input_max
Maximum input signal frequency
SINAD
Signal-to-noise and distortion
Input frequency DC to 300 Hz
and 1.4 Vpp sine wave input
I_active
Active supply current
Average for analog-to-digital
during conversion without
reference current
I_PD
Power-down supply current for
core supply
Total for analog-to-digital when
not active (this must be the SoC
level test)
Absolute offset error
62.5
ksps
31
FCLK = 10 MHz
Gain error
Vref
Bits
2.5
Successive approximation input
clock rate
Clock rate
UNIT
–2.5
Driving source
impedance
FCLK
MAX
55
kHz
60
dB
1.5
mA
1
µA
±2
mV
±2%
ADC reference voltage
1.467
V
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8.16.6.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a
FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 8-21 shows the timing diagram for the camera parallel port.
T3
T2
T4
pCLK
T6
T7
pVS, pHS
pDATA
Figure 8-21. Camera Parallel Port Timing Diagram
Section 8.16.6.7.1 lists the timing parameters for the camera parallel port.
8.16.6.7.1 Camera Parallel Port Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
2
MHz
pCLK
Clock frequency
T2
Tclk
Clock period
1/pCLK
ns
T3
tLP
Clock low period
Tclk/2
ns
T4
tHT
Clock high period
Tclk/2
ns
T6
tIS
RX data setup time
2
ns
T7
tIH
RX data hold time
2
ns
D
Duty cycle
45%
55%
8.16.6.8 UART
The CC3230x device includes two UARTs with the following features:
•
•
•
•
•
•
•
•
•
•
•
58
Programmable baud-rate generator allows speeds up to 3 Mbps
Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered
interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
Generation and detection of line-breaks
Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Generation and detection of even, odd, stick, or no-parity bits
– Generation of 1 or 2 stop-bits
RTS and CTS hardware flow support
Standard FIFO-level and End-of-Transmission interrupts
Efficient transfers using µDMA:
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO
level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level
System clock is used to generate the baud clock.
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8.16.6.9 SD Host
The CC3230x device provides an interface between a local host (LH), such as an MCU and an SD memory card,
and handles SD transactions with minimal LH intervention.
The SD host does the following:
•
•
•
•
•
•
Provides SD card access in 1-bit mode
Deals with SD protocol at the transmission level
Handles data packing
Adds cyclic redundancy checks (CRC)
Start and end bit
Checks for syntactical correctness
The application interface sends every SD command and either polls for the status of the adapter or waits for
an interrupt request. The result is then sent back to the application interface in case of exceptions or to warn
of end-of-operation. The controller can be configured to generate DMA requests and work with minimum CPU
intervention. Given the nature of integration of this peripheral on the CC3230x platform, TI recommends that
developers use peripheral library APIs to control and operate the block. This section emphasizes understanding
the SD host APIs provided in the peripheral library of the CC3230x Software Development Kit (SDK).
The SD Host features are as follows:
•
•
•
•
•
•
•
•
•
•
•
•
Full compliance with SD command and response sets, as defined in the SD memory card
– Specifications, v2.0
– Includes high-capacity (size >2 GB) HC and SD cards
Flexible architecture allows support for new command structure
1-bit transfer mode specifications for SD cards
Built-in 1024-byte buffer for read or write
– 512-byte buffer for both transmit and receive
– Each buffer is 32-bits wide by 128-words deep
32-bit-wide access bus to maximize bus throughput
Single interrupt line for multiple interrupt source events
Two slave DMA channels (1 for TX, 1 for RX)
Programmable clock generation
Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver
Supports configurable busy and response timeout
Support for a wide range of card clock frequency with odd and even clock ratio
Maximum frequency supported is 24 MHz
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8.16.6.10 Timers
Programmable timers can be used to count or time external events that drive the timer input pins. The CC3230x
general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or 32-bit GPTM block
provides two 16-bit timers or counters (referred to as Timer A and Timer B) that can be configured to operate
independently as timers or event counters, or they can be concatenated to operate as one 32-bit timer. Timers
can also be used to trigger µDMA transfers.
The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:
•
•
•
•
•
•
•
60
Operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal
Counts up or counts down
Sixteen 16- or 32-bit capture compare pins (CCP)
User-enabled stalling when the microcontroller asserts CPU Halt flag during debug
Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt
service routine
Efficient transfers using micro direct memory access controller (µDMA):
– Dedicated channel for each timer
– Burst request generated on timer interrupt
Runs from system clock (80 MHz)
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9 Detailed Description
9.1 Overview
The CC3230x wireless MCU family has a rich set of peripherals for diverse application requirements. This
section briefly highlights the internal details of the CC3230x devices and offers suggestions for application
configurations.
9.2 Arm® Cortex®-M4 Processor Core Subsystem
The high-performance Arm® Cortex®-M4 processor provides a cost-conscious platform that meets the needs of
minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
•
•
•
•
The Arm Cortex-M4 core has low-latency interrupt processing with the following features:
– A 32-bit Arm® Thumb® instruction set optimized for embedded applications
– Handler and thread modes
– Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit
– Support for Armv6 unaligned accesses
Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-latency
interrupt processing. The NVIC includes the following features:
– Bits of priority configurable from 3 to 8
– Dynamic reprioritization of interrupts
– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels
– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing
without the overhead of state saving and restoration between interrupts
– Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction
overhead
– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support
Bus interfaces:
– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces
– Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations
Cost-conscious debug solution featuring:
– Debug access to all memory and registers in the system, including access to memory-mapped devices,
access to internal core registers when the core is halted, and access to debug control registers even while
SYSRESETn is asserted
– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access
– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches
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9.3 Wi-Fi® Network Processor Subsystem
The Wi-Fi network processor subsystem includes a dedicated Arm MCU to completely offload the host MCU
along with an 802.11b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN
and Internet connections with 256-bit encryption. The CC3230x devices support station, AP, and Wi-Fi Direct
modes. The device also supports WPA2 personal and enterprise security, WPS 2.0, and WPA3 personal and
enterprise 4. The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack, TLS stack and
network applications such as HTTPS server.
9.3.1 WLAN
The WLAN features are as follows:
•
802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP,
Wi-Fi Direct client, and group owner with CCK and OFDM rates in the 2.4 GHz band (channels 1 through 13).
Note
802.11n is supported only in Wi-Fi® station and Wi-Fi Direct®.
•
•
•
•
•
•
•
The automatically calibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna
without requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in serial flash allows automatic
fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal, and WPA3
Enterprise.
Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the provisioning
decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point with HTTP server
– WPS - Wi-Fi Protected Setup, supporting both push button and pin code options.
– SmartConfig™ Technology: TI proprietary, easy to use, one-step, one-time process used to connect a
CC3230x-enabled device to the home wireless network.
802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket The 802.11
transceiver mode provides the option to select the working channel, rate, and transmitted power. The receiver
mode works with the filtering options.
Antenna selection for best connection
BLE/2.4 GHz radio coexistence mechanism to avoid interference
4
62
See CC3230 SDK v3.40 or later for details. Limited to STA mode only.
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9.3.2 Network Stack
The Network Stack features are as follows:
•
Integrated IPv4, IPv6 TCP/IP stack with BSD socket APIs for simple Internet connectivity with any MCU,
microprocessor, or ASIC
Note
Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
•
•
•
Support of 16 simultaneous TCP, UDP, RAW, SSL\TLS sockets
Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
Built-in network applications and utilities:
– HTTP/HTTPS
• Web page content stored on serial flash
• RESTful APIs for setting and configuring application content
• Dynamic user callbacks
– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized
server. After connecting to the access point, the CC3230x device provides critical information, such as
device name, IP, vendor, and port number.
– DHCP server
– Ping
Table 9-1 describes the NWP features.
Table 9-1. NWP Features
FEATURE
DESCRIPTION
802.11b/g/n station
Wi-Fi standards
802.11b/g AP supporting up to four stations
Wi-Fi Direct client and group owner
Wi-Fi channels
2.4 GHz ISM
Channel Bandwidth
20 MHz
Wi-Fi security
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal and enterprise (1)
Wi-Fi provisioning
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server
IP protocols
IPv4/IPv6
IP addressing
Static IP, LLA, DHCPv4, DHCPv6 with DAD
Cross layer
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW
Ping
Network applications and
utilities
HTTP/HTTPS web server
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
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Table 9-1. NWP Features (continued)
FEATURE
DESCRIPTION
Device identity
Trusted root-certificate catalog
TI root-of-trust public key
The CC3230S and CC3230SF variants also support:
Security
Power management
•
•
•
•
•
•
•
•
•
•
•
•
Secure key storage
Online certificate status protocol (OCSP)
Certificate signing request (CSR)
Unique per device Key-Pair
File system security
Software tamper detection
Cloning protection
Secure boot
Validate the integrity and authenticity of the run-time binary during boot
Initial secure programming
Debug security
JTAG and debug
Enhanced power policy management uses 802.11 power save and deep-sleep power modes
Transceiver
Other
Programmable RX filters with event-trigger mechanism
Rx Metrics for tracking the surrounding RF environment
(1)
See CC3230 SDK v3.40 or newer for details. Limited to STA mode only.
9.4 Security
The SimpleLink™ Wi-Fi® CC3230x Internet-on-a chip device enhances the security capabilities available for
development of IoT devices, while completely offloading these activities from the MCU to the networking
subsystem. The security capabilities include the following key features:
Wi-Fi and Internet Security:
•
Personal and enterprise Wi-Fi security
– Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK)
• WEP
– Enterprise standards
• EAP Fast
• EAP PEAPv0/1
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TLS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2
•
Secure sockets
– Protocol versions: OCSP, SSL v3, TLS 1.0, TLS 1.1, TLS 1.2
– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS
and SSL connections
64
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•
•
•
•
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– Ciphers suites
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
– Server authentication
– Client authentication
– Domain name verification
– Runtime socket upgrade to secure socket – STARTTLS
Secure HTTP server (HTTPS)
Trusted root-certificate catalog – Verifies that the CA used by the application is trusted and known secure
content delivery
TI root-of-trust public key – Hardware-based mechanism that allows authenticating TI as the genuine origin of
a given content using asymmetric keys
Secure content delivery – Allows encrypted file transfer to the system using asymmetric keys created by the
device
Code and Data Security:
•
•
•
•
•
•
•
•
Network passwords and certificates are encrypted and signed.
Cloning protection – Application and data files are encrypted by a unique key per device.
Access control – Access to application and data files only by using a token provided in file creation time. If an
unauthorized access is detected, a tamper protection lock down mechanism takes effect.
Secured boot – Authentication of the application image on every boot
Code and data encryption – User application and data files can be encrypted in the serial flash
Code and data authentication – User Application and data files are authenticated with a public key certificate
Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify data
buffer
Recovery mechanism
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Device Security:
•
•
•
Separate execution environments – Application processor and network processor run on separate Arm cores
Initial secure programming – Allows for keeping the content confidential on the production line
Debug security
– JTAG lock
– Debug ports lock
True random number generator
•
Figure 9-1 shows the high-level structure of the CC3230S and CC3230SF devices. The application image, user
data, and network information files (passwords, certificates) are encrypted using a device-specific key.
CC3230S and CC3230SF
Network Processor + MCU
MCU
Peripherals
SPI and I2C
Network Processor
ARM® Cortex®-M4
Processor
GPIO
256KB RAM /
UART
Internet
Wi-Fi®
HTTPS
MAC
TLS/SSL
Baseband
TCP/IP
Radio
Internet
1MB Flash (CC3230SF)
PWM
ADC
OEM
Application
-
Serial Flash
OEM
Application
Data Files
Network Information
Figure 9-1. CC3230S and CC3230SF High-Level Structure
9.5 Power-Management Subsystem
The CC3230x power-management subsystem contains DC/DC converters to accommodate the different voltage
or current requirements of the system.
•
•
•
•
Digital DC/DC (Pin 44)
– Input: VBAT wide voltage (2.1 to 3.6 V)
ANA1 DC/DC (Pin 37)
– Input: VBAT wide voltage (2.1 to 3.6 V)
PA DC/DC (Pin 39)
– Input: VBAT wide voltage (2.1 to 3.6 V)
ANA2 DC/DC (Pin 47, CC3230SF only)
– Input: VBAT wide voltage (2.1 to 3.6 V)
The CC3230x device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage
supply range. The internal power management, including DC/DC converters and LDOs, generates all of the
voltages required for the device to operate from a wide variety of input sources.
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9.6 Low-Power Operating Mode
From a power-management perspective, the CC3230x device comprises the following two independent
subsystems:
Arm® Cortex®-M4 application processor subsystem
Networking subsystem
•
•
Each subsystem operates in one of several power states.
The Arm® Cortex®-M4 application processor runs the user application loaded from an external serial flash, or
internal flash (in CC3230SF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer
functions.
The user program controls the power state of the application processor subsystem. The application processor
can be in one of the five modes described in Table 9-2.
Table 9-2. User Program Modes
APPLICATION PROCESSOR
(MCU) MODE(1)
DESCRIPTION
MCU active mode
MCU executing code at a state rate of 80 MHz
MCU sleep mode
The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode
offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity
from any GPIO line or peripheral.
MCU LPDS mode
State information is lost and only certain MCU-specific register configurations are retained. The MCU
can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)
Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory
retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU
can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the
wake-up source.
MCU hibernate mode
The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly
powered by the input supply is retained. The RTC continues running and the MCU supports wakeup
from an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about
15 ms plus the time to load the application from serial flash, which varies according to code size. In this
mode, the MCU can be configured to wake up using the RTC timer or external event on a GPIO.
MCU shutdown mode
The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in
this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the
nRESET line is changed (low to shut down, high to turn on).
(1)
Modes are listed in order of power consumption, with highest power modes listed first.
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The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network
activity, the NWP sleeps most of the time and wakes up only for beacon reception (see
Table 9-3).
Table 9-3. Networking Subsystem Modes
NETWORK PROCESSOR
MODE
DESCRIPTION
Network active mode
(processing layer 3, 2, and 1)
Transmitting or receiving IP protocol packets
Network active mode
(processing layer 2 and 1)
Transmitting or receiving MAC management frames; IP processing is not required
Network active listen mode
Special power-optimized active mode for receiving beacon frames (no other frames are supported)
Network connected Idle
A composite mode that implements 802.11 infrastructure power-save operation. The CC3230x NWP
automatically enters LPDS mode between beacons and then wakes into active listen mode to receive a
beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS mode and
the cycle repeats.
Advanced features of long sleep interval and IoT low power for extending LPDS time for up to 22
seconds while maintaining Wi-Fi connection is supported in this mode.
Network LPDS mode
Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake
up
Network disabled
The network is disabled
The operation of the application and network processor ensures that the device remains in the lowest power
mode most of the time to preserve battery life.
The following examples show the use of the power modes in applications:
•
•
A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but
sends and receives little data spends most of the time in connected idle, which is a composite of receiving a
beacon frame and waiting for the next beacon.
A product that is not continuously connected to the network but instead wakes up periodically (for example,
every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to
transmit data.
9.7 Memory
9.7.1 External Memory Requirements
The CC3230x device maintains a proprietary file system on the serial flash. The CC3230x file system stores
the MCU binary, service pack file, system files, configuration files, certificate files, web page files, and user files.
By using a format command through the API, users can provide the total size allocated for the file system.
The starting address of the file system cannot be set and is always at the beginning of the serial flash. The
applications microcontroller must access the serial flash memory area allocated to the file system directly
through the CC3230x file system. The applications microcontroller must not access the serial flash memory area
directly.
The file system manages the allocation of serial flash blocks for stored files according to download order,
which means that the location of a specific file is not fixed in all systems. Files are stored on serial flash using
human-readable filenames rather than file IDs. The file system API works using plain text, and file encryption
and decryption is invisible to the user. Encrypted files can be accessed only through the file system.
All file types can have a maximum of 100 supported files in the file system. All files are stored in 4-KB blocks and
thus use a minimum of 4KB of flash space. Fail-safe files require twice the original size and use a minimum of
8KB. Encrypted files are counted as fail-safe in terms of space. The maximum file size is 1MB.
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Table 9-4 lists the minimum required memory consumption under the following assumptions:
• System files in use consume 64 blocks (256KB).
• Vendor files are not taken into account.
• MCU code is taken as the maximal possible size for the CC3230 with fail-safe enabled to account for future
updates, such as through OTA.
• Gang image:
– Storage for the gang image is rounded up to 32 blocks (meaning 128-KB resolution).
– Gang image size depends on the actual content size of all components. Additionally, the image should
be 128KB aligned so unaligned memory is considered lost. Service pack, system files, and the 128KB
aligned memory are assumed to occupy 256KB.
• All calculations consider that the restore-to-default is enabled.
Table 9-4. Recommended Flash Size
ITEM
CC3230S (KB)
CC3230SF (KB)
File system allocation table
20
20
System and configuration files(1)
256
256
Service pack(1)
264
264
MCU Code(1)
512
2048
Gang image size
256 + MCU
256 + MCU
Total
1308 + MCU
2844 + MCU
Minimal flash size(2)
16 MBit
32 MBit
Recommended flash size(2)
16 MBit
32 MBit
(1)
(2)
Including fail-safe
For maximum MCU size
Note
The maximum supported serial flash size is 32MB (256Mb) (see the Using Serial Flash on CC3135
and CC3235x SimpleLink™ Wi-Fi® and Internet-of-Things Devices application report).
9.7.2 Internal Memory
The CC3230x device includes on-chip SRAM to which application programs are downloaded and executed.
The application developer must share the SRAM for code and data. The micro direct memory access (μDMA)
controller can transfer data to and from SRAM and various peripherals. The CC3230x ROM holds the rich set of
peripheral drivers, which saves SRAM space. For more information on drivers, see the CC3230x API list.
9.7.2.1 SRAM
The CC3230x family provides 256KB of on-chip SRAM. Internal RAM is capable of selective retention during
LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map.
Use the µDMA controller to transfer data to and from the SRAM.
When the device enters low-power mode, the application developer can choose to retain a section of memory
based on need. Retaining the memory during low-power mode provides a faster wakeup. The application
developer can choose the amount of memory to retain in multiples of 64KB. For more information, see the API
guide.
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9.7.2.2 ROM
The internal zero-wait-state ROM of the CC3230x device is at address 0x0000 0000 of the device memory and
is programmed with the following components:
•
•
Bootloader
Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
The bootloader is used as an initial program loader (when the serial flash memory is empty). The CC3230x
DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs
peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. The
DriverLib APIs in ROM can be called by applications to reduce flash memory requirements and free the flash
memory for other purposes.
9.7.2.3 Flash Memory
The CC3230SF device comes with an on-chip flash memory of 1MB that allows application code to execute in
place while freeing SRAM exclusively for read-write data. The flash memory is used for code and constant data
sections and is directly attached to the icode/dcode bus of the Arm Cortex-M4 core. A 128-bit-wide instruction
prefetch buffer allows maintenance of maximum performance for linear code or loops that fit inside the buffer.
The flash memory is organized as 2KB sectors that can be independently erased. Reads and writes can be
performed at word (32-bit) level.
9.7.2.4 Memory Map
Table 9-5 describes the various MCU peripherals and how they are mapped to the processor memory. For more
information on peripherals, see the API document.
Table 9-5. Memory Map
START ADDRESS
70
END ADDRESS
DESCRIPTION
0x0000 0000
0x0007 FFFF
On-chip ROM (bootloader + DriverLib)
0x0100 0000
0x010F FFFF
On-chip flash (for user application code)
0x2000 0000
0x2003 FFFF
Bit-banded on-chip SRAM
0x2200 0000
0x23FF FFFF
Bit-band alias of 0x2000 0000 to 0x200F FFFF
0x4000 0000
0x4000 0FFF
Watchdog timer A0
0x4000 4000
0x4000 4FFF
GPIO port A0
0x4000 5000
0x4000 5FFF
GPIO port A1
0x4000 6000
0x4000 6FFF
GPIO port A2
0x4000 7000
0x4000 7FFF
GPIO port A3
0x4000 C000
0x4000 CFFF
UART A0
0x4000 D000
0x4000 DFFF
UART A1
0x4002 0000
0x4000 07FF
I2C A0 (master)
0x4002 0800
0x4002 0FFF
I2C A0 (slave)
0x4002 4000
0x4002 4FFF
GPIO group 4
0x4003 0000
0x4003 0FFF
General-purpose timer A0
0x4003 1000
0x4003 1FFF
General-purpose timer A1
0x4003 2000
0x4003 2FFF
General-purpose timer A2
0x4003 3000
0x4003 3FFF
General-purpose timer A3
0x400F 7000
0x400F 7FFF
Configuration registers
0x400F E000
0x400F EFFF
System control
0x400F F000
0x400F FFFF
µDMA
0x4200 0000
0x43FF FFFF
Bit band alias of 0x4000 0000 to 0x400F FFFF
0x4401 0000
0x4401 0FFF
SDIO master
0x4401 8000
0x4401 8FFF
Camera Interface
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Table 9-5. Memory Map (continued)
START ADDRESS
END ADDRESS
0x4401 C000
0x4401 DFFF
McASP
DESCRIPTION
0x4402 0000
0x4402 1FFF
SSPI
Used for external serial flash
0x4402 1000
0x4402 2FFF
GSPI
Used by application processor
0x4402 5000
0x4402 5FFF
MCU reset clock manager
0x4402 6000
0x4402 6FFF
MCU configuration space
0x4402 D000
0x4402 DFFF
Global power, reset, and clock manager (GPRCM)
0x4402 E000
0x4402 EFFF
MCU shared configuration
0x4402 F000
0x4402 FFFF
Hibernate configuration
0x4403 0000
0x4403 FFFF
Crypto range (includes apertures for all crypto-related
blocks as follows)
0x4403 0000
0x4403 0FFF
DTHE registers and TCP checksum
0x4403 5000
0x4403 5FFF
MD5/SHA
0x4403 7000
0x4403 7FFF
AES
0x4403 9000
0x4403 9FFF
DES
0xE000 0000
0xE000 0FFF
Instrumentation trace Macrocell™
0xE000 1000
0xE000 1FFF
Data watchpoint and trace (DWT)
0xE000 2000
0xE000 2FFF
Flash patch and breakpoint (FPB)
0xE000 E000
0xE000 EFFF
NVIC
0xE004 0000
0xE004 0FFF
Trace port interface unit (TPIU)
0xE004 1000
0xE004 1FFF
Reserved for embedded trace macrocell (ETM)
0xE004 2000
0xE00F FFFF
Reserved
COMMENT
9.8 Restoring Factory Default Configuration
The device has an internal recovery mechanism that allows rolling back the file system to its predefined factory
image or restoring the factory default parameters of the device. The factory image is kept in a separate sector
on the serial flash in a secure manner and cannot be accessed from the host processor. The following restore
modes are supported:
•
•
•
None – no factory restore settings
Enable restore of factory default parameters
Enable restore of factory image and factory default parameters
The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 110 pins and
toggling the nRESET pin from low to high.
The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The
restore process typically takes about 8 seconds, depending on the attributes of the serial flash vendor.
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9.9 Boot Modes
9.9.1 Boot Mode List
The CC3230x device implements a sense-on-power (SOP) scheme to determine the device operation mode.
SOP values are sensed from the device pin during power up. This encoding determines the boot flow. Before the
device is taken out of reset, the SOP values are copied to a register and used to determine the device operation
mode while powering up. These values determine the boot flow as well as the default mapping (to JTAG, SWD,
UART0) for some of the pins. Table 9-6 lists the pull configurations.
Table 9-6. CC3230x Functional Configurations
BOOT MODE NAME
UARTLOAD
SOP[2]
Pullup
SOP[1]
Pulldown
SOP[0]
Pulldown
SOP MODE
COMMENT
LDfrUART
Factory, lab flash, and SRAM loads
through the UART. The device waits
indefinitely for the UART to load code.
The SOP bits then must be toggled to
configure the device in functional mode.
Also puts JTAG in 4-wire mode.
FUNCTIONAL_2WJ
Pulldown
Pulldown
Pullup
Fn2WJ
Functional development mode. In this
mode, 2-pin SWD is available to the
developer. TMS and TCK are available
for debugger connection.
FUNCTIONAL_4WJ
Pulldown
Pulldown
Pulldown
Fn4WJ
Functional development mode. In this
mode, 4-pin JTAG is available to the
developer. TDI, TMS, TCK, and TDO are
available for debugger connection.
UARTLOAD_FUNCTIONAL_4WJ
Pulldown
Pullup
Pulldown
LDfrUART_Fn4WJ
Supports flash and SRAM load through
UART and functional mode. The MCU
bootloader tries to detect a UART break
on UART receive line. If the break
signal is present, the device enters the
UARTLOAD mode, otherwise, the device
enters the functional mode. TDI, TMS,
TCK, and TDO are available for debugger
connection.
RET_FACTORY_IMAGE
Pulldown
Pullup
Pullup
RetFactDef
When device reset is toggled, the MCU
bootloader kick-starts the procedure to
restore factory default images.
The recommended values of pull down resistors are 100-kΩ for SOP0 and SOP1 and 2.7-kΩ for SOP2. The
application can use SOP2 for other functions after the device has powered up. However, to avoid spurious SOP
values from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The
SOP0 and SOP1 pins are multiplexed with the WLAN analog test pins and are not available for other functions.
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9.10 Hostless Mode
The SimpleLink Wi-Fi CC3230 device incorporates a scripting ability that enables offloading of simple tasks from
the host processor. Using simple and conditional scripts, repetitive tasks can be handled internally, which allows
the host processor to remain in a low-power state. In some cases where the scripter is being used to send
packets, it reduces code footprint and memory consumption. The if-this-then-that style conditioning can include
anything from GPIO toggling to transmitting packets.
The conditional scripting abilities can be divided into conditions and actions. The conditions define when to
trigger actions. Only one action can be defined per condition, but multiple instances of the same condition may
be used, so in effect multiple actions can be defined for a single condition. In total, 16 condition and action
pairs can be defined. The conditions can be simple, or complex using sub-conditions (using a combinatorial AND
condition between them). The actions are divided into two types, those that can occur during runtime and those
that can occur only during the initialization phase.
The following actions can only be performed when triggered by the pre-initialization condition:
• Set roles AP, station, P2P, and Tag modes
• Delete all stored profiles
• Set connection policy
• Hardware GPIO indication allows an I/O to be driven directly from the WLAN core hardware to indicate
internal signaling
The following actions may be activated during runtime:
• Send transceiver packet
• Send UDP packet
• Send TCP packet
• Increment counter increments one of the user counters by 1
• Set counter allows setting a specific value to a counter
• Timer control
• Set GPIO allows GPIO output from the device using the internal networking core
• Enter Hibernate state
Note
Consider the following limitations:
• Timing cannot be ensured when using the network scripter because some variable latency will
apply depending on the utilization of the networking core.
• The scripter is limited to 16 pairs of conditions and reactions.
• Both timers and counters are limited to 8 instances each. Timers are limited to a resolution of 1
second. Counters are 32 bits wide.
• Packet length is limited to the size of one packet and the number of possible packet tokens is
limited to 8.
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10 Applications, Implementation, and Layout
Note
Information in the following Applications section is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI's customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
10.1.1 BLE/2.4 GHz Radio Coexistence
The CC3230x device is designed to support BLE/2.4 GHz radio coexistence. Because WLAN is inherently more
tolerant to time-domain disturbances, the coexistence mechanism gives priority to the Bluetooth® low energy
entity over the WLAN.
The following coexistence modes can be configured by the user:
•
•
•
Off mode or intrinsic mode
– No BLE/2.4 GHz radio coexistence, or no synchronization between WLAN and Bluetooth® low energy—in
case Bluetooth® low energy exists in this mode, collisions can randomly occur.
Time division multiplexing (TDM, single antenna)
– In this mode, (see Figure 10-1) the two entities share the antenna through an RF switch using two GPIOs
(one input and one output from the WLAN perspective).
Time division multiplexing (TDM, dual antenna)
– in this mode, (see Figure 10-2) the two entities have separate antennas, No RF switch is required and
only a single GPIO (on input from the WLAN persective).
Figure 10-1 shows the single antenna implementation of a complete Bluetooth® low energy and WLAN
coexistence network. The Coex switch is controlled by a GPIO signal from the BLE device and a GPIO signal
from the CC3230x device.
BLE / 2.4-GHz
Wi-Fi Antenna
RF_BG
SPDT RF
Switch
and BPF
WLAN
CC3230x
RF
BLE
CCxxxx
CC_COEX_SW_OUT
CC_COEX_BLE_IN
Coex IO
Figure 10-1. Single-Antenna Coexistence Mode Block Diagram
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Figure 10-2 shows the dual antenna implementation of a complete Bluetooth low energy and WLAN coexistence
network. Note in this implementation no Coex switch is required and only a single GPIO from the BLE device to
the CC3230x device is required.
2.4-GHz Wi-Fi
Antenna
RF_BG
2.4-GHz
BPF
BLE
Antenna
2.4-GHz
BPF
WLAN
CC3230x
RF
BLE
CCxxxx
CC_COEX_BLE_IN
Coex IO
Figure 10-2. Dual-Antenna Coexistence Mode Block Diagram
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10.1.2 Antenna Selection
The CC3230x device is designed to also support antenna selection and is controlled from Image Creator. When
enabled, there are 3 options possible options:
•
•
•
ANT 1: When selected, the GPIOs that are defined for antenna selection with set the RF path for antenna 1.
ANT 2: When selected, the GPIOs that are defined for antenna selection will set the RF path for antenna 2.
Autoselect: When selected, during a scan and prior to connecting to an AP, CC3230x device will determine
the best RF path and select the appropriate antenna 5 6. The result is the saved as port of the profile.
Figure 10-3 shows the implementation of a complete Bluetooth® low energy and WLAN coexistence network
with WLAN and antenna selection. The Coex switch is controlled by a GPIO signal from the BLE device and
a GPIO signal from the CC3230x device. The antenna switch is controlled by 2 GPIO lines from the CC3230x
device.
BLE / 2.4-GHz Wi-Fi
Antenna
RF_BG
CC_COEX_SW_OUT
Coex SPDT
RF Switch
WLAN
CC3230x
CC_COEX_BLE_IN
ANTSEL1
BLE
CCxxxx
Coex IO
2.4-GHz
BPF
Antenna
Selection
SPDT RF
Switch
RF
ANTSEL2
BLE / 2.4-GHz Wi-Fi
Antenna
Figure 10-3. Antenna Selection Solution with Coexistence
5
6
76
When selecting Autoselect via the API, a reset is required in order for the CC3230x device to determine the best antenna for use.
Refer to the UniFlash CC3x20, CC3x35 SimpleLink™ Wi-Fi® and Internet-on-a chip™ Solution ImageCreator and Programming Tool
User's Guide for more information.
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Figure 10-4 shows the antenna selection implementation for Wi-Fi, with BLE operating on it's own antenna. Note
in this implementation no Coex switch is required and only a single GPIO from the BLE device to the CC3230x
device is required. The antenna switch is controlled by 2 GPIO lines from the CC3230x device.
2.4-GHz Wi-Fi
Antenna
Antenna
Selection
SPDT RF
Switch
2.4-GHz
BPF
RF_BG
CC_COEX_SW_OUT
WLAN
CC3230x
CC_COEX_BLE_IN
ANTSEL1
BLE
CCxxxx
Coex IO
RF
2.4-GHz Wi-Fi
Antenna
ANTSEL2
BLE Antenna
Figure 10-4. Coexistence Solution with Wi-Fi Antenna Selection and Dedicated BLE Antenna
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10.1.3 Typical Application
Figure 10-5 shows the schematic of the engine area for the CC3230x device in the wide-voltage mode of operation, and the optional RF implementations
with BLE/2.4GHz coexistence. The corresponding Bill-of-Materials show in Table 10-1. For a full operation reference design, see the CC3235x
SimpleLink™ and Internet of Things Hardware Design Files.
Note
The Following guidelines are recommended for implementation of the RF design:
• Ensure an RF path is designed with an impedance of 50 Ω
• Tuning of the antenna impedance π matching network is recommended after manufacturing of the PCB to account for PCB parasitics
• π or L matching and tuning may be required between cascaded passive components on the RF path
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Figure 10-5. CC3230x Engine Area and Optional BLE Coexistence
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Table 10-1. Bill-of-Materials for CC3230x Engine Area and Optional Coexistence
QUANTITY
DESIGNATOR
VALUE
MANUFACTURER
PART NUMBER
DESCRIPTION
1
C1
1 µF
MuRata
GRM155R61A105KE15D
Capacitor, Ceramic, 1 µF,
10 V, ±10%, X5R, 0402
2
C2, C3
100 µF
Taiyo Yuden
LMK325ABJ107MMHT
Capacitor, Ceramic, 100 µF,
10 V, ±20%, X5R, 1210
3
C4, C5, C6
4.7 µF
TDK
C1005X5R0J475M050BC
Capacitor, Ceramic, 4.7 µF,
6.3 V, ±20%, X5R, 0402
10
C7, C8, C9, C11, C12,
C13, C18, C19, C21, C22
0.1 µF
TDK
C1005X5R1A104K050BA
Capacitor, Ceramic, 0.1 µF,
10 V, ±10%, X5R, 0402
3
C10, C17, C20
10 µF
MuRata
GRM188R60J106ME47D
Capacitor, Ceramic, 10 µF,
6.3 V, ±20%, X5R, 0603
2
C14, C15
22 µF
TDK
C1608X5R0G226M080AA
Capacitor, Ceramic, 22 µF,
4 V, ±20%, X5R, 0603
1
C16
1 µF
TDK
C1005X5R1A105K050BB
Capacitor, Ceramic, 1 µF,
10 V, ±10%, X5R, 0402
2
C23, C24
10 pF
MuRata
GRM1555C1H100JA01D
Capacitor, Ceramic, 10 pF,
50 V, ±5%, C0G/NP0, 0402
2
C25, C26
6.2 pF
MuRata
GRM1555C1H6R2CA01D
Capacitor, Ceramic, 6.2 pF,
50 V, ±5%, C0G/NP0, 0402
1
C27
0.5 pF
MuRata
GRM1555C1HR50BA01D
Capacitor, Ceramic, 0.5 pF,
50 V, ±20%, C0G/NP0, 0402
3
C28(3), C29(3), C30(3)
68 pF
MuRata
2
C31(3), C32(3)
100 pF
1
E1
1
GRM0335C1H680JA1D
CAP, CERM, 68 pF, 50 V,
+/- 5%, C0G/NP0, 0201
Yageo
CC0201JRNPO8BN101
CAP, CERM, 100 pF, 25 V,
+/- 5%, C0G/NP0, 0201
2.45-GHz
Antenna
Taiyo Yuden
AH316M245001-T
ANT Bluetooth W-LAN
Zigbee®, SMD
FL1
1.02 dB
TDK
DEA202450BT-1294C1-H
Multilayer Chip Band Pass Filter
For 2.4 GHz W-LAN/Bluetooth, SMD
1
L1
3.3 nH
MuRata
LQG15HS3N3S02D
Inductor, Multilayer, Air Core,
3.3 nH, 0.3 A, 0.17 ohm, SMD
2
L2, L4
2.2 µH
MuRata
LQM2HPN2R2MG0L
Inductor, Multilayer, Ferrite,
2.2 µH, 1.3 A, 0.08 ohm, SMD
1
L3
1 µH
MuRata
LQM2HPN1R0MG0L
Inductor, Multilayer, Ferrite,
1 µH, 1.6 A, 0.055 ohm, SMD
1
L5(1)
10 µH
Taiyo Yuden
CBC2518T100M
Inductor, Wirewound, Ceramic,
10 µH, 0.48 A, 0.36 ohm, SMD
1
R1
10 k
Vishay-Dale
CRCW040210K0JNED
Resistor, 10 k, 5%, 0.063 W, 0402
80
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Table 10-1. Bill-of-Materials for CC3230x Engine Area and Optional Coexistence (continued)
QUANTITY
DESIGNATOR
VALUE
MANUFACTURER
PART NUMBER
DESCRIPTION
6
R2, R3, R4, R5, R9(3),
R10(3)
100 k
Vishay-Dale
CRCW0402100KJNED
Resistor, 100 k, 5%, 0.063 W, 0402
1
R6
2.7 k
Vishay-Dale
CRCW04022K70JNED
Resistor, 2.7 k, 5%, 0.063 W, 0402
1
R7
270
Vishay-Dale
CRCW0402270RJNED
Resistor, 270, 5%, 0.063 W, 0402
1
R8(2)
0
Panasonic
ERJ-2GE0R00X
Resistor, 0, 5% 0.063W, 0402
1
U1
MX25R
Macronix International
Co., LTD
MX25R3235FM1IL0
Ultra-Low Power, 32-Mbit [x 1/x 2/x 4]
CMOS MXSMIO (Serial Multi I/O)
Flash Memory, SOP-8
1
U2
CC3230
Texas Instruments
CC3230SF12RGK
SimpleLink™ Wi-Fi® and internet-of-things
Solution, a Single-Chip Wireless
MCU, RGK0064B
1
U3(3)
SPDT
Switch
Richwave
RTC6608OSP
0.03 GHz-6 GHz SPDT Switch
1
Y1
Crystal
Abracon Corportation
ABS07-32.768KHZ-9-T
Crystal, 32.768 KHz, 9PF, SMD
1
Y2
Crystal
Epson
Q24FA20H0039600
Crystal, 40 MHz, 8pF, SMD
(1)
(2)
(3)
For the CC3230SF device, L5 is populated. For the CC3230S device, L5 is not populated.
For the CC3230SF device, R8 is not populated. For the CC3230S device if R8 is populated, Pin 45 can be used as GPIO_31.
If the BLE/2.4 GHz Coexistence features is not used, these components are not required.
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10.2 PCB Layout Guidelines
This section details the PCB guidelines to speed up the PCB design using the CC3230x VQFN device. Follow
these guidelines ensures that the design will minimize the risk with regulatory certifications including FCC,
ETSI, and CE. For more information, see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout
Guidelines.
10.2.1 General PCB Guidelines
Use the following PCB guidelines:
•
•
•
•
Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended layers for
signals and ground.
Ensure that the VQFN PCB footprint follows the information in .
Ensure that the VQFN PCB GND and solder paste follow the recommendations provided in CC3120 and
CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.
Decoupling capacitors must be as close as possible to the VQFN device.
10.2.2 Power Layout and Routing
Three critical DC/DC converters must be considered for the CC3230x device.
•
•
•
Analog DC/DC converter
PA DC/DC converter
Digital DC/DC converter
Each converter requires an external inductor and capacitor that must be laid out with care. DC current loops are
formed when laying out the power components.
10.2.2.1 Design Considerations
The following design guidelines must be followed when laying out the CC3230x device:
•
•
•
•
•
•
•
82
Ground returns of the input decoupling capacitors (C11, C13, and C19) should be routed on Layer 2 using
thick traces to isolate the RF ground from the noisy supply ground. This step is also required to meet the
IEEE spectral mask specifications.
Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power
amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).
Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
Place all decoupling capacitors as close to the respective pins as possible.
Power budget—the CC3230x device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, for
24 ms during the calibration cycle.
Ensure the power supply is designed to source this current without any issues. The complete calibration (TX
and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
The CC3230x device contains many high-current input pins. Ensure the trace feeding these pins can handle
the following currents:
– VIN_DCDC_PA input (pin 39) maximum 1 A
– VIN_DCDC_ANA input (pin 37) maximum 600 mA
– VIN_DCDC_DIG input (pin 44) maximum 500 mA
– DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum 1 A
– DCDC_PA_OUT output node (pin 42) maximum 1 A
– DCDC_ANA_SW switching node (pin 38) maximum 600 mA
– DCDC_DIG_SW switching node (pin 43) maximum 500 mA
– VDD_PA_IN supply (pin 33) maximum 500 mA
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Figure 10-6. Ground Returns for Input Capacitors
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10.2.3 Clock Interface Guidelines
The following guidelines are for the slow clock:
•
•
•
The 32.768-kHz crystal must be placed close to the VQFN package.
Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance within
±150 ppm.
The ground plane on layer two is solid below the trace lanes, and there is ground around these traces on the
top layer.
The following guidelines are for the fast clock:
•
•
•
•
•
•
•
The 40-MHz crystal must be placed close to the VQFN package.
Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance within
±10 ppm at room temperature. The total frequency across parts, temperature, and with aging must be ±25
ppm to meet the WLAN specification.
To avoid noise degradation, ensure that no high-frequency lines are routed close to the routing of the crystal
pins.
Ensure that crystal tuning capacitors are close to the crystal pads.
Both traces (XTAL_N and XTAL_P) should be as close as possible to parallel and approximately the same
length.
The ground plane on layer two is solid below the trace lines, and there should be ground around these traces
on the top layer.
For frequency tuning, see CC31xx & CC32xx Frequency Tuning.
10.2.4 Digital Input and Output Guidelines
The following guidelines are for the digital I/Os:
•
•
•
•
•
•
•
84
Route SPI and UART lines away from any RF traces.
Keep the length of the high-speed lines as short as possible to avoid transmission line effects.
Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects (required if
the traces cannot be kept short). Place the resistor at the source end closer to the device that is driving the
signal.
Add a series-terminating resistor for each high-speed line (for example, SPI_CLK or SPI_DATA) to match
the driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line
impedance.
Route high-speed lines with a continuous ground reference plane below it to offer good impedance
throughout. This routing also helps shield the trace against EMI.
Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple locations,
use a separate line driver for each line.
If the lines are longer compared to the rise time, add series-terminating resistors near the driver for each
high-speed line to match the driver impedance to the line. Typical terminating-resistor values range from 27 to
36 Ω for a 50-Ω line impedance.
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10.2.5 RF Interface Guidelines
The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific antenna
design guides (including placement of the antenna). Also see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT
Solution Layout Guidelines for general antenna guidelines.
•
•
•
•
•
•
•
•
•
•
Ensure that the antenna is matched for 50-Ω. A π-matching network is recommended. Ensure that the π pad
is available for tuning the matching network after PCB manufacture.
Ensure that the area underneath the BPFs pads have a solid plane on layer 2 and that the minimum filter
requirements are met.
Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.
The RF trace bends must be made with gradual curves. Avoid 90-degree bends.
The RF traces must not have sharp corners.
There must be no traces or ground under the antenna section.
The RF traces must have via stitching on the ground plane beside the RF trace on both sides.
For optimal antenna performance, ensure adequate ground plane around the antenna on all layers.
Ensure RF connectors for conducted testing are isolated from the top layer ground using vias.
Maintain a controlled pad to trace shapes using filleted edges if necessary to avoid mismatch.
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11 Device and Documentation Support
11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Tools and Software
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed in this section.
For the most up-to-date list of development tools and software, see the CC3230S Design & development page.
Users can also click the "Alert Me" button on the top right corner of the CC3230S Design & development page to
stay informed about updates related to the CC3230x device.
Development Tools
Pin Mux Tool
The supported devices are: CC3200, CC3220x, CC3230x, and CC3235x.
The Pin Mux Tool is a software tool that provides a graphical user interface (GUI)
for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell
characteristics for MPUs from TI. Results are output as C header/code files that can
be imported into software development kits (SDKs) or used to configure customers'
custom software. Version 3 of the Pin Mux Tool adds the capability of automatically
selecting a mux configuration that satisfies the entered requirements.
SimpleLink™ Wi-Fi®
Starter Pro
The supported devices are: CC3100, CC3200, CC3120R, CC3220x, CC3130,
CC3135, CC3230x and CC3235x.
The SimpleLink™ Wi-Fi® Starter Pro mobile App is a new mobile application for
SimpleLink™ provisioning. The app goes along with the embedded provisioning
library and example that runs on the device side (see SimpleLink™ Wi-Fi®
SDK plugin and TI SimpleLink™ CC32XX Software Development Kit (SDK)). The
new provisioning release is a TI recommendation for Wi-Fi® provisioning using
SimpleLink™ Wi-Fi® products. The provisioning release implements advanced AP
mode and SmartConfig™ technology provisioning with feedback and fallback options
to ensure successful process has been accomplished. Customers can use both
embedded library and the mobile library for integration to their end products.
SimpleLink™ CC32XX
Software Development
Kit (SDK)
Uniflash Standalone
Flash Tool for TI
Microcontrollers (MCU),
Sitara Processors &
SimpleLink Devices
86
The CC3230x devices are supported.
The SimpleLink™ CC32XX SDK contains drivers for the CC3230 programmable
MCU, more than 30 sample applications, and documentation needed to use the
solution. It also contains the flash programmer, a command line tool for flashing
software, configuring network and software parameters (SSID, access point channel,
network profile, BS NIEW), system files, and user files (certificates, web pages, and
more). This SDK can be used with TI’s SimpleLink™ Wi-Fi® CC3230 LaunchPad™
development kits.
The supported devices are: CC3120R, CC3220x, CC3130, CC3135, CC3230x and
CC3235x.
CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs
and on-board flash memory for Sitara™ processors. Uniflash has a GUI, command
line, and scripting interface. CCS Uniflash is available free of charge.
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SimpleLink™ Wi-Fi®
Radio Testing Tool
The supported devices are: CC3100, CC3200, CC3120R, CC3220, CC3130, CC3135,
CC3230x and CC3235x.
The SimpleLink™ Wi-Fi® Radio Testing Tool is a Windows-based software tool for RF
evaluation and testing of SimpleLink™ Wi-Fi® CC3x20 and CC3x3x designs during
development and certification. The tool enables low-level radio testing capabilities by
manually setting the radio into transmit or receive modes. Using the tool requires
familiarity and knowledge of radio circuit theory and radio test methods.
Created for the internet-of-things (IoT), the SimpleLink™ Wi-Fi® CC31xx and CC32xx
family of devices include on-chip Wi-Fi®, Internet, and robust security protocols with no
prior Wi-Fi® experience needed for faster development. For more information on these
devices, visit SimpleLink™ Wi-Fi® family, Internet-on-a chip™ solutions.
UniFlash Standalone
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs
Flash Tool for TI
and on-board flash memory for Sitara™ processors. UniFlash has a GUI, command
Microcontrollers (MCU), line, and scripting interface. CCS UniFlash is available free of charge.
Sitara™ Processors
and SimpleLink™
Devices
TI Reference Designs
Find reference designs leveraging the best in TI technology – from analog and power management to embedded
processors. All designs include a schematic, test data and design files.
11.3 Firmware Updates
TI updates features in the service pack for this module with no published schedule. Due to the ongoing changes,
TI recommends that the user has the latest service pack in their module for production.
To stay informed, click the SDK “Alert me” button the top right corner of the product page, or visit SimpleLink™
CC32XX SDK.
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11.4 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the
CC3230x device and support tools (see Figure 11-1).
X
CC
3
2
3
0
x
xx
xxx
x
PREFIX
X = Preproduction device
Null = Production device
PACKAGING
R = large reel
DEVICE FAMILY
CC = Wireless Connectivity
PACKAGE
RGK = 9-mm × 9-mm VQFN
SERIES NUMBER
MEMORY SIZE
3 = Wi-Fi Centric
M2 = 256KB RAM
12 = 1MB Flash and 256KB RAM
MCU / HOST
1 = No MCU
2 = MCU
DEVICE GENERATION
0 = Gen 1
2 = Gen 2
3 = Gen 3
DEVICE VARIANTS
S = Secured
SF = Secured Flash
DUAL BAND
0 = 2.4-GHz only
5 = 2.4-GHz and 5-GHz supported
Figure 11-1. CC3230x Device Nomenclature
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11.5 Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for example, CC3230S). In the upper right corner, click the "Alert me" button. This registers
you to receive a weekly digest of product information that has changed (if any). For change details, check
the revision history of any revised document. The current documentation that describes the processor, related
peripherals, and other technical collateral follows.
The following documents provide support for the CC3230 device.
Application Reports
CC3135 and CC3235 SimpleLink™ CC3135 and CC3235 SimpleLink Wi-Fi Embedded Programming User
Wi-Fi® Embedded Programming Guide
User Guide
SimpleLink™ CC3135, CC3235 Wi- This application report describes the best practices for power
Fi® Internet-on-a chip™ Networking management and extended battery life for embedded low-power Wi-Fi
Sub-System Power Management
devices such as the SimpleLink Wi-Fi Internet-on-a chip solution from
Texas Instruments.
SimpleLink™ CC31xx, CC32xx Wi- The SimpleLink Wi-Fi CC31xx and CC32xx Internet-on-a chip family of
Fi® Internet-on-a chip™ Solution devices from Texas Instruments offer a wide range of built-in security
Built-In Security Features
features to help developers address a variety of security needs, which
is achieved without any processing burden on the main microcontroller
(MCU). This document describes these security-related features and
provides recommendations for leveraging each in the context of practical
system implementation.
SimpleLink™ CC3135, CC3235 Wi- This document describes the OTA library for the SimpleLink Wi-Fi
Fi® and Internet-of-Things Over-the- CC3x35 family of devices from Texas Instruments and explains how to
Air Update
prepare a new cloud-ready update to be downloaded by the OTA library.
SimpleLink™ CC3135, CC3235 Wi- This guide describes the provisioning process, which provides the
Fi® Internet-on-a chip™ Solution SimpleLink Wi-Fi device with the information (network name, password,
Device Provisioning
and so forth) needed to connect to a wireless network.
Transfer of TI's Wi-Fi® Alliance This document explains how to employ the Wi-Fi® Alliance (WFA)
Certifications to Products Based on derivative certification transfer policy to transfer a WFA certification,
SimpleLink™
already obtained by Texas Instruments, to a system you have developed.
Using Serial Flash on SimpleLink™ This application note is divided into two parts. The first part provides
CC3135 and CC3235 Wi-Fi® and important guidelines and best- practice design techniques to consider
Internet-of-Things Devices
when choosing and embedding a serial Flash paired with the CC3135
and CC3235 (CC3x35) devices. The second part describes the file
system, along with guidelines and considerations for system designers
working with the CC3x35 devices.
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User's Guides
SimpleLink™ Wi-Fi® and
Internet-of-Things CC31xx
and
CC32xx
Network
Processor
This document provides software (SW) programmers with all of the required
knowledge for working with the networking subsystem of the SimpleLink WiFi devices. This guide provides basic guidelines for writing robust, optimized
networking host applications, and describes the capabilities of the networking
subsystem. The guide contains some example code snapshots, to give users an
idea of how to work with the host driver. More comprehensive code examples can
be found in the formal software development kit (SDK). This guide does not provide
a detailed description of the host driver APIs.
SimpleLink™
Wi-Fi®
CC3135
and
CC3235
and IoT Solution Layout
Guidelines
This document provides the design guidelines of the 4-layer PCB used for the
CC3135 and CC3235 SimpleLink Wi-Fi family of devices from Texas Instruments.
The CC3135 and CC3235 devices are easy to lay out and are available in quad flat
no-leads (QFNS) packages. When designing the board, follow the suggestions in
this document to optimize performance of the board.
SimpleLink™
CC3235 The CC3235 SimpleLink LaunchPad Development Kit (LAUNCHXL-CC3235)
Wi-Fi®
LaunchPad™ is a cost-conscious evaluation platform for Arm Cortex-M4-based MCUs. The
Development Kit Hardware LaunchPad design highlights the CC3230 Internet-on-a chip solution and Wi-Fi
capabilities. The CC3235 LaunchPad also features temperature and accelerometer
sensors, programmable user buttons, three LEDs for custom applications,
and onboard emulation for debugging. The stackable headers of the CC3235
LaunchPad XL interface demonstrate how easy it is to expand the functionality
of the LaunchPad when interfacing with other peripherals on many existing
BoosterPack™ Plug-in Module add-on boards, such as graphical displays, audio
codecs, antenna selection, environmental sensing, and more.
SimpleLink™
Wi-Fi®
and Internet-on-a chip™
CC3135
and
CC3235
Solution Radio Tool
The Radio Tool serves as a control panel for direct access to the radio, and can
be used for both the radio frequency (RF) evaluation and for certification purposes.
This guide describes how to have the tool work seamlessly on Texas Instruments
evaluation platforms such as the BoosterPack™ plus FTDI emulation board for
CC3230 devices, and the LaunchPad™ for CC3230 devices.
SimpleLink™
Wi-Fi® This guide describes TI’s SimpleLink Wi-Fi provisioning solution for mobile
CC3135
and
CC3235 applications, specifically on the usage of the Android™ and IOS® building blocks
Provisioning for Mobile for UI requirements, networking, and provisioning APIs required for building the
Applications
mobile application.
More Literature
CC3235 SimpleLink™ Wi-Fi® and Internet This technical reference manual details the modules and peripherals
of Things Technical Reference Manual
of the CC3230 SimpleLink™ Wi-Fi® MCU. Each description
presents the module or peripheral in a general sense. Not all
features and functions of all modules or peripherals may be present
on all devices. Pin functions, internal signal connections, and
operational parameters differ from device to device. The user should
consult the device-specific data sheet for these details.
CC3x35 SimpleLink™ Wi-Fi® Hardware
Design Checklist
CC3235S/CC3235SF SimpleLink™ WiFi® LaunchPad™ Design Files
11.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
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Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.7 Trademarks
WPA™, WPA2™, WPA3™, and are trademarks of Wi-Fi Alliance.
Internet-on-a chip™, LaunchPad™, BoosterPack™, SmartConfig™, Sitara™, TI E2E™ are trademarks of Texas
Instruments.
Macrocell™ is a trademark of Kappa Global Inc.
Android™ is a trademark of Google LLC.
Wi-Fi CERTIFIED®, Wi-Fi Alliance®, Wi-Fi®, and Wi-Fi Direct® are registered trademarks of Wi-Fi Alliance.
Arm®, Cortex®, and Thumb® are registered trademarks of Arm Limited.
is a registered trademark of Bluetooth SIG Inc.
Zigbee® is a registered trademark of Zigbee Alliance.
IOS® is a registered trademark of Cisco.
All trademarks are the property of their respective owners.
11.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.9 Glossary
TI Glossary
92
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Package Option Addendum
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SWRS226B – FEBRUARY 2020 – REVISED MAY 2021
12.1.1 Packaging Information
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan (2)
Lead/Ball
Finish(3)
MSL Peak Temp (4)
Op Temp (°C)
Device Marking(5) (6)
CC3230SM2RGKR
PREVIEW
VQFN
RGK
64
2500
Green (RoHS &
no Sb/Br)
CU NIPDAU | CU
NIPDAUAG
Level-3-260C-168 HR
–40 to 85
CC3230SM2
CC3230SF12RGKR
PREVIEW
VQFN
RGK
64
2500
Green (RoHS &
no Sb/Br)
CU NIPDAU | CU
NIPDAUAG
Level-3-260C-168 HR
–40 to 85
CC3230SF12
(1)
(2)
(3)
(4)
(5)
(6)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD: Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material).
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided
by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider
certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
94
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SWRS226B – FEBRUARY 2020 – REVISED MAY 2021
12.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
CC3230SM2RGKR
VQFN
RGK
64
2500
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
CC3230SF12RGKR
VQFN
RGK
64
2500
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
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SWRS226B – FEBRUARY 2020 – REVISED MAY 2021
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
96
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC3230SM2RGKR
VQFN
RGK
64
2500
367.0
367.0
38.0
CC3230SF12RGKR
VQFN
RGK
64
2500
367.0
367.0
38.0
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CC3230SF12RGKR
ACTIVE
VQFN
RGK
64
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC3230SF
12
CC3230SM2RGKR
ACTIVE
VQFN
RGK
64
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC3230S
M2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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