SN74CBTLV3861-Q1
LOW-VOLTAGE 10-BIT FET BUS SWITCH
SCDS160B − MARCH 2004 − REVISED JANUARY 2008
D
D
D
D
D
D
DW OR PW PACKAGE
(TOP VIEW)
Qualified for Automotive Applications
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
Ioff Supports Partial-Power-Down Mode
Operation
Flowthrough Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
description/ordering information
The SN74CBTLV3861 provides ten bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
NC − No internal connection
The device is organized as one 10-bit bus switch.
When output enable (OE) is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high,
the switch is open, and the high-impedance state exists between the two ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION†
−40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − DW
Tape and reel
CCBTLV3861IDWRQ1
CL3861Q1
TSSOP − PW
Tape and reel
CCBTLV3861IPWRQ1
CL3861Q1
†
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
1
SN74CBTLV3861-Q1
LOW-VOLTAGE 10-BIT FET BUS SWITCH
SCDS160B − MARCH 2004 − REVISED JANUARY 2008
logic diagram (positive logic)
22
2
A1
B1
SW
11
13
A10
SW
B10
23
OE
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SN74CBTLV3861-Q1
LOW-VOLTAGE 10-BIT FET BUS SWITCH
SCDS160B − MARCH 2004 − REVISED JANUARY 2008
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High level control input voltage
High-level
VIL
Low level control input voltage
Low-level
TA
Operating free-air temperature
MIN
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
V
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
−40
UNIT
85
V
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range TA = −405C to
855C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VIK
VCC = 3 V,
II = −18 mA
−1.2
V
II
VCC = 3.6 V,
VI = VCC or GND
±1
μA
Ioff
VCC = 0,
VI or VO = 0 to 3.6 V
10
μA
10
μA
300
μA
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
ΔICC‡
Control inputs
VCC = 3.6 V,
One input at 3 V,
Other inputs at VCC or GND
Ci
Control inputs
VI = 3 V or 0
Cio(OFF)
3
VO = 3 V or 0,
OE = VCC
3V
VCC = 2
2.3
V,
TYP at VCC = 2
2.5
5V
ron§
II = 64 mA
VI = 0
VI = 1.7 V,
VI = 0
VCC = 3 V
pF
5
VI = 2.4 V,
pF
5
8
II = 24 mA
5
8
II = 15 mA
27
40
II = 64 mA
5
7
II = 24 mA
5
7
II = 15 mA
10
15
Ω
†
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
‡
switching characteristics over recommended operating free-air temperature range TA = −405C to
855C (unless otherwise noted) (see Figure 1)
TO
(OUTPUT)
tpd¶
A or B
B or A
ten
OE
A or B
2.1
5.5
OE
A or B
1.7
5.5
tdis
¶
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
PARAMETER
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
UNIT
MAX
0.25
ns
2.1
4.9
ns
2.5
5.8
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
3
SN74CBTLV3861-Q1
LOW-VOLTAGE 10-BIT FET BUS SWITCH
SCDS160B − MARCH 2004 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
2 × VCC
RL
From Output
Under Test
S1
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
VΔ
2.5 V ± 0.2 V
3.3 V ± 0.3 V
30 pF
50 pF
500 Ω
500 Ω
0.15 V
0.3 V
VCC
Timing Input
VCC/2
0V
tw
tsu
th
VCC
VCC/2
Input
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPLH
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
Output
VCC/2
VOL
tPHL
tPLH
Output
Waveform 2
S1 at GND
(see Note B)
VOH
Output
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
VOL + VΔ
VOL
tPHZ
VCC/2
VOH − VΔ
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CCBTLV3861IPWRG4Q1
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL3861Q1
CCBTLV3861IPWRQ1
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL3861Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
