CD4027B
SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
CD4027B CMOS Dual J-K Flip Flop
1 Features
3 Description
•
•
CD4027B is a single monolithic chip integrated circuit
containing two identical complementary-symmetry J-K
flip flops. Each flip-flop has provisions for individual
J, K, Set, Reset, and Clock input signals. Buffered
Q and Q signals are provided as outputs. This inputoutput arrangement provides for compatibile operation
with the RCA-CD4013B dual D-type flip-flop.
•
•
•
•
•
•
•
Set-reset capability
Static flip-flop operation – retains state indefinitely
with clock level either high or low
Medium speed operation – 16 MHz (typical) clock
toggle rate at 10 V
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 μA at 18 V over full
package-temperature range; 100 nA at 18 V and
25°C
Noise margin (over full package-temperature
range):
– 1 V at VDD = 5 V
– 2 V at VDD = 10 V
– 2.5 V at VDD = 15 V
5 V, 10 V, and 15 V parametric ratings
Meets all requirements of JEDEC tentative
standard No. 138, standard specifications for
description of 'B' series CMOS devices
2 Applications
•
Registers, counters, control circuits
The CD4027B is useful in performing control, register,
and toggle functions. Logic levels present at the J and
K inputs along with internal self-steering control the
state of each flip-flop; changes in the flip-flop state are
synchronous with the postitive-going transition of the
clock pulse. Set and reset functions are independent
of the clock and are initiated when a high level signal
is present at either the Set or Reset input.
The CD4027B types are supplied in 16-lead hermetic
dual-in-line ceramic packages (F3A suffix), 16-lead
dual-in-line plastic packages (E suffice), 16-lead
small-outline packages (M, M96, MT, and NSR
suffixes), and 16-lead thin shrink small-outline
packages (PW and PWR suffixes).
One of Two J-K Flip-Flops
SETx
C
Qx
Jx
C
C
C
C
C
Kx
C
Qx
C
RESETx
xCL K
C
C
Figure 3-1. Logic Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4027B
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Recommended Operating Conditions.........................4
6.3 Static Electrical Characteristics...................................5
6.4 Dynamic Electrical Characteristics..............................5
6.5 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Functional Block Diagram........................................... 9
8.2 Device Functional Modes(1) ....................................... 9
9 Device and Documentation Support............................10
9.1 Receiving Notification of Documentation Updates....10
9.2 Support Resources................................................... 10
9.3 Trademarks............................................................... 10
9.4 Electrostatic Discharge Caution................................10
9.5 Glossary....................................................................10
10 Mechanical, Packaging, and Orderable
Information.................................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2003) to Revision D (July 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
2
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
5 Pin Configuration and Functions
Q2
1
16
VDD
Q2
2
3
15
14
Q1
CLOCK2
RESET2
4
13
CLOCK1
K2
5
12
RESET1
J2
6
11
K1
SET2
7
8
10
J1
SET1
VSS
9
Q1
Figure 5-1. Terminal Assignment
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLOCK1
13
I
Clock input for channel 1
CLOCK2
3
I
Clock input for channel 2
J1
10
I
J input for channel 1
J2
6
I
J input for channel 2
K1
11
I
K input for channel 1
K2
5
I
K input for channel 2
Q1
15
O
Q output for channel 1
Q1
14
O
Inverted Q output for channel 1
Q2
1
O
Q output for channel 2
Q2
2
O
Inverted Q output for channel 2
RESET1
12
I
Reset input for channel 1
RESET2
4
I
Reset input for channel 2
SET1
9
I
Set input for channel 1
SET2
7
I
Set input for channel 2
VDD
16
—
Supply
VSS
8
—
Ground
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
6 Specifications
6.1 Absolute Maximum Ratings
VDD
DC Supply Voltage Range
All Inputs
Input Voltage Range
Any One
Input
DC Input Current
PD
Power Dissipation per Package
Voltages referenced to VSS Terminal
Operating- Temperature Range
Tstg
Storage temperature
Lead Temperatur (During Soldering)
MAX
UNIT
20
V
–0.5
VDD + 0.5
For TA = +100°C to +125°C
V
±10
mA
500
mW
200
mW
100
mW
–55
125
°C
–65
150
°C
265
°C
For TA = –55°C to + 100°C
Device Dissipation per Output Transistor
TA
MIN
–0.5
12mW/°C
For TA = Full package-temperature range
(all package types)
At distance 1/16 ± 1/32 inch
(1.59 ± 0.79mm) from case for 10s max
6.2 Recommended Operating Conditions
at TA = 25℃, except as noted. For maximum reliability, nominal operating conditions should be selected so that operation is
always within the following ranges:
VDD
(V)
CHARACTERISTIC
Supply-Voltage Range
tS
For TA = Full Package
Temperature Range
Data Setup Time
tW
Clock Pulse Width
LIMITS
ALL PACKAGES
MIN
MAX
3
18
5
200
10
75
15
50
5
140
10
60
15
40
5
fCL
trCL,
tfCL(1)
Clock Rise or Fall Time
tW
Set or Reset Pulse Width
(1)
4
Clock Input Frequency (Toggle Mode)
10
UNIT
V
ns
ns
3.5
dc
8
15
12
5
45
10
5
15
2
5
180
10
80
15
50
MHz
μs
ns
If more than one unite is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed
propagation delay time at 15 pF and the transitiopn time of the output driving stage for the estimated capacitive load.
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
6.3 Static Electrical Characteristics
TEST CONDITIONS
CHARACTERISTIC
VO
(V)
VIN
(V)
LIMITS AT INDICATED TEMPERATURES (°C)
VDD
(V)
–55
–40
+85
+125
UNIT
+25
MIN
TYP
MAX
Quiescent
0, 5
5
1
1
30
30
0.02
1
Device
0, 10
10
2
2
60
60
0.02
2
Current
0, 15
15
4
4
120
120
0.02
4
IDD Max.
0, 20
20
20
20
600
600
0.04
20
Output Low (Sink)
0.4
0, 5
5
0.64
0.61
0.42
0.36
0.51
1
Current
0.5
0, 10
10
1.6
1.5
1.1
0.9
1.3
2.6
IOL Min.
1.5
0, 15
15
4.2
4
2.8
2.4
3.4
6.8
Output High
4.6
0, 5
5
–0.64
–0.61
–0.42
–0.36
–0.51
–1
mA
(Source)
2.5
0, 5
5
–2
–1.8
–1.3
–1.15
–1.6
–3.2
Current
9.5
0, 10
10
–1.6
–1.5
–1.1
–0.9
–1.3
–2.6
IOH Min.
13.5
0, 15
15
– 4.2
–4
–2.8
–2.4
–3.4
–6.8
0, 5
5
0.05
0
0.05
Low-Level
0, 10
10
0.05
0
0.05
VOL Max.
0, 15
15
0.05
0
0.05
Output Voltage
Output Voltage
0, 5
5
4.95
4.95
5
High-Level
0, 10
10
9.95
9.95
10
0, 15
14.95
15
VOH Min.
Input Low
15
14.95
0,5, 4.5
5
1.5
mA
1.5
Voltage
1, 9
10
3
3
1.5, 13.5
15
4
4
Input High
0.5, 4.5
5
3.5
1, 9
10
7
VIH Min.
1.5, 13.5
Input Current, VIH Max.
15
0, 18
±0.1
±0.1
V
3.5
V
7
11
18
V
V
VIL Max.
Voltage
μa
11
±1
±10–5
±1
±0.1
μA
6.4 Dynamic Electrical Characteristics
at TA = 25°C; Input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ
CHARACTERISTIC
LIMITS
VDD
(V)
UNIT
ALL PACKAGES
MIN
TYP
MAX
Propagation Delay Time
5
150
300
Clock to Q or Q Outputs
10
65
130
tPHL, tPLH
15
45
90
5
150
300
10
65
130
15
45
90
Set to Q or Reset to Q, tPLH
Set to Q or Reset to Q, tPHL
Transition Time
tTHL, tTLH
5
200
400
10
85
170
15
60
120
5
100
200
10
50
100
15
40
80
ns
ns
ns
ns
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
6.4 Dynamic Electrical Characteristics (continued)
at TA = 25°C; Input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ
CHARACTERISTIC
ALL PACKAGES
MIN
TYP
3.5
7
10
8
16
15
12
24
UNIT
MAX
Maximum Clock Input
5
Frequency (Toggle Mode)(1)
fCL
5
70
140
Minimum Clock Pulse Width, tW
10
30
60
15
20
40
5
90
180
10
40
80
15
25
50
Minimum Set or Reset Pulse Width, tW
Minimum Data Setup Time, tS
Clock Input Rise or Fall Time
trCL, tfCL
(1)
MHz
5
100
200
10
35
75
15
25
50
5
45
10
5
15
2
Input Capacitance, CI
6
LIMITS
VDD
(V)
5
7.5
ns
ns
μs
pF
Input tr, tf = 5 ns
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6.5 Typical Characteristics
Figure 6-1. Typical Output Low (Sink) Current Characteristics
Figure 6-2. Typical Output High (Source) Current
Characteristics
Figure 6-3. Typical Power Dissipation vs Frequency
Figure 6-4. Typical Propagation Delay Time vs Load
Capacitance (Clock or Set to Q, Clock or Reset to Q)
Figure 6-5. Typical Maximum Clock Frequency vs Supply Voltage (Toggle Mode)
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
7 Parameter Measurement Information
VDD
VDD
Inputs
Outputs
Inputs
VDD
VIH
I
+
VSS
DVM
VIL
-
VSS
VSS
Figure 7-1. Input Current Test Circuit
Figure 7-2. Input-Voltage Test Circuit
VDD
VDD
Inputs
VSS
IDD
VSS
Figure 7-3. Quiescent Device Current Test Circuit
8
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
8 Detailed Description
8.1 Functional Block Diagram
One of Two J-K Flip-Flops
SETx
C
Qx
Jx
C
C
C
C
C
Kx
C
Qx
C
RESETx
xCL K
C
C
8.2 Device Functional Modes(1)
PRESENT STATE
INPUTS
(1)
(2)
OUTPUT
NEXT STATE
CL(2)
OUTPUTS
J
K
S
R
O
_/ ̅
O
O
I
X
O
O
O
_/ ̅
I
O
X
O
O
O
I
_/ ̅
I
O
O
X
O
O
O
_/ ̅
O
I
X
I
O
O
I
_/ ̅
O
I
X
X
O
O
X
̅ \_
No change
No change
X
X
I
O
X
X
I
O
X
X
O
I
X
X
O
I
X
X
I
I
X
X
I
I
Logic I = High Level, Logic O = Low Level, X = Do not care
Level change
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SCHS032D – NOVEMBER 1998 – REVISED JULY 2021
9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD4027BE
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD4027BE
Samples
CD4027BEE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD4027BE
Samples
CD4027BF
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD4027BF
Samples
CD4027BF3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD4027BF3A
Samples
CD4027BM
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4027BM
Samples
CD4027BM96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4027BM
Samples
CD4027BM96E4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4027BM
Samples
CD4027BMT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4027BM
Samples
CD4027BNSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4027B
Samples
CD4027BPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM027B
Samples
CD4027BPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM027B
Samples
JM38510/05152BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
05152BEA
Samples
M38510/05152BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
05152BEA
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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14-Oct-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of