CD4541BPW

[ /Title (CD45 41B) /Subject (CMO S Programmable Timer High Voltage Types (20V Rating)) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil, military, mil CD4541B CMOS Programmable Timer High Voltage Types (20V Rating) Data sheet acquired from Harris Semiconductor SCHS085E – Revised September 2003 Features The output from this timer is the Q or Q output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B (see Frequency Select Table). • Low Symmetrical Output Resistance, Typically 100Ω at VDD = 15V The output is available in either of two modes selectable via the MODE input, pin 10 (see Truth Table). When this MODE input is a logic “1”, the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2N. With the MODE input set to logic “0” and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic “1”. • Built-In Low-Power RC Oscillator • Oscillator Frequency Range . . . . . . . . . . DC to 100kHz • External Clock (Applied to Pin 3) can be Used Instead of Oscillator • Operates as 2N Frequency Divider or as a SingleTransition Timer • Q/Q Select Provides Output Logic Level Flexibility • AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation Timing is initialized by setting the AUTO RESET input (pin 5) to logic “0” and turning power on. If pin 5 is set to logic “1”, the AUTO RESET circuit is disabled and counting will not start until after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, VDD should be greater than 5V. • Operates With Very Slow Clock Rise and Fall Times • Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range • Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V The RC oscillator, shown in Figure 2, oscillates with a frequency determined by the RC network and is calculated using: • 5V, 10V, and 15V Parametric Ratings • Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” 1 f = ----------------------------------2.3 R TC C TC Description CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the MASTER RESET input. Ordering Information PART NUMBER Pinout CD4541B (CERDIP, PDIP, SOIC, SOP, TSSOP) TOP VIEW RTC 1 14 VDD CTC 2 13 B RS 3 12 A NC 4 11 NC AUTO RESET 5 Where f is between 1kHz and 100kHz and R S ≥ 10k Ω and ≈ 2R TC TEMP. RANGE (oC) -55 to 125 14 Ld CERDIP CD4541BE -55 to 125 14 Ld PDIP CD4541BM -55 to 125 14 Ld SOIC CD4541BMT -55 to 125 14 Ld SOIC CD4541BM96 -55 to 125 14 Ld SOIC CD4541BNSR -55 to 125 14 Ld SOP CD4541BPW -55 to 125 14 Ld TSSOP CD4541BPWR -55 to 125 14 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. 10 MODE MASTER RESET 6 9 Q/Q SELECT VSS 7 8 OUTPUT CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE CD4541BF3A 1 CD4541B Functional Diagram 12 A 13 B 1 RTC 2 CTC 3 RS 5 AR 6 MR 10 MODE 9 Q/Q SELECT 8 Q VDD = PIN 14 VSS = PIN 7 12 13 †A †B R N P Q 1 OF 3 MUX N P 3 †RS †CTC †RTC 2 210 213 8-STAGE COUNTER OSC 1 AUTO RESET† 9 216 OR 28 †Q/Q SELECT VDD 8-STAGE COUNTER R R 10 †MODE R 5 8 PWR ON RESET VSS VDD = 14 VSS = 7 6 MANUAL RESET† † All inputs are protected by CMOS Protection Network. NC = 4, 11 FIGURE 1. FREQUENCY SELECTION TABLE A B NO. OF STAGES N COUNT 2N 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 3 RS CTC TRUTH TABLE STATE PIN 0 TO CLOCK CKT 2 INTERNAL RESET 1 1 5 Auto Reset On 6 Master Reset Off Master Reset On 9 Output Initially Low After Reset (Q) Output Initially High After Reset (Q) 10 Single Transition Mode Recycle Mode RTC Auto Reset Disable FIGURE 2. RC OSCILLATOR CIRCUIT 2 CD4541B Absolute Maximum Ratings Thermal Information DC Supply - Voltage Range, VDD Voltages Referenced to VSS Terminal . . . . . . . . . . -0.5V to +20V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA Device Dissipation Per Output Transistor For TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Package Thermal Impedance, θJA (see Note 1) PDIP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W SOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) At Distance 1/16in ± 1/32in (1.59mm ±0.79mm) from case for 10s Maximum . . . . . . . . . . . . . . . . . . . . . . . . 265oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range For TA = Full Package Temperature Range . . . . . 3V (Min), 18V (Typ) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. Electrical Specifications LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS PARAMETER Quiescent Device Current, (Note 2) IDD (Max) Output Low (Sink) Current lOL (Min) Output High (Source) Current, IOH (Min) Output Voltage: Low-Level, VOL (Max) Output Voltage: High-Level, VOH (Min) Input Low Voltage, VIL (Max) 25 VO (V) VIN (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS - 0, 5 5 5 5 150 150 - 0.04 5 μA - 0, 10 10 10 10 300 300 - 0.04 10 μA - 0, 15 15 20 20 600 600 - 0.04 20 μA - 0, 20 20 100 100 3000 3000 - 0.08 100 μA 0.4 0, 5 5 1.9 1.85 1.26 1.08 1.55 3.1 - mA 0.5 0, 10 10 5 4.8 3.3 2.8 4 8 - mA 1.5 0, 15 15 12.6 12 8.4 7.2 10 20 - mA 4.6 0, 5 5 -1.9 -1.85 -1.26 -1.08 -1.55 -3.1 - mA 2.5 0, 5 5 -6.2 -6 -4.1 -3 -5 -10 - mA 9.5 0, 10 10 -5 -4.8 -3.3 -2.8 -4 -8 - mA 13.5 0, 15 15 -12.6 -12 -8.4 -7.2 -10 -20 - mA - 0, 5 5 - 0.05 - 0 0.05 V - 0, 10 10 - 0.05 - 0 0.05 V - 0, 15 15 - 0.05 - 0 0.05 V - 0, 5 5 - 4.95 4.95 5 - V - 0, 10 10 - 9.95 9.95 10 - V - 0, 15 15 - 14.95 14.95 15 - V 0.5, 4.5 - 5 - 1.5 - - 1.5 V 1, 9 - 10 - 3 - - 3 V 1.5, 13.5 - 15 - 4 - - 4 V 3 CD4541B Electrical Specifications (Continued) LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS 25 VO (V) VIN (V) VDD (V) -55 0.5, 4.5 - 5 - 1, 9 - 10 1.5, 13.5 - - 0, 18 PARAMETER Input High Voltage, VIH (Min) Input Current, lIN (Max) -40 85 MIN TYP MAX UNITS 3.5 3.5 - - V - 7 7 - - V 15 - 11 11 - - V 18 ±0.1 - ±10-5 ±0.1 μA ±0.1 ±1 125 ±1 NOTE: 2. With AUTO RESET enabled, additional current drain at 25oC is: 7μA (Typ), 200μA (Max) at 5V; 30μA (Typ), 350μA (Max) at 10V; 80μA (Typ), 500μA (Max) at 15V Dynamic Electrical Specifications PARAMETER Propagation Delay Times Clock to Q TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200kΩ SYMBOL VDD (V) MIN TYP MAX UNITS (28) tPHL , tPLH 5 - 3.5 10.5 μs 10 - 1.25 3.8 μs 15 - 0.9 2.9 μs 5 - 6.0 18 μs 10 - 3.5 10 μs 15 - 2.5 7.5 μs 5 - 100 200 ns 10 - 50 100 ns 15 - 40 80 ns 5 - 180 360 ns 10 - 90 180 ns 15 - 65 130 ns 5 900 300 - ns 10 300 100 - ns 15 225 85 - ns 5 - 1.5 - MHz 10 - 4 - MHz 15 - 6 - MHz (216) tPHL , tPLH Transition Time tTHL tTHL MASTER RESET, CLOCK Pulse Width Maximum Clock Pulse Input Frequency Maximum Clock Pulse Input Rise or Fall time fCL tr , tf 5, 10, 15 Unlimited 4 μs CD4541B Digital Timer Application A positive pulse on MASTER RESET resets the counters and latch. The output goes high and remains high until the number of pulses, selected by A and B, are counted. This circuit is retriggerable and is as accurate as the input frequency. If additional accuracy is desired, an external clock can be used on pin 3. A setup time equal to the width of the one-shot output is required immediately following initial power up, during which time the output will be high. VDD RTC CTC RS AR MR INPUT 1 14 2 3 4 5 6 13 12 11 10 9 7 8 B A OUTPUT t FIGURE 3. DIGITAL TIMER APPLICATION CIRCUIT 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD4541BE ACTIVE PDIP N 14 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -55 to 125 CD4541BE Samples CD4541BEE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4541BE Samples CD4541BF ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD4541BF Samples CD4541BF3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD4541BF3A Samples CD4541BM ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4541BM Samples CD4541BM96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CD4541BM Samples CD4541BMT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4541BM Samples CD4541BMTG4 ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4541BM Samples CD4541BNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4541B Samples CD4541BPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM541B Samples CD4541BPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CM541B Samples CD4541BPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM541B Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of