CD74AC251,
CD74ACT251
Data sheet acquired from Harris Semiconductor
SCHS246
8-Input Multiplexer, Three-State
August 1998
Features
Description
• Buffered Inputs
The CD74AC251 and CD74ACT251 8-input multiplexers that
utilize the Harris Advanced CMOS Logic technology. This
multiplexer features both true (Y) and complement (Y) outputs
as well as an Output Enable (OE) input. The OE must be at a
LOW logic level to enable this device. When the OE input is
HIGH, both outputs are in the high-impedance state. When
enabled, address information on the data select inputs determines which data input is routed to the Y and Y outputs.
• Typical Propagation Delay
- 6ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Pinout
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
CD74AC251E
0 to 70oC, -40 to 85, 16 Ld PDIP
-55 to 125
E16.3
CD74ACT251E
0 to 70oC, -40 to 85, 16 Ld PDIP
-55 to 125
E16.3
CD74AC251M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
M16.15
CD74ACT251M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CD74AC251, CD74ACT251
(PDIP, SOIC)
TOP VIEW
I3 1
16 VCC
I2 2
15 I4
I1 3
14 I5
I0 4
13 I6
Y 5
12 I7
Y 6
11 S0
OE 7
10 S1
GND 8
9 S2
2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris
customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
1
File Number
1981.1
CD74AC251, CD74ACT251
Functional Diagram
THREE-STATE
DISABLE OE
I0
I1
I2
CHANNEL
INPUTS
I3
I4
I5
I6
7
4
3
2
1
15
14
5
13
Y
12
OUTPUTS
6
I7
Y
11
S0
DATA
SELECT
10
S1
9
S2
TRUTH TABLE
INPUTS
OUTPUTS
SELECT
S2
S1
S0
OUTPUT ENABLE OE
Y
Y
X
X
X
H
Z
Z
L
L
L
L
I0
I0
L
L
H
L
I1
I1
L
H
L
L
I2
I2
L
H
H
L
I3
I3
H
L
L
L
I4
I4
H
L
H
L
I5
I5
H
H
L
L
I6
I6
H
H
H
L
I7
I7
H = High logic level, L = Low logic level, Z = High impedance (off),
X = Irrelevant, I0, I1...I7 = The level of the respective input
2
CD74AC251, CD74ACT251
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
1.5
1.4
-
1.4
-
1.4
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
-
-0.05
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
3
CD74AC251, CD74ACT251
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
ACT TYPES
Low Level Output Voltage
VOL
VIH or VIL
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State or Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
Input Leakage Current
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
4
CD74AC251, CD74ACT251
ACT Input Load Table
INPUT
UNIT LOAD
S0, S1, S3
1
OE
1
I0 - I 7
1
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
153
-
-
169
ns
3.3
(Note 9)
4.9
-
17.2
4.7
-
18.9
ns
5
(Note 10)
3.5
-
12.3
3.4
-
13.5
ns
1.5
-
-
169
-
-
186
ns
3.3
5.4
-
19
5.2
-
20.9
ns
5
3.8
-
13.5
3.7
-
14.9
ns
1.5
-
-
207
-
-
228
ns
3.3
6.6
-
23.2
6.4
-
25.5
ns
5
4.7
-
16.5
4.6
-
18.2
ns
1.5
-
-
223
-
-
245
ns
3.3
7.1
-
24.9
6.9
-
27.4
ns
5
5.1
-
17.8
4.9
-
19.6
ns
1.5
-
-
155
-
-
169
ns
3.3
5.2
-
18.7
5.1
-
20.3
ns
5
3.5
-
12.3
3.4
-
13.5
ns
AC TYPES
Propagation Delay,
Data to Y Output
Propagation Delay,
Data to Y Output
Propagation Delay,
Select to Y Output
Propagation Delay,
Select to Y Output
Propagation Delay,
Output Enable and Output
Disable to Output
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPZH, tPZL,
tPHZ, tPLZ
Three-State Output
Capacitance
CO
-
-
-
15
-
-
15
pF
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
120
-
-
120
-
pF
Propagation Delay,
Data to Y Output
tPLH, tPHL
5
(Note 10)
3.5
-
12.3
3.4
-
13.5
ns
Propagation Delay,
Data to Y Output
tPLH, tPHL
5
3.8
-
13.5
3.7
-
14.9
ns
Propagation Delay,
Select to Y Output
tPLH, tPHL
5
4.7
-
16.5
4.6
-
18.2
ns
Propagation Delay,
Select to Y Output
tPLH, tPHL
5
5.1
-
17.8
4.9
-
19.6
ns
Propagation Delay,
Output Enable and Output
Disable to Output
tPZH, tPZL,
tPHZ, tPLZ
5
3.5
-
12.3
3.4
-
13.5
ns
Power Dissipation Capacitance
ACT TYPES
5
CD74AC251, CD74ACT251
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
(Continued)
-40oC TO 85oC
PARAMETER
SYMBOL
-55oC TO 125oC
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Three-State Output
Capacitance
CO
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
45
-
-
45
-
pF
Power Dissipation Capacitance
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per device.
PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
tr = 3ns
tf = 3ns
INPUT LEVEL
90%
OUTPUT
DISABLE
VS
10%
GND
tPZL
tPLZ
VS
0.2VCC
OUTPUT: LOW
TO OFF TO LOW
tPHZ
tPZH
VOH (≠ VCC)
0.8 VCC
VS
OUTPUT: HIGH
TO OFF TO HIGH
OUTPUTS
ENABLED
OTHER
INPUTS
(TIED HIGH
OR LOW)
OUTPUTS
DISABLED
OUTPUT
DISABLE
OUTPUTS
ENABLED
GND (tPHZ, tPZH)
OPEN (tPHL, tPLH)
2 VCC (tPLZ, tPZL)
(OPEN DRAIN)
500Ω†
RL
DUT
WITH
THREESTATE
OUTPUT
VOL (≠ GND)
OUT
500Ω†
RL
CL
50pF
†FOR AC SERIES ONLY: WHEN VCC = 1.5V, RL = 1kΩ
FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT
tr = 3ns
90%
IN V
S
10%
tf = 3ns
INPUT LEVEL
VS
INVERTING
OUTPUT Y
tPHL
tPLH
NON-INVERTING
OUTPUT Y
VS
tPLH
tPHL
FIGURE 2. PROPAGATION DELAY TIMES
6
CD74AC251, CD74ACT251
OUTPUT
RL (NOTE)
500Ω
DUT
OUTPUT
LOAD
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
CD74AC
CD74ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
Input Level
FIGURE 3. PROPAGATION DELAY TIMES
7
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD74AC251M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
AC251M
Samples
CD74AC251M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
AC251M
Samples
CD74AC251M96E4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
AC251M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of