CD74ACT238E

CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 D D D D D D D D E PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 description/ordering information The CD74ACT238 decoder/demultiplexer is designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications (see Application Information). ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to 125°C PDIP – E Tube CD74ACT238E CD74ACT238E † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 FUNCTION TABLE SELECT INPUTS ENABLE INPUTS G1 G2A G2B C B X X H X X X X H X X A OUTPUTS Y0 Y1 Y2 Y3 Y4 X L X L Y5 Y6 L L L L L L L L L L L L L L L X X X X X L L L L L L L L H L L L L L H L L L L L L L H L L L L H L H L L L L L L H L L L H L L L H L L L L L H L L L H H L L L H L L L L H L L H L L L L L L H L L L H L L H L H L L L L L H L L H L L H H L L L L L L L H L H L L H H H L L L L L L L H logic diagram (positive logic) 15 A Y0 1 14 Y1 13 Select Inputs B Y2 2 12 11 3 Y3 Data Outputs Y4 C 10 9 G2A Enable Inputs G2B G1 2 Y7 4 7 5 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y5 Y6 Y7 CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25°C –40°C to 85°C UNIT MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current –24 IOL ∆t/∆v Low-level output current Input transition rise or fall rate High-level input voltage –55°C to 125°C 2 2 0.8 2 V 0.8 V VCC VCC V –24 –24 mA 24 24 24 mA 10 10 10 ns/V VCC VCC 0.8 V 0 0 VCC VCC 0 0 V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH VOL VI = VIH or VIL VI = VIH or VIL II ICC VI = VCC or GND VI = VCC or GND, DICC‡ VI = VCC – 2.1 V –55°C to 125°C TA = 25°C VCC MAX MIN –40°C to 85°C MAX MIN UNIT MAX IOH = –50 µA IOH = –24 mA 4.5 V 4.4 4.5 V 3.94 IOH = –50 mA† IOH = –75 mA† 5.5 V IOL = 50 µA IOL = 24 mA IOL = 50 mA† 4.5 V 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 IOL = 75 mA† 5.5 V IO = 0 4.4 4.4 3.7 3.8 V 3.85 5.5 V 3.85 5.5 V 1.65 V 1.65 5.5 V ±0.1 ±1 ±1 µA 5.5 V 8 160 80 µA 2.4 3 2.8 mA 4.5 V to 5.5 V Ci 10 10 10 pF † Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. ‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT UNIT LOAD A, B, or C 0.83 G2A or G2B 1 G1 0.42 Unit Load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A B A, B, C Any Y tPLH tPHL G1 Any Y tPLH tPHL G2A G2B G2A, Any Y PARAMETER –55°C to 125°C –40°C to 85°C MIN MAX MIN MAX 3.9 15.6 4 14.2 3.9 15.6 4 14.2 3.4 13.6 3.5 12.4 3.4 13.6 3.5 12.4 3.6 14.2 3.7 12.9 3.6 14.2 3.7 12.9 UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT 110 pF CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw 3V 1.5 V Input LOAD CIRCUIT 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.5 V 1.5 V 0V 0V trec Data Input 3V 1.5 V CLK th tsu 1.5 V 10% 90% 90% tr 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V 1.5 V 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3V Input 1.5 V 1.5 V 0V tPLH In-Phase Output 50% 10% 90% 90% tr 90% 1.5 V 1.5 V 0V tPHL tPHL Out-of-Phase Output 3V Output Control VOH 50% VCC 10% VOL tf tPLH 50% VCC 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ tPZL 20% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) ≈VCC 20% VCC VOL 80% VCC VOH 80% VCC ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 APPLICATION INFORMATION CD74ACT238 BIN/OCT 1 2 3 VCC 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 0 1 2 3 4 5 6 7 CD74ACT238 BIN/OCT 1 A0 2 A1 3 A2 1 2 2 4 6 A3 0 1 3 & 4 4 A4 EN 5 5 6 7 15 14 13 12 11 10 9 7 8 9 10 11 12 13 14 15 CD74ACT238 BIN/OCT 1 2 3 6 0 1 1 2 2 4 3 & 4 4 5 EN 5 6 7 Figure 2. 24-Bit Decoding Scheme 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 14 13 12 11 10 9 7 16 17 18 19 20 21 22 23 CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 APPLICATION INFORMATION CD74ACT238 BIN/OCT 1 A0 2 A1 3 A2 1 1 2 2 4 6 VCC 0 3 & 4 4 A3 EN 5 A4 5 6 7 15 14 13 12 11 10 9 7 0 1 2 3 4 5 6 7 CD74ACT238 BIN/OCT 1 2 3 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 8 9 10 11 12 13 14 15 CD74ACT238 BIN/OCT 1 2 3 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 16 17 18 19 20 21 22 23 CD74ACT238 BIN/OCT 1 2 3 6 0 1 1 2 2 4 3 & 4 4 5 EN 5 6 7 15 14 13 12 11 10 9 7 24 25 26 27 28 29 30 31 Figure 3. 32-Bit Decoding Scheme POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) CD74ACT238E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74ACT238E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of