CD74HC03E

[ /Title (CD74H C03, CD74H CT03) /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003 Features Description • Buffered Inputs The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally as well as pin compatible with the standard LS logic family. • Typical Propagation Delay: 8ns at VCC = 5V, CL = 15pF, TA = 25oC • Output Pull-up to 10V • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads These open drain NAND gates can drive into resistive loads to output voltages as high as 10V. Minimum values of RL required versus load voltage are shown in Figure 2. • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH TEMP. RANGE (oC) PACKAGE CD54HC03F3A -55 to 125 14 Ld CERDIP CD54HCT03F3A -55 to 125 14 Ld CERDIP CD74HC03E -55 to 125 14 Ld PDIP CD74HC03M -55 to 125 14 Ld SOIC CD74HC03MT -55 to 125 14 Ld SOIC CD74HC03M96 -55 to 125 14 Ld SOIC CD74HCT03E -55 to 125 14 Ld PDIP CD74HCT03M -55 to 125 14 Ld SOIC CD74HCT03MT -55 to 125 14 Ld SOIC CD74HCT03M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC03, CD54HCT03 (CERDIP) CD74HC03, CD74HCT03 (PDIP, SOIC) TOP VIEW 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Functional Diagram 1A 1B 2A 2B 3A 3B 4A 4B 1 3 2 4 5 6 9 8 1Y 2Y 3Y 10 12 11 13 4Y GND = 7 VCC = 14 TRUTH TABLE A B Y L L Z (Note 1) H (Note 2) H L Z (Note 1) H (Note 2) L H Z (Note 1) H (Note 2) H H L L NOTES: 1. Without pull-up (high impedance) 2. Requires pull-up (RL to VL) Logic Symbol nA nY nB 2 CD54HC03, CD74HC03, CD54HCT, CD74HCT03 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC Drain Current, per Output, IO For -0.5V < VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V HC TYPES High Level Input Voltage Low Level Input Voltage Low Level Output Voltage CMOS Loads VIL VOL - VIH or VIL Low Level Output Voltage TTL Loads - - 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 2 - 20 - 40 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V Input Leakage Current Quiescent Device Current HCT TYPES 3 CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL VI (V) Low Level Output Voltage CMOS Loads VOL VIH or VIL IO (mA) VCC (V) -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA II VCC and GND - 5.5 - ICC VCC or GND 0 5.5 - - 2 - 20 - 40 µA ∆ICC (Note 4) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load -40oC TO 85oC 0.02 Low Level Output Voltage TTL Loads Input Leakage Current 25oC NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS nA, nB 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 100 - 125 - 150 ns 4.5 - - 20 - 25 - 30 ns 6 - - 17 - 21 - 26 ns HC TYPES Propagation Delay, Input to Output (Figure 1) Propagation Delay, Data Input to Output Y tPLH, tPHL CL = 15pF 5 - 8 - - - - - ns Transition Times (Figure 1) tTLH, tTHL CL = 50pF 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance Power Dissipation Capacitance (Notes 5, 6) CI - - - - 10 - 10 - 10 pF CPD - 5 - 6.4 - - - - - pF HCT TYPES Propagation Delay, Input to Output (Figure 1) tPLH, tPHL CL = 50pF 4.5 - - 24 - 30 - 36 ns Propagation Delay, Data Input to Output Y tPLH, tPHL CL = 15pF 5 - 9 - - - - - ns Transition Times (Figure 1) tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns - - - 10 - 10 - 10 pF Input Capacitance CI - 4 CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Switching Specifications Input tr, tf = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS Power Dissipation Capacitance (Notes 5, 6) CPD - 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 5 - 9 - - - - - pF NOTES: 5. CPD is used to determine the dynamic power consumption, per gate. 6. PD = CPD VCC2 fi + Σ (CL VCC2 fo) + Σ (VL2/RL) (Duty Factor “Low”) where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage, Duty Factor “Low” = percent of time output is “low”, VL = output voltage, RL = pull-up resistor. Test Circuits and Waveforms 800 INPUT LEVEL VS RL MIN, PULLUP RESISTOR (Ω) VS tPZL tPLZ VOH 90% nY 10% VOL tTHL OUTPUT LOW OUTPUT OFF OUTPUT LOW 1kΩ nA(nB) VCC OPEN DRAIN NAND GATE nB(nA) 500 HCT 400 VCC = 5V ±10% 300 VL HC RL 200 HC/HCT03 100 0 FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY TIMES, AND TEST CIRCUIT tr = 6ns VO 1 2 3 4 5 6 7 VL, LOAD VOLTAGE (V) GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL 9 tf = 6ns tr = 6ns VCC 90% 50% 10% 8 10 FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE tf = 6ns tPHL 600 0.8V (HCT VIL MAX) ≤ 1.35V (HC VIL MAX) RL 0.26V MAX = R = 4mA VO ON o 65Ω AT 25 C RON 50pF VCC INPUT VL 700 tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5 PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2025 PACKAGING INFORMATION Orderable part number (1) Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) CD54HC03F Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HC03F.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HC03F CD54HC03F CD54HC03F3A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HC03F3A CD54HC03F3A.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HC03F3A CD54HCT03F3A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HCT03F3A CD54HCT03F3A.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54HCT03F3A CD74HC03E Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HC03E CD74HC03E.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HC03E CD74HC03M Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 HC03M CD74HC03M96 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HC03M CD74HC03M96.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 HC03M CD74HC03MT Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 HC03M CD74HCT03E Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HCT03E CD74HCT03E.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74HCT03E Call TI Call TI -55 to 125 HCT03M -55 to 125 HCT03M -55 to 125 HCT03M CD74HCT03M Obsolete Production SOIC (D) | 14 - - CD74HCT03M96 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes CD74HCT03M96.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | SN | NIPDAU Level-1-260C-UNLIM NIPDAU Level-1-260C-UNLIM Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (6) 28-Jun-2025 Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. 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OTHER QUALIFIED VERSIONS OF CD54HC03, CD54HCT03, CD74HC03, CD74HCT03 : • Catalog : CD74HC03, CD74HCT03 • Military : CD54HC03, CD54HCT03 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC03M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT03M96 SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1 CD74HCT03M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC03M96 SOIC D 14 2500 356.0 356.0 35.0 CD74HCT03M96 SOIC D 14 2500 366.0 364.0 50.0 CD74HCT03M96 SOIC D 14 2500 356.0 356.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CD74HC03E N PDIP 14 25 506 13.97 11230 4.32 CD74HC03E N PDIP 14 25 506 13.97 11230 4.32 CD74HC03E.A N PDIP 14 25 506 13.97 11230 4.32 CD74HC03E.A N PDIP 14 25 506 13.97 11230 4.32 CD74HCT03E N PDIP 14 25 506 13.97 11230 4.32 CD74HCT03E N PDIP 14 25 506 13.97 11230 4.32 CD74HCT03E.A N PDIP 14 25 506 13.97 11230 4.32 CD74HCT03E.A N PDIP 14 25 506 13.97 11230 4.32 Pack Materials-Page 3 PACKAGE OUTLINE D0014A SOIC - 1.75 mm max height SCALE 1.800 SMALL OUTLINE INTEGRATED CIRCUIT C 6.2 TYP 5.8 SEATING PLANE PIN 1 ID AREA A 0.1 C 12X 1.27 14 1 2X 7.62 8.75 8.55 NOTE 3 7 8 B 4.0 3.8 NOTE 4 SEE DETAIL A 14X 0.51 0.31 0.25 C A B 1.75 MAX 0.25 TYP 0.13 0.25 GAGE PLANE 0 -8 0.25 0.10 1.27 0.40 DETAIL A TYPICAL 4220718/A 09/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. www.ti.com EXAMPLE BOARD LAYOUT D0014A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 14X (1.55) SYMM 1 14 14X (0.6) 12X (1.27) SYMM 8 7 (R0.05) TYP (5.4) LAND PATTERN EXAMPLE SCALE:8X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220718/A 09/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0014A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 14X (1.55) SYMM 1 14 14X (0.6) 12X (1.27) SYMM 7 8 (5.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X 4220718/A 09/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X .005 MIN [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 [0.36-0.66] 14X .045-.065 [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 8 7 B .245-.283 [6.22-7.19] .2 MAX TYP [5.08] C .13 MIN TYP [3.3] SEATING PLANE .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 TYP 14X .008-.014 [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL A SEE DETAIL B 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 8 7 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX [0.05] ALL AROUND (.063) [1.6] METAL ( .063) [1.6] SOLDER MASK OPENING METAL (R.002 ) TYP [0.05] .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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