CD74HC04, CD54HC04
CD54HC04
SCHS117F – AUGUSTCD74HC04,
1997 – REVISED
APRIL 2021
SCHS117F – AUGUST 1997 – REVISED APRIL 2021
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CDx4HC04 Hex Inverters
1 Features
3 Description
•
•
•
This device contains six independent inverters. Each
gate performs the Boolean function Y = A in positive
logic.
•
•
Buffered inputs
Wide operating voltage range: 2 V to 6 V
Wide operating temperature range:
–55°C to +125°C
Supports fanout up to 10 LSTTL loads
Significant power reduction compared to LSTTL
logic ICs
2 Applications
•
•
Synchronize inverted clock inputs
Invert a digital signal
Device Information(1)
PART NUMBER
SOIC (14)
8.70 mm × 3.90 mm
CD74HC04E
PDIP (14)
19.30 mm × 6.40 mm
CD54HC04F
CDIP (14)
21.30 mm × 7.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1A
1
14
1Y
2
13
6A
2A
3
4
12
11
6Y
3A
5
10
5Y
3Y
6
7
9
8
4A
GND
BODY SIZE (NOM)
CD74HC04M
(1)
2Y
PACKAGE
VCC
5A
4Y
Functional pinout
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Operating Characteristics........................................... 6
6.8 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Documentation Support.......................................... 13
12.2 Related Links.......................................................... 13
12.3 Support Resources................................................. 13
12.4 Trademarks............................................................. 13
12.5 Electrostatic Discharge Caution..............................13
12.6 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2004) to Revision F (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated to new data sheet standards................................................................................................................ 1
• Moved the HCT devices to a standalone data sheet (SCHS401) ......................................................................1
• RθJA increased for the D and PW packages and decreased for the N package................................................. 5
2
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5 Pin Configuration and Functions
1A
1
14
VCC
1Y
2
13
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
Figure 5-1. D, N, or J Package
14-Pin SOIC, PDIP, or CDIP
Top View
Pin Functions
PIN
NAME
NO.
I/O
1A
1
Input
1Y
2
Output
2A
3
Input
2Y
4
Output
3A
5
Input
3Y
6
Output
GND
7
—
4Y
8
Output
4A
9
Input
5Y
10
Output
5A
11
Input
6Y
12
Output
6A
13
Input
VCC
14
—
DESCRIPTION
Channel 1, Input A
Channel 1, Output Y
Channel 2, Input A
Channel 2, Output Y
Channel 3, Input A
Channel 3, Output Y
Ground
Channel 4, Output Y
Channel 4, Input A
Channel 5, Output Y
Channel 5, Input A
Channel 6, Output Y
Channel 6, Input A
Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
IIK
Input clamp current(2)
VI < –0.5 V or VI > VCC +
0.5 V
±20
mA
IOK
Output clamp current(2)
VO < –0.5 V or VO > VCC +
0.5 V
±20
mA
IO
Continuous output current
VO > –0.5 V or VO < VCC +
0.5 V
±25
mA
±50
mA
Continuous current through VCC or GND
Junction temperature(3)
TJ
Lead temperature (soldering 10s)
Tstg
(1)
(2)
(3)
Plastic package
150
Hermetic package or die
175
SOIC - lead tips only
Storage temperature
–65
V
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
UNIT
CD74HC04 IN D (SOIC) AND N (PDIP) PACKAGES
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
MIN
NOM
MAX
2
5
6
Low-level input voltage
VI
Input voltage
VO
Output voltage
3.15
0.5
1.35
VCC = 6 V
tt
4
Input transition time
V
4.2
VCC = 4.5 V
0
VCC
V
VCC
V
1000
VCC = 4.5 V
500
VCC = 6 V
400
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V
1.8
0
VCC = 2 V
V
1.5
VCC = 2 V
VIL
UNIT
ns
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over operating free-air temperature range (unless otherwise noted)
MIN
TA
Operating free-air temperature
NOM
–55
MAX
UNIT
125
°C
6.4 Thermal Information
CD74HC04
THERMAL
METRIC(1)
PW (TSSOP)
N (PDIP)
D (SOIC)
14 PINS
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
151.7
69.3
133.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.4
57.4
89.0
°C/W
RθJB
Junction-to-board thermal resistance
94.7
49.0
89.5
°C/W
ΨJT
Junction-to-top characterization
parameter
25.2
37.4
45.5
°C/W
ΨJB
Junction-to-board characterization
parameter
94.1
48.8
89.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCC
25°C
MIN
IOH = –20
µA
VOH
High-level
output voltage
VI = VIH or
IOH = –4
VIL
mA
VOL
Low-level output VI = VIH or
voltage
VIL
–40°C to 85°C
MAX
MIN
TYP
–55°C to 125°C
MAX
MIN
2V
1.9
1.9
1.9
4.5 V
4.4
4.4
4.4
6V
5.9
5.9
5.9
4.5 V
3.98
3.84
3.7
6V
5.48
5.34
5.2
TYP
UNIT
MAX
V
IOH = –5.2
mA
IOL = 20
µA
TYP
2V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
0.1
0.1
IOL = 4 mA 4.5 V
6V
0.26
0.33
0.4
IOL = 5.2
mA
6V
0.26
0.33
0.4
V
II
Input leakage
current
VI = VCC or 0
6V
±0.1
±1
±1
µA
ICC
Supply current
VI = VCC or
IO = 0
0
6V
2
20
40
µA
Ci
Input
capacitance
5V
10
10
10
pF
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6.6 Switching Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
tpd
FROM
Propagation delay
A
A
tt
Transition-time
TO
Y
Operating free-air temperature (TA)
TEST
CONDITIO
NS
VCC
CL = 50 pF
Y
CL = 15 pF
Y
CL = 50 pF
25°C
–40°C to 85°C
–55°C to 125°C
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
2V
85
105
130
4.5 V
17
21
26
6V
14
18
22
2V
75
95
110
4.5 V
15
19
22
6V
13
16
19
5V
UNIT
ns
6
ns
6.7 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Power dissipation capacitance
No load
per gate
Cpd
VCC
MIN
5V
TYP
MAX UNIT
21
pF
6.8 Typical Characteristics
7
0.3
6
0.25
VOL Output Low Voltage (V)
VOH Output High Voltage (V)
TA = 25°C
5
4
3
2
2-V
4.5-V
6-V
1
0
0.2
0.15
0.1
0.05
0
0
1
2
3
4
IOH Output High Current (mA)
5
6
Figure 6-1. Typical output voltage in the high state
(VOH)
6
2-V
4.5-V
6-V
0
1
2
3
4
IOL Output Low Current (mA)
5
6
Figure 6-2. Typical output voltage in the low state
(VOL)
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7 Parameter Measurement Information
•
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
The outputs are measured one at a time, with one input transition per measurement.
Test
Point
90%
VCC
90%
Input
10%
10%
tr(1)
From Output
Under Test
CL(1)
0V
tf(1)
90%
VOH
90%
Output
10%
A.
10%
tr(1)
CL= 50 pF and includes probe and jig capacitance.
A.
Figure 7-1. Load Circuit
tf(1)
VOL
tt is the greater of tr and tf.
Figure 7-2. Voltage Waveforms Transition Times
VCC
Input
50%
50%
0V
tPLH
(1)
tPHL
(1)
VOH
Output
50%
50%
VOL
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
A.
The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
This device contains six independent inverters. Each gate performs the Boolean function Y = A in positive logic.
8.2 Functional Block Diagram
xA
xY
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The CD74HC04 can drive a load with a total capacitance less than or equal to the maximum load listed in the
Switching Characteristics connected to a high-impedance CMOS input while still meeting all of the datasheet
specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided
load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output
and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in
parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated
with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage
current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the
Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy
input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to
the standard CMOS input.
8
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8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
Device
VCC
+IIK
+IOK
Logic
Input
Output
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
INPUT
OUTPUT
A
Y
L
H
H
L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
This device can be used to add an additional stage to a counter with an external flip-flop. Because counters
use a negative edge trigger, the flip-flop's clock input must be inverted to provide this function. This function
only requires one of the six available inverters in the device, so the remaining channels can be used for other
applications needing an inverted signal or improved signal integrity. Unused inputs must be terminated at VCC or
GND. Unused outputs can be left floating.
9.2 Typical Application
20
Counter
Clear
21
CLR
22
23
Input
CLR
Q
24
D-Typ e
Flip-Flop
D
Q
Figure 9-1. Typical application schematic
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
CD74HC04 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device can
only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to
exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.
10
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9.2.1.2 Input Considerations
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
CD74HC04, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The CD74HC04 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions.
Refer to the Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC04
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
23
Input ± 32 kHz
24 ± 1 kHz
23
24
Figure 9-2. Typical application timing diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to the
device
1A
1
14
VCC
1Y
2
13
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
Unused inputs
tied to VCC
Unused
output left
floating
Figure 11-1. Example layout for the CD74HC04
12
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CD54HC04F
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC04F
CD54HC04F3A
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8409801CA
CD54HC04F3A
CD74HC04E
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC04E
CD74HC04M
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC04M
CD74HC04M96
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC04M
CD74HC04MT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC04M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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