CD74HC14M96

[ /Title (CD74H C14, CD74H CT14) /Subject (High Speed CMOS Logic Hex Invert- CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Data sheet acquired from Harris Semiconductor SCHS129F High-Speed CMOS Logic Hex Inverting Schmitt Trigger January 1998 - Revised May 2005 Features Description • Unlimited Input Rise and Fall Times The ’HC14 and ’HCT14 each contain six inverting Schmitt triggers in one package. • Exceptionally High Noise Immunity Ordering Information • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads PART NUMBER TEMP. RANGE (oC) PACKAGE • Wide Operating Temperature Range . . . -55oC to 125oC CD54HC14F3A -55 to 125 14 Ld CERDIP • Balanced Propagation Delay and Transition Times CD54HCT14F3A -55 to 125 14 Ld CERDIP • Significant Power Reduction Compared to LSTTL Logic ICs CD74HC14E -55 to 125 14 Ld PDIP CD74HC14M -55 to 125 14 Ld SOIC • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC14MT -55 to 125 14 Ld SOIC CD74HC14M96 -55 to 125 14 Ld SOIC CD74HC14PW -55 to 125 14 Ld TSSOP • HCT Types - 4.5V to 5.5V Operation - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC14PWR -55 to 125 14 Ld TSSOP CD74HCT14E -55 to 125 14 Ld PDIP CD74HCT14M -55 to 125 14 Ld SOIC CD74HCT14MT -55 to 125 14 Ld SOIC CD74HCT14M96 -55 to 125 14 Ld SOIC CD74HCT14PW -55 to 125 14 Ld TSSOP CD74HCT14PWR -55 to 125 14 Ld TSSOP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC14, CD54HCT14 (CERDIP) CD74HC14, CD74HCT14 (PDIP, SOIC, TSSOP) TOP VIEW 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2005, Texas Instruments Incorporated 1 CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Functional Diagram 1A 2A 3A 4A 5A 6A 1 2 3 4 5 6 9 8 11 10 13 12 1Y 2Y 3Y 4Y 5Y 6Y GND = 7 VCC = 14 TRUTH TABLE INPUT (A) OUTPUT (Y) L H H L H= High Level L= Low Level Logic Diagram nA nY VH VO VH = VT+ - VTVI VT- VT+ V T+ VT - VCC VH VI GND VCC VO GND FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP 2 CD54HC14, CD74HC14, CD54HCT, CD74HCT14 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VT+ - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 0.7 1.5 0.7 1.5 0.7 1.5 V 4.5 1.7 3.15 1.7 3.15 1.7 3.15 V 6 2.1 4.2 2.1 4.2 2.1 4.2 V 2 0.3 1.0 0.3 1.0 0.3 1.0 V 4.5 0.9 2.2 0.9 2.2 0.9 2.2 V 6 1.2 3.0 1.2 3.0 1.2 3.0 V 2 0.2 1.0 0.2 1.0 0.2 1.0 V 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 6 0.6 1.6 0.6 1.6 0.6 1.6 V -0.02 2 1.9 - 1.9 - 1.9 - V -0.02 4.5 4.4 - 4.4 - 4.4 - V -0.02 6 5.9 - 5.9 - 5.9 - V - - - - - - - - V -4 4.5 3.98 - 3.84 - 3.7 - V -5.2 6 5.48 - 5.34 - 5.2 - V 0.02 2 - 0.1 - 0.1 - 0.1 V 0.02 4.5 - 0.1 - 0.1 - 0.1 V 0.02 6 - 0.1 - 0.1 - 0.1 V HC TYPES Input Switch Points VT- VH High Level Output Voltage CMOS Loads VOH - - V T- High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VT+ - - - - - - - - - - - V 4 4.5 - 0.26 - 0.33 - 0.4 V 5.2 6 - 0.26 - 0.33 - 0.4 V 3 CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current SYMBOL VI (V) II VCC or GND - ICC VCC or GND VT+ - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 6 - ±0.1 - ±1 - ±1 µA 0 6 - 2 - 20 - 40 µA - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V 5.5 1.4 2.1 1.4 2.1 1.4 2.1 V 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V 5.5 0.6 1.4 0.6 1.4 0.6 1.4 V 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 5.5 0.4 1.5 0.4 1.5 0.4 1.5 V -0.02 4.5 4.4 - 4.4 - 4.4 - V -4 4.5 3.98 - 3.84 - 3.7 - V 0.02 4.5 - 0.1 - 0.1 - 0.1 V 4 4.5 - 0.26 - 0.33 - 0.4 V HCT TYPES Input Switch Points VT- VH High Level Output Voltage CMOS Loads VOH V T- High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VT+ Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 2 - 20 - 40 µA ∆ICC (Note 2) VCC - 2.1 - 4.5 to 5.5 - 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS nA 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4 Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 135 - 170 - 205 ns CL = 50pF 4.5 - - 27 - 34 - 41 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns CL = 50pF 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC TYPES Propagation Delay, A to Y Output Transition Times tTLH, tTHL Input Capacitance Power Dissipation Capacitance (Notes 3, 4) CI - - - - 10 - 10 - 10 pF CPD - 5 - 20 - - - - - pF CL = 50pF 4.5 - - 38 - 48 - 57 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 4.5 - - 15 - 19 - 22 ns HCT TYPES Propagation Delay, A to Y tPLH, tPHL Output Transition Times tTLH, tTHL Input Capacitance Power Dissipation Capacitance (Notes 3, 4) CI - - - - 10 - 10 - 10 pF CPD - 5 - 20 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per inverter. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 4. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD54HC14F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC14F CD54HC14F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8409101CA CD54HC14F3A CD54HCT14F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HCT14F CD54HCT14F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8689001CA CD54HCT14F3A CD74HC14E ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC14E CD74HC14EE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC14E CD74HC14M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14M96G4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14ME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14MG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14MTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC14M CD74HC14PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ14 CD74HC14PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ14 CD74HCT14E ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT14E Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD74HCT14M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT14M CD74HCT14M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT14M CD74HCT14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT14M CD74HCT14MG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT14M CD74HCT14MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT14M CD74HCT14PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK14 CD74HCT14PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK14 CD74HCT14PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK14 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of