CD74HC151MT

CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 CDx4HC151, CDx4HCT151 High-Speed CMOS Logic 8-Input Multiplexer 1 Features 2 Description • • • The ’HC151 and ’HCT151 are single 8-channel digital multiplexers having three binary control inputs, A, B and C and an active low enable (G) input. The three binary signals select 1 of 8 channels. Outputs are both inverting (W) and non-inverting (Y). • • • • • • Complementary data outputs Buffered inputs and outputs Fanout (over temperature range) – Standard outputs: 10 LSTTL Loads – Bus driver outputs: 15 LSTTL Loads Wide operating temp range: -55°C° to 125°C Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs Alternate source is Philips/Signetics HC Types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT Types – 4.5 V to 5.5 V Operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min) – CMOS input compatibility, II ≤ 1μA at VOL, VOH Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC151M SOIC (16) 9.90 mm × 3.90 mm CD74HC151E PDIP (16) 19.31 mm × 6.35 mm CD54HC151F3A CDIP (16) 24.38 mm × 6.92 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 011 010 G A B C CBA 111 110 101 100 001 000 D0 D1 D2 Y D3 D4 W D5 D6 D7 Functional Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 (1) 5.1 Absolute Maximum Ratings .....................................4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics............................................6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................9 8 Power Supply Recommendations................................10 9 Layout.............................................................................10 9.1 Layout Guidelines..................................................... 10 10 Device and Documentation Support..........................11 10.1 Documentation Support.......................................... 11 10.2 Receiving Notification of Documentation Updates.. 11 10.3 Support Resources................................................. 11 10.4 Trademarks............................................................. 11 10.5 Electrostatic Discharge Caution.............................. 11 10.6 Glossary.................................................................. 11 11 Mechanical, Packaging, and Orderable Information.................................................................... 11 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2003) to Revision D (November 2021) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 • Updated pin names to match current TI naming conventions. I3 is now D3, I2 is now D2, I1 is now D1, I0 is now D0, Y is now W, E is now G, S2 is now C, S1 is now B, S0 is now A, I7 is now D7, I6 is now D6, I5 is now D5, I4 is now D4 ............................................................................................................................................................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 4 Pin Configuration and Functions D3 1 16 VCC D2 2 D4 D1 D0 3 15 14 4 13 Y 5 12 D6 D7 W G 6 11 A 7 8 10 B C GND 9 D5 J, N, or D package 16-Pin CDIP, PDIP, SOIC Top View Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 3 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 5 Specifications (1) 5.1 Absolute Maximum Ratings MIN MAX -0.5 7 UNIT VCC Supply voltage range IIK Input diode current (VI < -0.5 V or VI > VCC + 0.5 V) ±20 mA IOK Output diode current (VO < -0.5 V or VO > VCC + 0.5 V) ±20 mA IO Continuous output current (VO > -0.5 V or VO < VCC + 0.5 V) ±25 mA ±50 mA 150 °C 150 °C 300 °C Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature -65 Lead Temperature (Soldering 10s) (1) V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions TA Temperature Range VCC Supply Voltage Range VI,VO DC Input or Output Voltage tt Input Rise and Fall Time HC Types HCT Types MIN MAX UNIT –55 125 ℃ 2 6 4.5 5.5 0 VCC 2V V V 1000 4.5 V 500 6V 400 ns 5.3 Thermal Information CD74HC151, CD74HCT151 THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance (1) D (SOIC) N (PDIP) 16 PINS 16 PINS UNIT 73 67 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 5.4 Electrical Characteristics (1) PARAMETER TEST CONDITIONS VCC (V) 25℃ MIN TYP -40℃ to 85℃ MAX MIN MAX -55℃ to 125℃ MIN MAX UNITS HC TYPES VIH High level input voltage VIL Low level input voltage High level output voltage VOH High level output voltage Low level output voltage VOL Low level output voltage 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = – 20 μA 2 1.9 1.9 1.9 IOH = – 20 μA 4.5 4.4 4.4 4.4 IOH = – 20 μA 6 5.9 5.9 5.9 IOH = – 4 mA 4.5 3.98 3.84 3.7 IOH = – 5.2 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 5.34 V V 5.2 IOL = 4 mA 4.5 0.26 0.33 0.4 IOL = 5.2 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 8 80 160 μA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 2 0.8 0.8 V 0.8 V IOH = – 20 μA 4.5 4.4 4.4 4.4 High level output voltage IOH = – 4 mA 4.5 3.98 3.84 3.7 Low level output voltage IOL = 20 mA 4.5 0.1 0.1 0.1 Low level output voltage IOL = 4 mA 4.5 0.26 0.33 0.4 VI = VCC or GND 5.5 ± 0.1 ±1 ±1 μA 8 80 160 μA Input leakage current ICC Supply current (1) (2) 2 High level output voltage II ΔICC (2) 2 Additional supply current per input pin V VI = VCC or GND 5.5 Select inputs held at VCC – 2.1 4.5 to 5.5 100 540 675 735 Data inputs held at VCC – 2.1 4.5 to 5.5 100 162 202.5 220.5 Enable inputs held at VCC – 2.1 4.5 to 5.5 100 108 135 147 V μA VI = VIH or VIL, unless otherwise noted. For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 5 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 5.5 Switching Characteristics Input tt = 6ns. Unless otherwise specified, CL = 50pF. (See Parameter Measurement Information) PARAMETER VCC (V) Any Data Input to Y 4.5 25℃ MIN -40℃ to 85℃ TYP MAX MIN -55℃ to 125℃ MAX MIN MAX UNIT HC TYPES 2 Any Data Input to W 14(3) 29 37 43 230 280 37 46 56 31 39 48 185 230 280 37 46 56 31 39 48 205 255 310 41 51 62 15(3) 4.5 15(3) 6 2 17(3) 4.5 Enable to Y 6 35 43 53 2 140 175 210 28 35 42 24 30 36 145 180 220 29 36 44 6 25 31 38 2 75 95 110 4.5 15 19 22 6 13 16 19 10 10 10 11(3) 4.5 6 2 Enable to W tt 12(3) 4.5 Output Transition Time CIN Input Capacitance CPD Power Dissipation Capacitance(1) (2) 51 185 2 Any Select to W 255 43 2 4.5 tpd 215 34 6 6 Any Select to Y 170 5 59 ns ns ns ns ns ns ns pF pF HCT TYPES tpd 4.5 16(3) 38 48 57 ns Any Data Input to W 4.5 15(3) 36 45 54 ns Any Select to Y 4.5 17 (3) 41 51 62 ns Any Select to W 4.5 18(3) 43 54 65 ns 12(3) 29 36 44 ns 36 46 54 ns 15 19 22 ns 10 10 10 pF Enable to Y 4.5 CL = 50 pF Enable to W 4.5 tt Output Transition Time 4.5 CIN Input Capacitance CPD Power Dissipation Capacitance(1) (2) (1) (2) (3) 6 Any Data Input to Y 5 15(3) 58 pF CPD is used to determine the dynamic power consumption, per gate. PD = VCC 2fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. Test Point From Output Under Test CL(1) (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs VCC Input 50% 90% tPLH tPHL tr(1) (1) VOH Output 50% 10% 10% tr(1) tPLH(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. VOH 50% VOH 90% Output VOL Output 0V tf(1) 90% 50% tPHL(1) 10% 10% 0V (1) VCC 90% Input 50% Figure 6-3. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-2. Voltage Waveforms, Propagation Delays for Standard CMOS Inputs 3V Input 1.3V 1.3V 0V tPLH (1) tPHL(1) VOH Output Waveform 1 50% 50% VOL tPHL(1) tPLH(1) VOH Output Waveform 2 50% 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 7 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 7 Detailed Description 7.1 Overview The ’HC151 and ’HCT151 are single 8-channel digital multiplexers having three binary control inputs, A, B and C and an active low enable (G) input. The three binary signals select 1 of 8 channels. Outputs are both inverting (W) and non-inverting (Y). 7.2 Functional Block Diagram G A B C CBA 111 110 101 100 011 010 001 000 D0 D1 D2 Y D3 D4 W D5 D6 D7 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 7.3 Device Functional Modes SELECT INPUTS(1) (1) DATA INPUTS ENABLE OUTPUT C B A D0 D1 D2 D3 D4 D5 D6 D7 G W Y X X X X X X X X X X X H H L L L L L X X X X X X X L H L L L L H X X X X X X X L L H L L H X L X X X X X X L H L L L H X H X X X X X X L L H L H L X X L X X X X X L H L L H L X X H X X X X X L L H L H H X X X L X X X X L H L L H H X X X H X X X X L L H H L L X X X X L X X X L H L H L L X X X X H X X X L L H H L H X X X X X L X X L H L H L H X X X X X H X X L L H H H L X X X X X X L X L H L H H L X X X X X X H X L L H H H H X X X X X X X L L H L H H H X X X X X X X H L L H H = High Voltage Level, L = Low Voltage Level, X = Don’t Care Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 9 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 www.ti.com SCHS150D – SEPTEMBER 1998 – REVISED NOVEMBER 2021 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. 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Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC151 CD74HC151 CD54HCT151 CD74HCT151 11 PACKAGE OPTION ADDENDUM www.ti.com 18-Mar-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 5962-9065201MEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9065201ME A CD54HCT151F3A CD54HC151F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8412801EA CD54HC151F3A CD54HCT151F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9065201ME A CD54HCT151F3A CD74HC151E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC151E CD74HC151EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC151E CD74HC151M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC151M CD74HC151M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC151M CD74HC151M96E4 ACTIVE SOIC D 16 2500 TBD Call TI Call TI -55 to 125 CD74HC151MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC151M CD74HCT151E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT151E CD74HCT151M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT151M CD74HCT151M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT151M CD74HCT151M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT151M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Mar-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of