CD74HC161M96

[ /Title (CD74 HC161 , CD74 HCT16 1, CD74 HC163 , CD74 HCT16 3) /Subject (High Speed CMOS Logic Presettable Counte rs) /Autho r () /Keywords (High Speed CMOS Logic Presettable Counte rs, High Speed The CD54HCT161 is obsolete and no longer is supplied. CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Data sheet acquired from Harris Semiconductor SCHS154D High-Speed CMOS Logic Presettable Counters February 1998 - Revised October 2003 Features Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the ’HC161 and ’HCT161 types). • ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset • ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. • Synchronous Counting and Loading • Two Count Enable Inputs for n-Bit Cascading The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage. • Look-Ahead Carry for High-Speed Counting • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times Ordering Information • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC161F3A -55 to 125 16 Ld CERDIP CD54HC163F3A -55 to 125 16 Ld CERDIP • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD54HCT163F3A -55 to 125 16 Ld CERDIP CD74HC161E -55 to 125 16 Ld PDIP CD74HC161M -55 to 125 16 Ld SOIC CD74HC161MT -55 to 125 16 Ld SOIC Description CD74HC161M96 -55 to 125 16 Ld SOIC The ’HC161, ’HCT161, ’HC163, and ’HCT163 are presettable synchronous counters that feature look-ahead carry logic for use in high-speed counting applications. The ’HC161 and ’HCT161 are asynchronous reset decade and binary counters, respectively; the ’HC163 and ’HCT163 devices are decade and binary counters, respectively, that are reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock. CD74HC163E -55 to 125 16 Ld PDIP CD74HC163M -55 to 125 16 Ld SOIC CD74HC163MT -55 to 125 16 Ld SOIC CD74HC163M96 -55 to 125 16 Ld SOIC CD74HCT161E -55 to 125 16 Ld PDIP CD74HCT161M -55 to 125 16 Ld SOIC A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met). CD74HCT161MT -55 to 125 16 Ld SOIC CD74HCT161M96 -55 to 125 16 Ld SOIC CD74HCT163E -55 to 125 16 Ld PDIP CD74HCT163M -55 to 125 16 Ld SOIC CD74HCT163MT -55 to 125 16 Ld SOIC CD74HCT163M96 -55 to 125 16 Ld SOIC All counters are reset with a low level on the Master Reset input, MR. In the ’HC163 and ’HCT163 counters (synchronous reset types), the requirements for setup and hold time with respect to the clock must be met. NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Pinout CD54HC161, CD54HCT161, CD54HC163, CD54HCT163 (CERDIP) CD74HC161, CD74HCT161, CD74HC163, CD74HCT163 (PDIP, SOIC) TOP VIEW MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE 9 SPE GND 8 Functional Diagram P0 3 SPE CP MR PE TE P1 4 P2 5 P3 6 9 14 2 13 1 12 7 11 10 15 2 Q0 Q1 Q2 Q3 TC CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 MODE SELECT - FUNCTION TABLE FOR ’HC161 AND ’HCT161 INPUTS OPERATING MODE OUTPUTS MR CP PE TE SPE Pn Qn TC Reset (Clear) L X X X X X L L Parallel Load H ↑ X X l l L L H ↑ X X l h H (Note 1) Count H ↑ h h h (Note 3) X Count (Note 1) Inhibit H X I (Note 2) X h (Note 3) X qn (Note 1) H X X I (Note 2) h (Note 3) X qn L MODE SELECT - FUNCTION TABLE FOR ’HC163 AND ’HCT163 INPUTS OPERATING MODE OUTPUTS MR CP PE TE SPE Pn Qn TC Reset (Clear) l ↑ X X X X L L Parallel Load h (Note 3) ↑ X X l l L L h (Note 3) ↑ X X l h H (Note 1) Count h (Note 3) ↑ h h h (Note 3) X Count (Note 1) Inhibit h (Note 3) X I (Note 2) X h (Note 3) X qn (Note 1) h (Note 3) X X I (Note 2) h (Note 3) X qn L H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition. NOTES: 1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and ’HC/HCT163). 2. The High-to-Low transition of PE or TE on the ’HC/HCT161 and the ’HC/HCT163 should only occur while CP is HIGH for conventional operation. 3. The Low-to-High transition of SPE on the ’HC/HCT161 and SPE or MR on the ’HC/HCT163 should only occur while CP is HIGH for conventional operation. 3 CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 4) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 4 CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA PARAMETER Quiescent Device Current MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 5) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 5. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS P0 - P3 0.25 PE 0.65 CP 1.05 MR 0.8 SPE 0.5 TE 1.05 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. 5 CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS fMAX - 2 6 - - 5 - 4 - MHz 4.5 30 - - 24 - 20 - MHz 6 35 - - 28 - 24 - MHz 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns HC TYPES Maximum CP Frequency (Note 6) CP Width (Low) MR Pulse Width (161) Setup Time, Pn to CP Setup Time, PE or TE to CP Setup Time, SPE to CP Setup Time, MR to CP (163) Hold Time, PN to CP Hold Time, TE or PE to CP Hold Time, SPE to CP Recovery Time, MR to CP (161) tW(L) tW tSU tSU tSU tSU tH tH tH tREC - - - - - - - - - - 2 100 - - 125 - 150 - ns 4.5 20 - - 25 - 30 - ns 6 17 - - 21 - 26 - ns 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns 2 65 - - 80 - 100 - ns 4.5 13 - - 16 - 20 - ns 6 11 - - 14 - 17 - ns 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns 6 0 - - 0 - 0 - ns 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns 6 0 - - 0 - 0 - ns 2 75 - - 95 - 110 - ns 4.5 15 - - 19 - 22 - ns 6 13 - - 16 - 19 - ns 6 CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Prerequisite For Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Maximum CP Frequency fMAX - 4.5 30 - - 24 - 20 - MHz CP Width (Low) (Note 6) tW(L) - 4.5 16 - - 20 - 24 - ns MR Pulse Width (161) tW - 4.5 20 - - 25 - 30 - ns Setup Time, Pn to CP tSU - 4.5 10 - - 13 - 15 - ns Setup Time, PE or TE to CP tSU - 4.5 13 - - 16 - 20 - ns Setup Time, SPE to CP tSU - 4.5 12 - - 15 - 18 - ns Setup Time, MR to CP (163) tSU - 4.5 13 - - 16 - 20 - ns Hold Time, PN to CP tH - 4.5 5 - - 5 - 5 - ns Hold Time, TE or PE to CP tH - 4.5 3 - - 3 - 3 - ns Hold Time, SPE to CP tH - 4.5 3 - - 3 - 3 - ns tREC - 4.5 15 - - 19 - 22 - ns PARAMETER HCT TYPES Recovery Time, MR to CP (161) NOTE: 6. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC devices: 1 1 f MAX (CP) = ----------------------------------------------------------------------------------------------------------------------------------------------------- = ----------------------------- ≈ 21MHz ( min ) CP-to-TC prop. delay + TE-to-CP setup + TE-to-CP Hold 37 + 10 + 0 Switching Specifications CL = 50pF, Input tr, tf = 6ns -40oC TO 85oC 25oC PARAMETER SYMBOL TEST CONDITIONS tPHL, tPLH CL = 50pF -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 39 - 48 ns CL = 50pF 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 39 - 48 ns CL = 50pF 2 - - 120 - 150 - 180 ns 4.5 - - 24 - 30 - 36 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 20 - 26 - 31 ns HC TYPES Propagation Delay CP to TC CP to Qn TE to TC tPHL, tPLH tPHL, tPLH 7 CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC PARAMETER MR to Qn (161) MR to TC (161) Output Transition Time -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPHL CL = 50pF 2 - - 210 - 265 - 315 ns 4.5 - - 42 - 53 - 63 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 6 - - 36 - 45 - 54 ns CL = 50pF 2 - - 210 - 265 - 315 ns 4.5 - - 42 - 53 - 63 ns CL = 50pF 6 - - 36 - 45 - 54 ns CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns tPHL tTHL, tTLH Power Dissipation Capacitance (Notes 7, 8) CPD - 5 - 60 - - - - - pF Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF tPHL, tPLH CL = 50pF 4.5 - - 42 - 53 - 63 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 4.5 - - 39 - 49 - 59 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 4.5 - - 32 - 40 - 48 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns HCT TYPES Propagation Delay CP to TC CP to Qn TE to TC MR to Qn (161) tPHL, tPLH tPHL, tPLH tPHL MR to TC (161) tPHL CL = 50pF 4.5 - - 50 - 63 - 75 ns Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns Power Dissipation Capacitance (Notes 7, 8) CPD - 5 - 63 - - - - - pF Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF NOTES: 7. CPD is used to determine the dynamic power consumption, per package. 8. PD = CPD VCC2 fi + ∑(CL VCC2 fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 8 CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Timing Diagram MASTER RESET (161) (ASYNCHRONOUS) MASTER RESET (163) (SYNCHRONOUS) SPE P0 PRESET DATA INPUTS P1 P2 P3 CP (161) CP (163) COUNT ENABLES PE TE Q0 Q1 OUTPUTS Q2 Q3 TC 12 RESET 13 14 15 0 COUNT PRESET Sequence illustrated on waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. 9 1 2 INHIBIT CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 1.3V 10% INVERTING OUTPUT tPHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tTLH 90% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2.7V 1.3V 0.3V GND tTHL trCL tWH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT INVERTING OUTPUT GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. VCC 90% 50% 10% 1.3V 1.3V tWL tf = 6ns tPHL 1.3V 0.3V 0.3V FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT 2.7V tWH tr = 6ns DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH I fCL 3V GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tREM VCC SET, RESET OR PRESET tfCL = 6ns CLOCK 50% 50% tWL CLOCK INPUT tWL + tWH = trCL = 6ns VCC 90% CLOCK I fCL CL 50pF FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 10 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD54HC161F ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HC161F Samples CD54HC161F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407501EA CD54HC161F3A Samples CD54HC163F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8607601EA CD54HC163F3A Samples CD54HCT163F ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT163F Samples CD54HCT163F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT163F3A Samples CD74HC161E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC161E Samples CD74HC161M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC161M Samples CD74HC161M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC161M Samples CD74HC163E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC163E Samples CD74HC163M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC163M Samples CD74HC163M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC163M Samples CD74HC163MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC163M Samples CD74HCT161E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT161E Samples CD74HCT161EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT161E Samples CD74HCT161M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT161M Samples CD74HCT161M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT161M Samples CD74HCT163E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT163E Samples CD74HCT163M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT163M Samples CD74HCT163M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT163M Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of