CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
CDx4HC251, CDx4HCT251 High-Speed CMOS Logic 8-Input Multiplexer, Three-State
1 Features
2 Description
•
•
•
•
The ’HC251 and ’HCT251 are 8-channel digital
multiplexers with three-state outputs, fabricated with
high-speed silicongate CMOS technology. Together
with the low power consumption of standard CMOS
integrated circuits, they possess the ability to drive
10 LSTTL loads. The three-state feature makes them
ideally suited for interfacing with bus lines in a busoriented system.
•
•
•
•
•
•
•
Selects one of eight binary data inputs
Three-state output capability
True and complement outputs
Typical (data to output) propagation delay of 14 ns
at VCC = 5 V, CL = 15 pF, TA = 25 ℃
Fanout (over temperature range)
– Standard outputs : 10 LSTTL loads
– Bus driver outputs : 15 LSTTL loads
Wide operating temperature range : – 55 ℃ to 125
℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
Alternate source is Philips
HC types
– 2 V to 6 V operation
– High noise immunity : NIL = 30 %, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility, VIL = 0.8
V (Max), VIH = 2 V (Min)
– CMOS input compatibility, II ≤ 1 μA at VOL, VOH
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
CD54HC251F
CDIP (16)
24.38 mm × 6.92 mm
CD54HCT251F
CDIP (16)
24.38 mm × 6.92 mm
CD74HC251M
SOIC (16)
9.90 mm × 3.90 mm
CD74HCT251M
SOIC (16)
9.90 mm × 3.90 mm
CD74HC251E
PDIP (16)
19.31 mm × 6.35 mm
CD74HCT251E
PDIP (16)
19.31 mm × 6.35 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
OE
S0
S1
S2
I0
I1
I2
Y
I3
I4
Y
I5
I6
I7
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
(1)
5.2 Recommended Operating Conditions ..................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Switching Characteristics ...........................................6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Documentation Support.......................................... 12
10.2 Receiving Notification of Documentation Updates..12
10.3 Support Resources................................................. 12
10.4 Trademarks............................................................. 12
10.5 Electrostatic Discharge Caution..............................12
10.6 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2003) to Revision D (March 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
4 Pin Configuration and Functions
J, N, or D Package
16-Pin CDIP, PDIP, or SOIC
Top View
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
(2)
IIK
Input diode current
IOK
Output diode current
IO
Drain current, per output
IO
Output source or sing current per
VO > – 0.5 V or VO < VCC + 0.5 V
output pin
(2)
MIN
MAX
-0.5
7
UNIT
V
VI < 0.5 V or VI > VCC + 0.5 V
±20
mA
VO < – 0.5 V or VO > VCC + 0.5 V
±20
mA
– 0.5 V < VO < VCC + 0.5 V
±25
mA
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
300
°C
-65
Lead temperature (Soldering 10s) (SOIC - lead tips only)
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
5.2 Recommended Operating Conditions
MIN
VCC
Supply voltage range
VI, VO
DC input or output voltage
HC Types
HCT Types
MAX
2
6
V
4.5
5.5
V
VCC
V
0
2V
tt
TA
(1)
Input rise and fall time
UNIT
1000
4.5 V
500
6V
400
Temperature range
– 55
125
ns
℃
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance(1)
D (SOIC)
N (PDIP)
16 PINS
16 PINS
UNIT
67
73
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
5.4 Electrical Characteristics
TEST
CONDITIONS(1)
PARAMETER
VCC
(V)
25°C
MIN
TYP
–40°C to 85°C
MAX
MIN
MAX
–55°C to 125°C
MIN
MAX
UNIT
HC TYPES
VIH
High-level input voltage
VIL
Low-level input voltage
High-level output voltage
CMOS loads
VOH
2
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
V
6
4.2
4.2
4.2
V
2
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
V
6
1.8
1.8
1.8
V
IOH = – 20μA
2
1.9
1.9
1.9
V
IOH = – 20μA
4.5
4.4
4.4
4.4
V
IOH = – 20μA
6
5.9
5.9
5.9
V
IOH = – 6mA
4.5
3.98
3.84
3.7
V
IOH = – 7.8mA
6
5.48
IOL = 20μA
2
0.1
0.1
0.1
V
IOL = 20μA
4.5
0.1
0.1
0.1
V
IOL = 20μA
6
0.1
0.1
0.1
V
Low-level output voltage
TTL loads
IOL = 6mA
4.5
0.26
0.33
0.4
V
IOL = 7.8mA
6
0.26
0.33
0.4
V
II
Input leakage current
VCC or GND
6
±0.1
±1
±1
µA
ICC
Supply current
VCC or GND
6
8
80
160
µA
IOZ
Three-state leakage
current
6
±0.5
±0.5
±10
µA
High-level output voltage
TTL loads
Low-level output voltage
CMOS loads
VOL
5.34
5.2
V
HCT TYPES
VIH
High-level input voltage
4.5 to
5.5
VIL
Low-level input voltage
4.5 to
5.5
2
2
0.8
2
0.8
V
0.8
V
High-level output voltage
CMOS loads
IOH = – 20μA
4.5
4.4
4.4
4.4
V
High-level output voltage
TTL loads
IOH = – 6mA
4.5
3.98
3.84
3.7
V
Low-level output voltage
CMOS loads
IOL = 20μA
4.5
0.1
0.1
0.1
V
Low-level output voltage
TTL loads
IOL = 6mA
4.5
0.26
0.33
0.4
V
II
Input leakage current
VCC and GND
5.5
±0.1
±1
±1
µA
ICC
Supply Current
VCC and GND
5.5
8
80
160
µA
IOZ
Three-state leakage
current
±0.5
±5.0
±10
µA
VOH
VOL
∆ICC (2) (3)
(1)
(2)
(3)
Additional supply current
per input pin
6
S0, S1, S2
4.5 to
5.5
55
198
247.5
269.5
µA
I0 - I7
4.5 to
5.5
50
180
225
245
µA
OE
4.5 to
5.5
265
954
1192.5
1298.5
µA
VI = VIH or VIL, unless otherwise noted.
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA..
Inputs held at VCC – 2.1.
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
5.5 Switching Characteristics
Input tt = 6ns. Unless otherwise specified, CL = 50pF
PARAMETER
VCC (V)
-40°C to
85°C
25°C
TYP
-55°C to
125°C
MAX
MAX
MAX
245
305
370
49
61
74
UNIT
HC TYPES
2
tpd
Select to outputs
tpd
Data to outputs
4.5
21(1)
6
42
52
63
2
175
220
265
35
44
53
30
37
45
140
175
210
28
35
42
6
24
30
36
2
75
95
110
4.5
15
19
22
6
13
16
19
4.5
12(1)
6
2
tpd
Enable to high Z and enable from high Z
tt
Output transition times
4.5
11(1)
ns
ns
ns
ns
Ci
Input capacitance
10
10
10
pF
CO
Three-state output capacitance
15
15
15
pF
Cpd
(3) (4)
Power dissipation capacitance
5
60(2)
pF
HCT TYPES
tpd
Select to outputs
4.5
18(1)
42
53
63
ns
tpd
Data to outputs
4.5
12(1)
35
44
53
ns
12(1)
30
38
45
ns
15
19
22
ns
10
10
10
pF
tpd
Enable to high Z and enable from high Z
4.5
tt
Output transition times
4.5
Ci
Input capacitance
Cpd (3) (4)
Power dissipation capacitance
(1)
(2)
(3)
(4)
6
5
60(2)
pF
Typical value tested at 5V, CL = 15pF.
Typical value tested at 5V.
CPD is used to determine the dynamic power consumption, per channel.
PD = VCC 2fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
Test
Point
S1
RL
From Output
Under Test
CL(1)
S2
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for 3-State Outputs
VCC
Input
50%
VCC
Output
Control
50%
50%
50%
0V
0V
tPHL(1)
tPLH(1)
tPZL(3)
VOH
Output
50%
VOL
tPHL
(1)
tPLH
50%
50%
10%
VOL
(1)
tPZH
VOH
Output
§ 9CC
Output
Waveform 1
S1 at VLOAD(1)
50%
Output
Waveform 2
S1 at GND(2)
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
tPLZ(4)
(3)
tPHZ
(4)
90%
VOH
50%
§0V
(1) tPLZ and tPHZ are the same as tdis.
(2) tPZL and tPZH are the same as ten.
Figure 6-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
Figure 6-3. Voltage Waveforms, Standard CMOS
Inputs Propagation Delays
90%
VCC
90%
Input
10%
10%
tr(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 6-4. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
3V
Input
1.3V
1.3V
3V
Input
1.3V
1.3V
0V
tPLH(1)
VOH
Output
Waveform 1
50%
50%
VOL
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-5. Voltage Waveforms, Propagation
Delays for TTL-Compatible Inputs
8
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Output
Waveform 2
S1 OPEN,
S2 CLOSED
tPLZ(2)
VCC
50%
10%
VOL
tPZH(1)
VOH
50%
Output
Waveform 1
S1 CLOSED,
S2 OPEN
tPLH(1)
tPHL(1)
Output
Waveform 2
0V
tPZL(1)
tPHL(1)
tPHZ(2)
90%
VOH
50%
0V
(1) tPLZ and tPHZ are the same as tdis.
(2) tPZL and tPZH are the same as ten.
Figure 6-6. Voltage Waveforms, TTL-Compatible
CMOS Inputs Propagation Delays
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
7 Detailed Description
7.1 Overview
The ’HC251 and ’HCT251 are 8-channel digital multiplexers with three-state outputs, fabricated with high-speed
silicongate CMOS technology. Together with the low power consumption of standard CMOS integrated circuits,
they possess the ability to drive 10 LSTTL loads. The three-state feature makes them ideally suited for
interfacing with bus lines in a bus-oriented system.
This multiplexer features both true (Y) and complement (Y) outputs as well as an output enable (OE) input.
The OE must be at a low logic level to enable this device. When the OE input is high, both outputs are in
the high-impedance state. When enabled, address information on the data select inputs determines which data
input is routed to the Y and Y outputs. The ’HCT251 logic family is speed, function, and pin-compatible with the
standard ’LS251.
7.2 Functional Block Diagram
OE
S0
S1
S2
I0
I1
I2
Y
I3
I4
Y
I5
I6
I7
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
7.3 Device Functional Modes
Table 7-1. Truth Table(1)
INPUTS
OUTPUT
SELECT
(1)
10
S2
S1
S0
OUTPUT CONTROL OE
Y
Y
X
X
X
H
Z
Z
L
L
L
L
I0
I0
L
L
H
L
I1
I1
L
H
L
L
I2
I2
L
H
H
L
I3
I3
H
L
L
L
I4
I4
H
L
H
L
I5
I5
H
H
L
L
I6
I6
H
H
H
L
I7
I7
H = High voltage level.
L = Low voltage level.
X = Dont care.
Z = High impedance (Off).
I0, I1… I7 = The level of the respective input.
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SCHS169D – NOVEMBER 1998 – REVISED MARCH 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9052401MEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9052401ME
A
CD54HCT251F3A
CD54HC251F
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC251F
Samples
CD54HC251F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8512501EA
CD54HC251F3A
Samples
CD54HCT251F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9052401ME
A
CD54HCT251F3A
CD74HC251E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC251E
Samples
CD74HC251M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC251M
Samples
CD74HC251M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC251M
Samples
CD74HC251MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC251M
Samples
CD74HCT251E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT251E
Samples
CD74HCT251M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT251M
Samples
CD74HCT251M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT251M
Samples
CD74HCT251MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT251M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of