CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry
1 Features
2 Description
•
•
•
•
•
The CDx4HC283 and CDx4HCT283 contain 4-bit
binary adders. The HCT device has TTL-voltage
compatible inputs.
•
•
•
•
•
Adds two binary numbers
Full internal lookahead
Fast ripple carry for economical expansion
Operates with both positive and negative logic
Fanout (over temperature range)
– Standard outputs 10 LSTTL loads
– Bus driver outputs 15 LSTTL loads
Wide operating temperature range: –55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
Logic ICs
HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility,
VIL = 0.8 V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 µA at VOL, VOH
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD54HC283
J (CDIP, 16)
24.38 mm × 6.92 mm
CD74HC283CD74H D (SOIC, 16)
C283
N (PDIP, 16)
9.90 mm × 3.90 mm
CD74HCT283CD74 D (SOIC, 16)
HCT283
N (PDIP, 16)
9.90 mm × 3.90 mm
(1)
19.31 mm × 6.35 mm
19.31 mm × 6.35 mm
For all packages see the orderable addendum at the end of
the datasheet.
Functional Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings(1) .................................... 4
5.2 Recommended Operating Conditions ........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Switching Characteristics ...........................................6
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2003) to Revision E (July 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
4 Pin Configuration and Functions
J, N, or D package
16-Pin CDIP, PDIP, or SOIC
Top View
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
5 Specifications
5.1 Absolute Maximum Ratings(1)
VCC
Supply voltage
MIN
MAX
– 0.5
7
UNIT
V
IIK
Input diode current
For VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IOK
Output diode current
For VO < –0.5 V or VO > VCC + 0.5 V
±20
mA
IO
Drain current, per output
For –0.5 V < VO < VCC + 0.5 V
±25
mA
IO
Output source or sink current per output pin
For VO > –0.5 V or VO < VCC + 0.5 V
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature range
150
°C
300
°C
– 65
Lead temperature (Soldering 10s)(SOIC - lead tips only)
(1)
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.
5.2 Recommended Operating Conditions
VCC
Supply voltage range
VI, VO
DC input or output voltage
MIN
MAX
2
6
V
VCC
V
HC types
0
2V
Input rise and fall time
TA
UNIT
1000
4.5 V
500
6V
400
Temperature range
–55
ns
125
V
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance
(1)
D (SOIC)
N (PDIP)
16 PINS
16 PINS
UNIT
73
67
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
5.4 Electrical Characteristics
PARAMETER
TEST
CONDITIONS(2)
VCC
(V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
High level input
voltage
VIH
Low level input
voltage
VIL
High level output
voltage
VOH
Low level output
voltage
VOL
2
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6
4.2
4.2
V
4.2
2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6
1.8
1.8
1.8
IOH = –20 μA
2
1.9
1.9
1.9
IOH = –20 μA
4.5
4.4
4.4
4.4
V
V
IOH = –20 μA
6
5.9
5.9
5.9
IOH = –4 mA
4.5
3.98
3.84
3.7
IOH = –5.2 mA
6
6
5.34
5.2
IOL = 20 μA
2
0.1
0.1
0.1
IOL = 20 μA
4.5
0.1
0.1
0.1
IOL = 20 μA
6
0.1
0.1
0.1
V
IOL = 4 mA
4.5
0.26
0.33
0.4
IOL = 5.2 mA
6
0.26
0.33
0.4
V
V
II
Input leakage
current
VCC or GND
6
±0.1
±1
±1
µA
ICC
Supply current
VCC or GND
6
8
80
160
µA
HCT Types
VIH
High level input
voltage
4.5 to
5.5
VIL
Low level input
voltage
4.5 to
5.5
VOH
2
2
0.8
2
0.8
0.8
IOH = – 20 μA
4.5
4.4
IOH = – 4 mA
4.5
3.98
4.5
0.1
0.1
0.1
V
VOL
Low level output
voltage
IOL = 20 μA
IOL = 4 mA
4.5
0.26
0.33
0.4
V
II
Input leakage
current
VCC to GND
5.5
±0.1
±1
±1
µA
ICC
Supply current
VCC or GND
5.5
8
80
160
µA
CIN input held at
VCC – 2.1
4.5 to
5.5
100
540
675
735
µA
B1, A1, A0 inputs
held at VCC – 2.1
4.5 to
5.5
100
360
450
490
µA
B0 input held at
VCC – 2.1
4.5 to
5.5
100
144
180
196
µA
B3, A3, A2, B2
inputs held at VCC –
2.1
4.5 to
5.5
100
180
225
245
µA
VOL
ΔICC
(1)
(2)
(1)
Additional supply
current per input pin
4.4
V
High level output
voltage
VOH
4.4
V
3.84
V
3.7
V
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
VI = VIH or VIL, unless otherwise noted.
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
5.5 Switching Characteristics
TEST
CONDITIONS
PARAMETER
VCC (V)
25℃
MIN
TYP
–40 to 85℃
MAX
MIN
–55℃ to 125℃
MAX
MIN
MAX
UNIT
HC TYPES
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
CL = 50 pF
Propagation delay
CIN to S0
27
34
41
2
180
225
270
4.5
36
45
54
13
CL = 15 pF
5
CL = 50 pF
6
31
38
46
2
195
245
295
4.5
39
49
59
15
CL = 15 pF
5
CL = 50 pF
6
33
42
50
2
230
290
345
4.5
46
58
69
16
CL = 15 pF
5
CL = 50 pF
6
39
49
59
2
195
245
295
4.5
39
49
59
19
CL = 15 pF
5
CL = 50 pF
6
33
42
50
2
210
265
315
4.5
42
53
63
CL = 5 0pF
An, Bn to Sn
45
6
CL = 50 pF
An, Bn to COUT
240
40
CL = 50 pF
CL = 50 pF
CIN to S3
200
32
5
CL = 50 pF
CIN to S2, CIN to COUT
160
CL = 15 pF
CL = 50 pF
CIN to S1
2
4.5
16
CL = 15 pF
5
CL = 50 pF
6
36
45
54
2
75
95
110
4.5
15
19
22
6
13
16
19
-
10
10
10
tTLH,
tTHL
Output transition time
CL = 50 pF
CIN
Input capacitance
CL = 50 pF
CPD
Power dissipation
capacitance(1) (2)
18
5
70
CL = 15 pF
5
13
CL = 50 pF
4.5
ns
ns
ns
ns
ns
ns
ns
pF
pF
HCT TYPES
6
tPLH,
tPHL
Propagation delay
CIN to S0
tPLH,
tPHL
CIN to S1
tPLH,
tPHL
CIN to S2, CIN to COUT
tPLH,
tPHL
CIN to S3
tPLH,
tPHL
An, Bn to COUT
tPLH,
tPHL
An, Bn to Sn
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CL = 15 pF
5
CL = 50 pF
4.5
CL = 15 pF
5
CL = 50 pF
4.5
CL = 15 pF
5
CL = 50 pF
4.5
CL = 15 pF
5
CL = 50 pF
4.5
CL = 15 pF
5
CL = 50 pF
4.5
31
39
47
43
54
65
46
58
69
53
66
80
48
60
72
49
61
74
18
19
22
20
21
ns
ns
ns
ns
ns
ns
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
5.5 Switching Characteristics (continued)
PARAMETER
tTLH,
tTHL
Output transition time
CIN
Input capacitance
CPD
Power dissipation
capacitance(1) (2)
(1)
(2)
TEST
CONDITIONS
VCC (V)
CL = 50 pF
4.5
5
25℃
MIN
TYP
–40 to 85℃
MAX
MIN
–55℃ to 125℃
MAX
MIN
MAX
UNIT
15
19
22
ns
10
10
10
pF
82
pF
CPD is used to determine the dynamic power consumption, per package.
PD = VCC 2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
6 Parameter Measurement Information
Test
Point
From Output
Under Test
CL(1)
1. Includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Output
Figure 6-2. HC and HCT Transition Times and
Propagation Delay Times, Combination Logic
Figure 6-3. HCT Transition Times and Propagation Delay Times, Combination Logic
1. The greater between tr and tf is the same as tt.
2. The greater between tplh and tphl is the same as tpd.
8
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
7 Detailed Description
7.1 Overview
The ’HC283 and ’HCT283 binary full adders add two 4-bit binary numbers and generate a carry-out bit if the sum
exceeds 15.
Because of the symmetry of the add function, this device can be used with either all active-high operands
(positive logic) or with all active-low operands (negative logic). When using positive logic the carry-in input must
be tied low if there is no carry-in.
7.2 Functional Block Diagram
7.3 Feature Description
•
•
Balanced CMOS Push-Pull Outputs
Clamp Diode Structure
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
10
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SCHS176E – NOVEMBER 1997 – REVISED JULY 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8976501EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8976501EA
CD54HC283F3A
Samples
CD54HC283F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8976501EA
CD54HC283F3A
Samples
CD54HCT283F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HCT283F3A
Samples
CD74HC283E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC283E
Samples
CD74HC283M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC283M
Samples
CD74HC283M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC283M
Samples
CD74HC283ME4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC283M
Samples
CD74HC283MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC283M
Samples
CD74HCT283E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT283E
Samples
CD74HCT283M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT283M
Samples
CD74HCT283M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT283M
Samples
CD74HCT283MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT283M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of