CD54HC365, CD74HC365, CD54HCT365
CD74HCT365, CD54HC366, CD74HC366
SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and
Inverting
Device Information
1 Features
•
•
•
•
•
•
•
•
•
Buffered inputs
High current bus driver outputs
Typical propagation delay tPLH, tPHL = 8 ns
at VCC = 5 V, CL = 15 pF, TA = 25℃
Fanout (over temperature range)
– Standard outputs: 10 LSTTL Loads
– Bus driver outputs: 15 LSTTL Loads
Wide operating temperature range: -55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
Logic ICs
HC types
– 2 V to 6 V operation
– High Noise Immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility,
VIL = 0.8 V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1µA at VOL,VOH
PACKAGE(1)
BODY SIZE (NOM)
CD54HC365
J (CERDIP, 16)
19.56 x 6.92 mm
CD54HC366
J (CERDIP, 16)
19.56 x 6.92 mm
CD54HCT365
J (CERDIP, 16)
19.56 x 6.92 mm
N (PDIP, 16)
19.30 x 6.35 mm
D (SOIC, 16)
9.90 x 3.90 mm
D (SOIC, 16)
9.90 x 3.90 mm
D (SOIC, 16)
9.90 x 3.90 mm
N (PDIP, 16)
19.30 x 6.35 mm
D (SOIC, 16)
9.90 x 3.90 mm
D (SOIC, 16)
9.90 x 3.90 mm
N (PDIP, 16)
19.30 x 6.35 mm
D (SOIC, 16)
9.90 x 3.90 mm
D (SOIC, 16)
9.90 x 3.90 mm
D (SOIC, 16)
9.90 x 3.90 mm
PART NUMBER
CD74HC365
CD74HC366
CD74HCT365
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
2 Description
The ’HC365, ’HCT365, and ’HC366 silicon gate
CMOS three-state buffers are general purpose highspeed non-inverting and inverting buffers.
Logic Diagram for the HC/HCT365 and HC366 (Outputs for HC/HCT365 are Complements of Those
Shown, i.e., 1Y, 2Y, etc.)
A.
Inverter not included in HC/HCT 365.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC365, CD74HC365, CD54HCT365
CD74HCT365, CD54HC366, CD74HC366
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings(1) .................................... 4
5.2 Operating Conditions.................................................. 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 HCT Input Loading Table............................................ 6
5.6 Switching Characteristics ...........................................6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes............................................8
8 Power Supply Recommendations..................................9
9 Layout...............................................................................9
9.1 Layout Guidelines....................................................... 9
10 Device and Documentation Support..........................10
10.1 Receiving Notification of Documentation Updates..10
10.2 Support Resources................................................. 10
10.3 Trademarks............................................................. 10
10.4 Electrostatic Discharge Caution..............................10
10.5 Glossary..................................................................10
11 Mechanical, Packaging, and Orderable
Information.................................................................... 10
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2003) to Revision D (July 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
4 Pin Configuration and Functions
Figure 4-1. CD54HC365, CD54HCT365, CD54HC366 (CERDIP) CD74HC365, CD74HCT365, CD74HC366
(PDIP, SOIC) Top View
Table 4-1. Pin Functions
PIN
NO.
NAME
1
OE1
2
3
4
5
6
7
TYPE(1)
DESCRIPTION
I
Output Enable 1, Active Low
1A
I
1A Input
1Y
O
1Y Output
2A
I
2A Input
2Y
O
2Y Output
3A
I
3A Input
3Y
O
3Y Output
8
GND
—
Ground Pin
9
4Y
O
4Y Output
10
4A
I
4A Input
11
5Y
O
5Y Output
12
5A
I
5A Input
13
6Y
O
6Y Output
14
6A
I
6A Input
15
OE2
I
Output Enable 2, Active Low
16
VCC
—
(1)
Power Pin
Signal Types: I = Input, O = Output, I/O = Input or Output.
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
5 Specifications
5.1 Absolute Maximum Ratings(1)
MIN
MAX
-0.5
7
UNIT
VCC
DC supply voltage
IIK
DC input diode current
For VI < -0.5 V or VI > VCC
+ 0.5 V
±20
mA
IOK
DC output diode current
For VO < -0.5 V or VO >
VCC + 0.5
±20
mA
IO
DC drain current, per output
For -0.5 V < VO < VCC +
0.5 V
±35
mA
IO
DC output source or sink current per output pin
For VO > -0.5 V or VO <
VCC + 0.5 V
±25
mA
ICC
DC VCC or ground current
±50
mA
TJ
Maximum junction temperature
150
℃
Tstg
Maximum storage temperature range
150
℃
300
℃
-65
Maximum lead temperature (soldering 10s)SOIC - lead tips
only
(1)
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 Operating Conditions
MIN
VCC
Supply voltage range
VI, VO
DC input or output voltage
HC Types
HCT Types
MAX
2
6
V
4.5
5.5
V
VCC
V
0
2V
Input rise and fall time
TA
1000
4.5 V
500
6V
400
Temperature range
UNIT
-55
125
ns
℃
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance
(1)
N (PDIP)
D (SOIC)
16 PINS
16 PINS
UNIT
67
73
°C/W
The package thermal impedance is calculated in accordance with JESD 51 - 7
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
5.4 Electrical Characteristics
PARAMETER
TEST CONDITIONS
VI (V)
IO (mA)
VCC
(V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to
125℃
MIN
UNIT
MAX
HC TYPES
VIH
VIL
High level input voltage
Low level input voltage
2
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6
4.2
4.2
4.2
2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6
VOH
High level output voltage CMOS
loads
VIH or VIL
High level output voltage TTL
loads
VOL
Low level output voltage CMOS
loads
Low level output voltage TTL
loads
VIH or VIL
VIH or VIL
V
1.8
1.8
V
1.8
-0.02
2
1.9
1.9
1.9
-0.02
4.5
4.4
4.4
4.4
-0.02
6
5.9
5.9
5.9
-6
4.5
3.98
3.84
3.7
-7.8
6
5.48
5.34
5.2
V
0.02
2
0.1
0.1
0.1
0.02
4.5
0.1
0.1
0.1
0.02
6
0.1
0.1
0.1
6
4.5
0.26
0.33
0.4
7.8
6
0.26
0.33
0.4
6
±0.1
±1
±1
μA
V
II
Input leakage current
VCC or
GND
ICC
Quiescent device current
VCC or
GND
0
6
8
80
160
μA
IOZ
Three-state leakage current
VIH or VIL
VO = VCC or
GND
6
±0.5
±5
±10
μA
HCT TYPES
VIH
High level input voltage
4.5 to
5.5
VIL
Low level input voltage
4.5 to
5.5
VOH
VOL
High level output voltage CMOS
loads
High level output voltage TTL
loads
Low level output voltage CMOS
loads
Low level output voltage TTL
loads
2
2
0.8
2
0.8
V
0.8
-0.02
4.5
4.4
4.4
4.4
-4
4.5
3.98
3.84
3.7
0.02
4.5
0.1
0.1
0.1
4
4.5
0.26
0.33
0.4
VIH or VIL
V
V
VIH or VIL
V
II
Input leakage current
VCC or
GND
0
5.5
±0.1
±1
±1
μA
ICC
Quiescent device current
VCC or
GND
0
5.5
8
80
160
μA
ΔICC
Additional supply current per input
pin: 1 Unit Load(1)
VCC - 2.1
360
450
490
μA
IOZ
Three-state leakage current
VIL or VIH
±0.5
±5
±10
μA
(1)
4.5 to
5.5
VO = VCC or
GND
5.5
100
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
5.5 HCT Input Loading Table
Unit Loads(1)
Input
(1)
OE1
0.6
All others
0.55
Unit Load is ΔICC limit specified in Section 5.4, e.g., 360 µA max at 25℃.
5.6 Switching Characteristics
tr, tf = 6 ns
PARAMETER
TEST
CONDITIONS
VCC (V)
CL = 50 pF
25℃
TYP
40℃ to 85℃
55℃ to 125℃
UNIT
MAX
MAX
MAX
2
105
130
160
ns
4.5
21
26
32
ns
18
22
27
ns
HC TYPES
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
Propagation delay, data to
outputs
HC/HCT 365
Propagation delay, data to
outputs
HC 366
Propagation delay time, output
enable and disable to outputs
6
CL = 15 pF
5
8
2
110
140
165
ns
CL = 50 pF
4.5
22
28
33
ns
19
24
28
ns
6
ns
CL = 15 pF
5
9
2
150
190
225
ns
CL = 50 pF
4.5
30
38
45
ns
26
33
38
ns
6
ns
CL = 15 pF
5
12
ns
2
60
75
90
ns
CL = 50 pF
4.5
12
15
18
ns
6
tTLH, tTHL
Output transition time
10
13
15
ns
CI
Input capacitance
10
10
10
pF
CO
Three-state ouput capacitance
20
20
20
pF
Power dissipation capacitance(1)
CPD
5
(2)
40
pF
HCT TYPES
tPLH, tPHL
CL = 50 pF
4.5
CL = 15 pF
5
25
31
38
ns
ns
ns
9
ns
Propagation delay, data to
outputs
HC 366
CL = 50 pF
4.5
tPLH, tPHL
CL = 15 pF
5
tPLH, tPHL
Propagation delay time, output
enable and disable to ouputs
CL = 50 pF
4.5
CL = 15 pF
5
tTLH, tTHL
Output transition time
CL = 50 pF
4.5
12
15
18
ns
CIN
Input capacitance
10
10
10
pF
CO
Three-stage capacitance
20
20
20
pF
CPD
(1)
(2)
6
Propagation delay, data to
outputs
HC/HCT 365
Power dissipation capacitance(1)
(2)
5
27
34
41
11
ns
ns
35
44
53
14
ns
ns
42
pF
CPD is used to determine the dynamic power consumption, per buffer.
PD = VCC 2 fi (CPD + CI) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
6 Parameter Measurement Information
Figure 6-1. HC Transition Times and Propagation
Delay Times, Combination Logic
Figure 6-3. HC Three-State Propagation Delay
Waveform
A.
Figure 6-2. HCT Transition Times and Propagation
Delay Times, Combination Logic
Figure 6-4. HCT Three-State Propagation Delay
Waveform
Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is output RL = 1 kΩ to VCC,
CL = 50 pF.
Figure 6-5. HC and HCT Three-State Propagation Delay Test Circuit
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
7 Detailed Description
7.1 Overview
The ’HC365, ’HCT365, and ’HC366 silicon gate CMOS three-state buffers are general purpose high-speed noninverting and inverting buffers. They have high drive current outputs which enable high speed operation even
when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet
have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low
power Schottky inputs.
The ’HC365 and ’HCT365 are non-inverting buffers, whereas the ’HC366 is an inverting buffer. These devices
have two three-state control inputs (OE1 and OE2) which are NORed together to control all six gates.
The ’HCT365 logic families are speed, function and pin compatible with the standard LS logic family.
7.2 Functional Block Diagram
Functional Diagrams
HC366
HC365, HCT365
7.3 Device Functional Modes
Table 7-1. Function Table
INPUTS(1)
(1)
(2)
8
OUTPUTS (Y)(2)
OE 1
OE 2
A
HC/HCT 365
HCT 366
L
L
L
L
H
L
L
H
H
L
X
H
X
Z
Z
H
X
X
Z
Z
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
H = Driving High, L = Driving Low, Z = High Impedance State
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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SCHS180D – NOVEMBER 1997 – REVISED JULY 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD54HC365F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8500101EA
CD54HC365F3A
Samples
CD54HC366F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8682801EA
CD54HC366F3A
Samples
CD54HCT365F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HCT365F3A
Samples
CD74HC365E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC365E
Samples
CD74HC365M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC365M
Samples
CD74HC365M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC365M
Samples
CD74HC365MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC365M
Samples
CD74HC366E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC366E
Samples
CD74HC366M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC366M
Samples
CD74HC366M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC366M
Samples
CD74HCT365E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT365E
Samples
CD74HCT365M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT365M
Samples
CD74HCT365M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT365M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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14-Oct-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of