CD74HC366QDRQ1

CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 CDx4HC365-Q1, CD74HC366-Q1 High-Speed CMOS Logic HEX Buffer/Line Driver, Three-State Non-Inverting and Inverting 1 Features 2 Description • • • • The CD74HC365-Q1, CD74HC366-Q1, and CD74HCT365-Q1 silicon gate CMOS three state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. • • • • • • Qualified for automotive applications Buffered inputs High current bus driver outputs Typical propagation delay tPLH, tPHL = 8 ns at VCC = 5 V, CL = 15 pF, TA = 25°C Fanout (over temperature range) – Standard outputs – 10 LSTTL loads – Bus driver outputs – 15 LSTTL loads Wide operating temperature range: –40°C to 125°C Balanced propagation delay and transition times Significant power reduction compared to LSTTL logic ICs HC types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL= 0.8 V (maximum), VIH = 2 V (minimum) – CMOS input compatibility, Il ≤ 1 μA at VOL, VOH Device Information PART NUMBER (1) PACKAGE CD74HC366QDRQ1 D (SOIC, 16) (1) BODY SIZE (NOM) 9.90 mm × 3.90 mm For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 ESD Ratings............................................................... 4 5.3 Recommended Operating Conditions.........................4 5.4 Thermal Information....................................................4 5.5 Electrical Characteristics.............................................5 5.6 Switching Characteristics............................................6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Device Functional Modes..........................................10 8 Power Supply Recommendations................................11 9 Layout............................................................................. 11 9.1 Layout Guidelines..................................................... 11 10 Device and Documentation Support..........................12 10.1 Receiving Notification of Documentation Updates..12 10.2 Support Resources................................................. 12 10.3 Trademarks............................................................. 12 10.4 Electrostatic Discharge Caution..............................12 10.5 Glossary..................................................................12 11 Mechanical, Packaging, and Orderable Information.................................................................... 12 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (January 2010) to Revision A (August 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 4 Pin Configuration and Functions D Package 16-Pin SOIC Top View Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 Submit Document Feedback 3 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX -0.5 7 UNIT VCC Supply voltage range IIK Input clamp current VI < -0.5V or VI > VCC + 0.5V ±20 mA IOK Output clamp current VO < -0.5V or VO > VCC + 0.5V ±20 mA Drain current IO Continuous output current ICC V ±35 VO > -0.5V or VO < VCC + 0.5V mA ±25 Continuous current through VCC or GND ±50 mA Latch up Class I TJ Junction temperature Tstg Storage temperature -65 Lead temperature (soldering 10s) (1) 150 °C 150 °C 300 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 1500 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 250 Machine model 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 5.3 Recommended Operating Conditions MIN HC Types 2 6 4.5 5.5 Input voltage 0 VCC V Output voltage 0 VCC V 125 °C VCC Supply voltage VI VO TA Operating free-air temperature HCT Types –40 2V Δt/Δv MAX UNIT Input Rise and Fall Time V 1000 4.5 V 500 6V 400 ns 5.4 Thermal Information D (SOIC) THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance (1) 16 PINS UNIT 73 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 5.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS(2) PARAMETER VCC (V) 25°C MIN TYP -40°C TO 125°C MAX MIN MAX UNITS HC Types VIH High-level input voltage VIL Low-level input voltage High-level output voltage loads VOH CMOS TTL Low-level output voltage loads VOL CMOS TTL II Input leakage current ICC Supply current IOZ Three-state leakage current IOH = –20 μA 2 1.5 1.5 4.5 3.15 3.15 6 4.2 V 4.2 2 0.5 0.5 4.5 1.35 1.35 6 1.8 1.8 2 1.9 1.9 4.5 4.4 4.4 6 5.9 5.9 V V IOH = –6 mA 4.5 3.98 3.7 IOH = –7.8 mA 6 5.48 5.2 2 0.1 0.1 IOL = 20 μA 4.5 0.1 0.1 6 0.1 0.1 IOL = 6 mA 4.5 0.26 0.4 V IOL = 7.8 mA 6 0.26 0.4 VI = VCC or GND 6 ±0.1 ±1 μA VI = VCC or GND; Io =0A 6 8 160 μA VO = VCC or GND 6 ±0.5 ±10 μA HCT Types VIH High-level input voltage 4.5 to 5.5 VIL Low-level input voltage 4.5 to 5.5 VOH High-level output voltage loads IOH = – 20 μA 4.5 4.4 4.4 IOH = – 4 mA 4.5 3.98 3.7 VOL Low-level output voltage loads IOL = 20 μA 4.5 0.1 0.1 IOL = 4 mA 4.5 0.26 0.4 II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 μA ICC Supply current VI = VCC or GND 5.5 8 160 μA ΔICC Additional supply current per input pin: 1 unit load(1) VCC - 2.1 4.5 to 5.5 360 490 μA IOZ Three-state leakage current VO = VCC or GND 5.5 ±0.5 ±10 μA (1) (2) 2 2 0.8 100 V 0.8 V V V For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. VI = VIH or VIL, unless otherwise specified. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 Submit Document Feedback 5 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 5.6 Switching Characteristics CL = 50pF. Input tr, tf = 6ns PARAMETER VCC (V) -40°C TO 125°C 25°C TYP MAX MAX 2 110 165 4.5 22 33 UNITS HC Types HC365 tPLH, tPHL Propagation delay, data to outputs HC366 tTLH, tTHL Output transition time CI Input capacitance CO Three-state output capacitance CPD Power dissipation capacitance(1) (2) 6 19 28 2 150 225 4.5 31 45 6 26 38 ns 2 60 90 4.5 12 18 6 10 15 10 10 pF 20 20 pF 5 40 ns pF HCT Types HCT365 4.5 25 38 HCT366 4.5 27 41 Propagation delay, output enable and disable to outputs 4.5 35 53 tTLH, tTHL Output transition time 4.5 12 18 ns CI Input capacitance 10 10 pF CO Three-state output capacitance 20 20 pF CPD Power dissipation capacitance(1) (2) tPLH, tPHL Propagation delay, data to outputs tPLH, tPHL (1) (2) 6 5 42 ns ns pF CPD is used to determine the dynamic power consumption, per inverter. PD = VCC 2 × fi (CPD + CL), where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. VCC Test Point S1 RL From Output Under Test CL(1) S2 (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for 3-State Outputs VCC Input 50% VCC Output Control 50% 50% 50% 0V 0V tPHL(1) tPLH(1) tPZL(3) VOH Output 50% VOL tPHL (1) tPLH 50% 50% 10% VOL (1) tPZH VOH Output § 9CC Output Waveform 1 S1 at VLOAD(1) 50% Output Waveform 2 S1 at GND(2) 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. tPLZ(4) (3) tPHZ (4) 90% VOH 50% §0V (1) tPLZ and tPHZ are the same as tdis. (2) tPZL and tPZH are the same as ten. Figure 6-2. Voltage Waveforms, Standard CMOS Inputs Setup Propagation Delays Figure 6-3. Voltage Waveforms, Standard CMOS Inputs Propagation Delays 90% VCC 90% Input 10% 10% tr(1) 0V tf(1) 90% VOH 90% Output 10% 10% tr(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. Figure 6-4. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Input Devices Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 Submit Document Feedback 7 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 3V Input 1.3V 1.3V 3V Input 1.3V 1.3V 0V tPLH(1) VOH Output Waveform 1 50% 50% VOL 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-5. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays 8 Submit Document Feedback Output Waveform 2 S1 OPEN, S2 CLOSED tPLZ(2)
VCC 50% 10% VOL tPZH(1) VOH 50% Output Waveform 1 S1 CLOSED, S2 OPEN tPLH(1) tPHL(1) Output Waveform 2 0V tPZL(1) tPHL(1) tPHZ(2) 90% VOH 50% 0V (1) tPLZ and tPHZ are the same as tdis. (2) tPZL and tPZH are the same as ten. Figure 6-6. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 7 Detailed Description 7.1 Overview The CD74HC365-Q1, CD74HC366-Q1, and CD74HCT365-Q1 silicon gate CMOS three state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. The CD74HC365-Q1 and CD74HCT365-Q1 are non-inverting buffers, whereas the CD74HC366-Q1 is an inverting buffer. These devices have two three-state control inputs (OE1 and OE2) which are NORed together to control all six gates. The ’HCT365-Q1 logic families are speed, function and pin compatible with the standard LS logic family. 7.2 Functional Block Diagram Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 Submit Document Feedback 9 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 7.3 Device Functional Modes Table 7-1. Function Table INPUTS(1) (1) (2) 10 OUTPUTS (Y)(2) OE1 OE2 A HC/HCT365 HC366 L L L L H L L H H L X H X Z Z H X X Z Z H = High Voltage Level, L = Low Voltage Level, X = Don’t Care H = Driving High, L = Driving Low, Z = High Impedance State Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 Submit Document Feedback 11 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382A – JANUARY 2010 – REVISED AUGUST 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD74HC366QDRQ1 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC366Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of