CD74HC367MG4

CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 CDx4HC367, CDx4HC368, CDx4HCT367, CD74HCT368 High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting 1 Features 2 Description • • • • The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. The ’HC367 and ’HCT367 are non-inverting buffers, whereas the ’HC368 and CD74HCT368 are inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. • • • • • • Buffered inputs High current bus driver outputs Two independent three-state enable controls Typical propagation delay tPLH, tPHL = 8 ns at VCC = 5 V, CL =15 pF, TA = 25℃ Fanout (over temperature range) – Standard outputs: 10 LSTTL Loads – Bus driver outputs: 15 LSTTL Loads Wide operating temperature range: -55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC Types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT Types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min) – CMOS input compatibility, II ≤ 1 μA at VOL, VOH Device Information PACKAGE BODY SIZE (NOM) CD74HC367M SOIC (16) 9.90 mm × 3.90 mm CD74HC368M SOIC (16) 9.90 mm × 3.90 mm CD74HCT367M SOIC (16) 9.90 mm × 3.90 mm CD74HCT368M SOIC (16) 9.90 mm × 3.90 mm CD74HC367E PDIP (16) 19.31 mm × 6.35 mm CD74HC368E PDIP (16) 19.31 mm × 6.35 mm CD74HCT367E PDIP (16) 19.31 mm × 6.35 mm CD74HCT368E PDIP (16) 19.31 mm × 6.35 mm CD54HC367F3A CDIP (16) 24.38 mm × 6.92 mm CD54HC368F3A CDIP (16) 24.38 mm × 6.92 mm CD54HCT367F3A CDIP (16) 24.38 mm × 6.92 mm (1) 1OE 1A1 1A2 1A3 1A4 1 2OE 2 3 4 5 6 7 9 10 (1) PART NUMBER 1Y1 2A1 1Y2 2A2 For all available packages, see the orderable addendum at the end of the data sheet. 15 12 11 14 13 2Y1 2Y2 1Y3 1Y4 Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics............................................6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Receiving Notification of Documentation Updates..10 10.2 Support Resources................................................. 10 10.3 Trademarks............................................................. 10 10.4 Electrostatic Discharge Caution..............................10 10.5 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2003) to Revision E (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 4 Pin Configuration and Functions 'HC367, 'HCT367 J, D, or N package 16-Pin CDIP, SOIC, PDIP Top View Copyright © 2022 Texas Instruments Incorporated 'HC368, CD74HCT368 J, D, or N package 16-Pin CDIP, SOIC, PDIP Top View Submit Document Feedback Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 3 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX -0.5 7 UNIT VCC Supply voltage range IIK Input clamp current (VI < -0.5 V or VI > VCC + 0.5 V) ±20 mA IOK Output clamp current (VO < -0.5 V or VO > VCC + 0.5 V) ±20 mA IO Continuous output current (-0.5 V < VO < VCC + 0.5 V) ±35 mA ±50 mA 150 °C 150 °C 300 °C Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature -65 Lead Temperature (Soldering 10s) (1) V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions TA Temperature range VCC Supply voltage range VI,VO Input or output voltage HC Types HCT Types MIN MAX UNIT –55 125 ℃ 2 6 V 4.5 5.5 V 0 VCC V 1000 ns 4.5 V 500 ns 6V 400 ns 2V tt Input rise and fall time 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance (1) D (SOIC) N (PDIP) 16 PINS 16 PINS UNIT 73 67 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS (2) VCC (V) 25℃ MIN TYP -40℃ to 85℃ MAX MIN -55℃ to 125℃ MAX MIN MAX UNIT HC TYPES High level input voltage VIH Low level input voltage VIL High level output voltage VOH High level output voltage Low level output voltage VOL Low level output voltage II Input leakage current ICC Supply current IOZ Three-state leakage current 2 1.5 1.5 1.5 V 4.5 3.15 3.15 3.15 V 6 4.2 4.2 4.2 V 2 0.5 0.5 0.5 V 4.5 1.35 1.35 1.35 V 6 1.8 1.8 1.8 V IOH = – 20 μA 2 1.9 1.9 1.9 V IOH = – 20 μA 4.5 4.4 4.4 4.4 V IOH = – 20 μA 6 5.9 5.9 5.9 V IOH = – 6 mA 4.5 3.98 3.84 3.7 V IOH = – 7.8 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 V IOL = 20 μA 4.5 0.1 0.1 0.1 V IOL = 20 μA 6 0.1 0.1 0.1 V IOL = 6 mA 4.5 0.26 0.33 0.4 V IOL = 7.8 mA 6 0.26 0.33 0.4 V 6 ±0.1 ±1 ±1 μA 0 6 8 80 160 μA VO = VCC or GND 6 ±0.5 ±5.0 ±10 μA 5.34 5.2 V HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 0.8 V 0.8 V 4.5 4.4 4.4 4.4 V High level output voltage IOH = – 4 mA 4.5 3.98 3.84 3.7 V Low level output voltage IOL = 20 μA 4.5 0.1 0.1 0.1 V Low level output voltage IOL = 4 mA 4.5 0.26 0.33 0.4 V VI = VCC to GND 5.5 ±0.1 ±1 ±1 μA 8 80 160 μA ICC Supply current (1) (2) 0.8 2 IOH = – 20 μA Input leakage current IOZ 2 High level output voltage II ΔICC (1) 2 Additional supply current per input pin Three-state leakage current VI = VCC to GND 5.5 OE1 input held at VCC – 2.1 4.5 to 5.5 100 216 270 294 All other inputs held at VCC – 2.1 4.5 to 5.5 100 198 247.5 269.5 VO = VCC or GND 5.5 ±0.5 ±5.0 ±10 μA μA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL, unless otherwise noted. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 5 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 5.5 Switching Characteristics Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF PARAMETER 25℃ VCC (V) TYP MAX -40℃ to 85℃ -55℃ to 125℃ MAX MAX UNIT HC TYPES Data to outputs HC/HCT367 2 105 130 160 ns 4.5 21 26 32 ns 6 8(3) 18 24 27 ns 105 130 160 ns 21 26 32 ns 18 24 27 ns 2 150 190 225 ns 4.5 30 38 45 ns 2 Data to outputs HC/HCT368 tpd 4.5 6 Output enable and disable to outputs tt Output transition time 6 9(3) 12(3) 26 33 38 ns 2 60 75 90 ns 4.5 12 15 18 ns 6 10 13 15 ns CI Input capacitance 10 10 10 pF CO Three-state output capacitance 20 20 20 pF Power dissipation CPD capacitance(1) 5 40 Data to outputs HC/HCT367 4.5 9(3) 25 31 38 ns Data to outputs HC/HCT368 4.5 11(3) 30 38 45 ns Output enable and disable to outputs 4.5 14(3) 35 44 53 ns tt Output transition time 4.5 12 15 18 ns CIN Input capacitance 10 10 10 pF CO Three-state capacitance 20 20 20 pF (2) pF HCT TYPES tpd CPD (1) (2) (3) 6 Power dissipation (2) capacitance(1) 5 42 pF CPD is used to determine the dynamic power consumption, per buffer. PD = VCC 2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 6 Parameter Measurement Information tpd is the maximum between tPLH and tPHL tt is the maximum between tTLH and tTHL Figure 6-1. HC Transition Times and Propagation Delay Times, Combination Logic Figure 6-2. HCT Transition Times and Propagation Delay Times, Combination Logic Figure 6-3. HC Three-State Propagation Delay Waveform Figure 6-4. HCT Three-State Propagation Delay Waveform Note Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1 kΩ to VCC, CL = 50 pF. Figure 6-5. HC and HCT Three-State Propagation Delay Test Circuit Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 7 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 7 Detailed Description 7.1 Overview The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. The ’HC367 and ’HCT367 are non-inverting buffers, whereas the ’HC368 and CD74HCT368 are inverting buffers. These devices have two output enables, one enable (OE1) controls 4 gates and the other (OE2) controls the remaining 2 gates. The ’HCT367 and CD74HCT368 logic families are speed, function and pin compatible with the standard LS logic family. 7.2 Functional Block Diagram 1 1OE 1A1 1A2 1A3 1A4 15 2OE 2 3 4 5 6 7 9 10 1Y1 2A1 1Y2 2A2 12 11 14 13 2Y1 2Y2 1Y3 1Y4 7.3 Device Functional Modes Table 7-1. Truth Table(1) INPUTS OE (1) 8 Submit Document Feedback OUTPUTS (Y) A HC/HCT367 HC/HCT368 L L L H L H H L H X (Z) (Z) H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance (OFF) State Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 9 CD54HC367, CD74HC367, CD54HCT367 CD74HCT367, CD54HC368, CD74HC368, CD74HCT368 www.ti.com SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC367 CD74HC367 CD54HCT367 CD74HCT367 CD54HC368 CD74HC368 CD74HCT368 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9070601MEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9070601ME A CD54HCT367F3A CD54HC367F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8500201EA CD54HC367F3A Samples CD54HC368F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8681201EA CD54HC368F3A Samples CD54HCT367F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9070601ME A CD54HCT367F3A CD74HC367E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC367E Samples CD74HC367M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC367M Samples CD74HC367M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC367M Samples CD74HC367MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC367M Samples CD74HC368E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC368E Samples CD74HC368M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC368M Samples CD74HCT367E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT367E Samples CD74HCT367M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT367M Samples CD74HCT367M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT367M Samples CD74HCT367MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT367M Samples CD74HCT368E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT368E Samples CD74HCT368M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT368M Samples CD74HCT368M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT368M Samples CD74HCT368MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT368M Samples Addendum-Page 1 Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of