CD54HC373, CD74HC373
SCLS452C – FEBRUARY 2001 – REVISED MAY 2022
CDx4HC373 Octal Transparent D-Type Latches With 3-State Outputs
1 Features
2 Description
•
•
The ’HC373 devices are octal transparent D-type
latches designed for 2-V to 6-V VCC operation.
•
•
•
2-V to 6-V VCC operation
Wide operating temperature range of
–55℃ to 125℃
Balanced propagation delays and transition times
Standard outputs drive up to 15 LS-TTL loads
Significant power reduction compared to LS-TTL
Logic ICs
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is low,
the Q outputs are latched at the logic levels of the D
inputs.
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD74HC373M
SOIC (20)
12.80 mm × 7.50 mm
CD74HC373E
PDIP (20)
25.40 mm × 6.35 mm
CD54HC373F
CDIP (20)
26.92 mm × 6.92 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (positive logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC373, CD74HC373
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SCLS452C – FEBRUARY 2001 – REVISED MAY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements ................................................. 5
5.6 Switching Characteristics ...........................................6
5.7 Operating Characteristics........................................... 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes............................................8
8 Power Supply Recommendations..................................9
9 Layout...............................................................................9
9.1 Layout Guidelines....................................................... 9
10 Device and Documentation Support..........................10
10.1 Receiving Notification of Documentation Updates..10
10.2 Support Resources................................................. 10
10.3 Trademarks............................................................. 10
10.4 Electrostatic Discharge Caution..............................10
10.5 Glossary..................................................................10
11 Mechanical, Packaging, and Orderable
Information.................................................................... 10
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2022) to Revision C (May 2022)
Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, N was 69 is now 84.6.... 4
Changes from Revision A (April 2003) to Revision B (January 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS452C – FEBRUARY 2001 – REVISED MAY 2022
4 Pin Configuration and Functions
OE
1
20
1Q
2
19
8Q
1D
3
18
8D
7D
VCC
2D
4
17
2Q
5
16
7Q
3Q
6
15
6Q
6D
3D
7
14
4D
8
13
5D
4Q
9
12
5Q
10
11
LE
GND
J, N, or DW package
20-Pin CDIP, PDIP, or SOIC
Top View
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SCLS452C – FEBRUARY 2001 – REVISED MAY 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
± 20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
± 20
mA
IO
Continuous output drain current per output
VO = 0 to VCC
± 35
mA
IO
Continuous output source or sink current per output
VO = 0 to VCC
± 25
mA
Continuous current through VCC or GND
± 50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature range
150
°C
(1)
(2)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
6
VCC = 4.5 V
VI
Input voltage
VO
Output voltage
4.2
0.5
VCC = 4.5 V
1.35
VCC = 6 V
0
Input transition (rise and fall) time
TA
(1)
V
1.8
0
VCC = 2 V
tt
V
3.15
VCC = 2 V
Low-level input voltage
V
1.5
VCC = 6 V
VIL
UNIT
VCC
V
VCC
V
1000
VCC = 4.5 V
500
VCC = 6 V
400
Operating free-air temperature
–55
125
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
N (PDIP)
20 PINS
20 PINS
UNIT
109.1
84.6
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
76
72.5
°C/W
RθJB
Junction-to-board thermal resistance
77.6
65.3
°C/W
ψJT
Junction-to-top characterization parameter
51.5
55.3
°C/W
ψJB
Junction-to-top characterization parameter
77.1
65.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
(1)
DW (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 μA
VOH
VI = VIH or VIL
IOH = –6 mA
IOH = –7.8 mA
VOL
TA = 25°C
VCC
MIN
TA = –55°C to 125°C TA = –40°C to 85°C
MAX
MIN
MAX
MIN
2V
1.9
1.9
1.9
4.5 V
4.4
4.4
4.4
6V
5.9
5.9
5.9
4.5 V
3.98
3.7
3.84
6V
5.48
5.2
5.34
MAX
V
2V
0.1
0.1
0.1
IOL = 20 μA
4.5 V
0.1
0.1
0.1
6V
0.1
0.1
0.1
IOL = 6 mA
4.5 V
0.26
0.4
0.33
6V
0.26
0.4
0.33
VI = VIH or VIL
IOL = 7.8 mA
UNIT
V
II
VI = VCC or 0
6V
±0.1
±1
±1
μA
IOZ
VO = VCC or 0
6V
±0.5
±10
±5
μA
ICC
VI = VCC or 0
8
160
80
μA
Ci
IO = 0
6V
10
10
10
pF
Co
20
20
20
pF
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
VCC
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
TA = 25°C
MIN
TA = –55°C to 125°C
MAX
MIN
MAX
TA= –40°C to 85°C
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
50
75
65
4.5 V
10
15
13
6V
9
13
11
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
MAX
UNIT
ns
ns
ns
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5.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
PARAMETER
FROM
TO
LOAD
(INPUT) (OUTPUT) CAPACITANCE
D
Q
CL = 50 pF
tpd
LE
ten
tdis
OE
OE
tt
Q
CL = 50 pF
Q
CL = 50 pF
Q
CL = 50 pF
Q
CL = 50 pF
VCC
TA = 25°C
MIN
TA = –55°C to 125°C TA = –40°C to 85°C
MAX
MIN
MAX
MIN
MAX
2V
150
225
190
4.5 V
30
45
38
6V
26
38
33
2V
175
265
220
4.5 V
35
53
44
6V
30
45
37
2V
150
225
190
4.5 V
30
45
38
6V
26
38
33
2V
150
225
190
4.5 V
30
45
38
6V
26
38
33
2V
60
90
75
4.5 V
12
18
15
6V
10
15
13
UNIT
ns
ns
ns
ns
5.7 Operating Characteristics
VCC = 5 V, TA = 25℃
PARAMETER
Cpd
6
Power dissipation capacitance
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TYP
51
UNIT
pF
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SCLS452C – FEBRUARY 2001 – REVISED MAY 2022
6 Parameter Measurement Information
A.
B.
C.
D.
E.
F.
G.
H.
I.
CL includes probe and test-fixture capacitance.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
For clock inputs, fmaxis measured with the input duty cycle at 50%.
The outputs are measured one at a time with one input transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 6-1. Load Circuit and Voltage Waveforms
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7 Detailed Description
7.1 Overview
The ’HC373 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table(each latch)
INPUTS
8
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD54HC373F
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC373F
Samples
CD54HC373F3A
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8407201RA
CD54HC373F3A
Samples
CD74HC373E
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC373E
Samples
CD74HC373EE4
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC373E
Samples
CD74HC373M
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC373M
Samples
CD74HC373M96
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC373M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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