CD74HC390, CD54HCT390, CD74HCT390
SCHS185E – SEPTEMBER 1997 – REVISED APRIL 2022
CD74HC390, CDx4HCT390 High-Speed CMOS Logic Dual Decade Ripple Counter
1 Features
2 Description
•
•
The SN74HC390 and ‘HCT390 devices include two
independent 4-bit decade ripple counters, falling-edge
clocked with asynchronous clear. Each counter is
divided into two sections, a divide-by-2 and divideby-5 counter, each of which has an independent clock
input. This allows for very flexible configuration of the
device.
•
•
•
•
•
•
•
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4,
5, 10, 20, 25, 50, 100
Two controller reset inputs to clear each decade
counter individually
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: -55°C to 125°C
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
HC types
– 2V to 6V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility, VIL = 0.8
V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 μA at VOL, VOH
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD54HCT390F3A
CDIP (16)
24.38 mm × 6.92 mm
CD74HC390M
SOIC (16)
9.90 mm × 3.90 mm
CD74HCT390M
SOIC (16)
9.90 mm × 3.90 mm
CD74HC390E
PDIP (16)
19.31 mm × 6.35 mm
CD74HCT390E
PDIP (16)
19.31 mm × 6.35 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
nCLKB
Q
Q
Q
Q
nCLKA
R
R
R
R
nCLR
VCC = 16
GND = 8
2QA
2QB
2QC
2QD
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SCHS185E – SEPTEMBER 1997 – REVISED APRIL 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
(1)
5.2 Recommended Operating Conditions ..................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics ................. 6
5.6 Switching Characteristics............................................6
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Documentation Support.......................................... 12
10.2 Receiving Notification of Documentation Updates..12
10.3 Support Resources................................................. 12
10.4 Trademarks............................................................. 12
10.5 Electrostatic Discharge Caution..............................12
10.6 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November 2021) to Revision E (April 2022)
Page
• Corrected table 7-3, QC value 6 from H to L.....................................................................................................10
Changes from Revision C (September 1997) to Revision D (November 2021)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
• Updated pin names to match current TI naming conventions. 1CP0 is now 1CLK A; 1MR is now 1CLR; 1Q0 is
now 1QA; 1CP1 is now 1CLK B; 1Q1 is now 1QB; 1Q2 is now 1QC; 1Q3 is now 1QD; 2Q3 is now 2QD; 2Q2 is
now 2QC; 2Q1 is now 2QB; 2CP1 is now 2CLK B; 2Q0 is now 2QA; 2MR is now 2CLR; 2CP0 is now 2CLK A . 1
2
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SCHS185E – SEPTEMBER 1997 – REVISED APRIL 2022
4 Pin Configuration and Functions
1CLKA
1
16
VCC
1CLR
2
1QA
1CLKB
3
15
14
2CLR
4
13
1QB
5
12
2QA
2CLKB
1QC
1QD
6
11
2QB
7
8
10
2QC
2QD
GND
9
2CLKA
J, N or D Package
16-Pin CDIP, PDIP, or SOIC
Top View
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
-0.5
7
Supply voltage range
(2)
IIK
Input diode current
IOK
Output diode current
IO
±20
mA
(VO < 0 or VO > VCC)
±20
mA
Output source or sink current per
(VO = 0 to VCC)
output pin
±25
mA
Continuous current through VCC or GND
±50
mA
150
°C
150
°C
300
°C
Junction temperature
Tstg
Storage temperature
-65
Lead temperature (Soldering 10s) (SOIC - Lead tips only)
(2)
V
(VI < 0 or VI > VCC)
(2)
TJ
(1)
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
5.2 Recommended Operating Conditions
MIN
MAX
2
6
4.5
5.5
0
VCC
HC Types
VCC
Supply voltage range
VI, VO
Input or output voltage
tt
Input rise and fall time
TA
Temperature range
HCT Types
2V
V
V
1000
4.5 V
500
6V
(1)
UNIT
ns
400
–55
125
℃
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
5.3 Thermal Information
CD74HC390, CD74HCT390
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance
(1)
D (SOIC)
N (PDIP)
16 PINS
16 PINS
UNIT
73
67
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS185E – SEPTEMBER 1997 – REVISED APRIL 2022
5.4 Electrical Characteristics
PARAMETER
TEST
CONDITIONS(1)
VCC
(V)
25℃
MIN
TYP
-40℃ to 85℃
MAX
MIN
-55℃ to 125℃
MAX
MIN
MAX
UNIT
HC TYPES
High level input
voltage
VIH
Low level input
voltage
VIL
High level output
voltage
VOH
High level output
voltage
Low level output
voltage
VOL
Low level output
voltage
2
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
V
6
4.2
4.2
4.2
V
2
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
V
6
1.8
1.8
1.8
V
IOH = – 20 μA
2
1.9
1.9
1.9
V
IOH = – 20 μA
4.5
4.4
4.4
4.4
V
IOH = – 20 μA
6
5.9
5.9
5.9
V
IOH = – 4 mA
4.5
3.98
3.84
3.7
V
IOH = – 5.2 mA
6
5.48
IOL = 20 μA
2
0.1
0.1
0.1
V
IOL = 20 μA
4.5
0.1
0.1
0.1
V
IOL = 20 μA
6
0.1
0.1
0.1
V
5.34
5.2
V
IOL = 4 mA
4.5
0.26
0.33
0.4
V
IOL = 5.2 mA
6
0.26
0.33
0.4
V
II
Input leakage
current
VI = VCC or GND
6
±0.1
±1
±1
μA
ICC
Supply current
VI = VCC or GND
6
8
80
160
μA
HCT TYPES
VIH
High level input
voltage
4.5 to
5.5
VIL
Low level input
voltage
4.5 to
5.5
VOH
VOL
2
2
0.8
2
0.8
V
0.8
V
High level output
voltage
IOH = – 20 μA
4.5
4.4
4.4
4.4
V
High level output
voltage
IOH = – 4 mA
4.5
3.98
3.84
3.7
V
Low level output
voltage
IOL = 20 μA
4.5
0.1
0.1
0.1
V
Low level output
voltage
IOL = 4 mA
4.5
0.26
0.33
0.4
V
II
Input leakage
current
VI = VCC or GND
5.5
±0.1
±1
±1
μA
ICC
Supply current
VI = VCC or GND
5.5
8
80
160
μA
ΔICC (2)
(1)
(2)
Additional supply
current per input
pin
nCLK A inputs
4.5 to
held at VCC – 2.1
5.5
100
162
202.5
220.5
nCLK B, CLR
4.5 to
inputs held at VCC
5.5
– 2.1
100
216
270
294
μA
VI = VIH or VIL, unless otherwise noted.
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8mA.
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5.5 Prerequisite for Switching Characteristics
PARAMETER
VCC (V)
25℃
-40℃ to 85℃
MIN
MIN
-55℃ to 125℃
MAX
MIN
MAX
UNIT
HC TYPES
fMAX
2
6
5
4
4.5
30
24
20
6
35
28
24
2
80
100
120
Clock Pulse Width, nCLK A,
nCLK B
4.5
16
20
24
6
14
17
20
2
70
90
105
Reset Removal Time
4.5
14
18
21
6
12
15
18
2
50
65
75
4.5
10
13
15
6
9
11
13
Maximum Clock Frequency
tW
tREM
tW
Reset Pulse Width
MHz
ns
ns
ns
HCT TYPES
fMAX
Maximum Clock Frequency
4.5
27
22
18
MHz
tW
Clock Pulse Width, nCLK A,
nCLK B
4.5
19
24
29
ns
tREM
Reset Removal Time
4.5
15
19
22
ns
tW
Reset Pulse Width
4.5
13
16
20
ns
5.6 Switching Characteristics
Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF. (see Parameter Measurement Information)
PARAMETER
VCC(V)
-40℃ to
85℃
25℃
TYP
-55℃ to
125℃
UNIT
MAX
MAX
MAX
175
220
265
ns
35
44
53
ns
HC TYPES
2
nCLK A to nQA
nCLK B to nQB
nCLK B to nQC
tpd
nCLK B to nQD
nCLK A to nQD
CLR to Qn
4.5
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(3)
6
30
37
45
ns
2
185
230
280
ns
4.5
37
46
56
ns
6
31
39
48
ns
2
245
305
370
ns
4.5
49
61
74
ns
6
42
52
63
ns
2
180
225
270
ns
4.5
15
(3)
36
45
54
ns
6
31
38
46
ns
2
365
455
550
ns
4.5
73
91
110
ns
6
62
77
94
ns
2
190
240
285
ns
38
48
57
ns
32
41
48
ns
4.5
6
6
14
16
(3)
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SCHS185E – SEPTEMBER 1997 – REVISED APRIL 2022
5.6 Switching Characteristics (continued)
Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF. (see Parameter Measurement Information)
PARAMETER
VCC(V)
TYP
Output Transition Times
tt
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance(1) (2)
-40℃ to
85℃
25℃
-55℃ to
125℃
UNIT
MAX
MAX
MAX
2
75
95
110
ns
4.5
15
19
22
ns
6
13
16
19
ns
10
10
10
pF
5
28
(3)
nCLK A to nQA
4.5
17
(3)
nCLK B to nQB
4.5
nCLK B to nQC
4.5
nCLK B to nQD
4.5
nCLK A to nQC
4.5
CLR to Qn
4.5
Output Transition Times
4.5
pF
HCT TYPES
tpd
tt
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance(1) (2)
(1)
(2)
(3)
(4)
18
(3)
18
(3)
40
50
60
ns
43
51
65
ns
55
69
83
ns
42
53
63
ns
84
105
126
ns
42
53
63
ns
15
19
22
ns
(4)
(4)
(4)
pF
10
5
32
(3)
10
10
pF
CPD is used to determine the dynamic power consumption, per package.
PD = VCC 2 fi + Σ (CL VCC 2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
CL = 15 pF and VCC = 5 V.
CL = 15 pF
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6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
tw
3V
Clock
Input
3V
Input
1.3V
1.3V
1.3V
0V
0V
tsu
Figure 6-2. Voltage Waveforms, TTL-Compatible
CMOS Inputs Pulse Duration
th
3V
Data
Input
1.3V
1.3V
0V
Figure 6-3. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input
1.3V
1.3V
0V
tPLH(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH
(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays
8
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7 Detailed Description
7.1 Overview
The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and
are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked
sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections are normally
used in a BCD decade or bi-quinary configuration, since they share a common controller reset (nCLR). If the
two controller reset inputs (1CLR and 2CLR) are used to simultaneously clear all 8 bits of the counter, a number
of counting configurations are possible within one package. The separate clock inputs (nCLK A and nCLK B) of
each section allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50, or 100.
Each section is triggered by the High-to-Low transition of the input pulses (nCLK A and nCLK B).
For BCD decade operation, the nQA output is connected to the nCLK
bi-quinary decade operation, the nQD output is connected to the nCLK
output.
B
A
input of the divide-by-5 section. For
input and nQA becomes the decade
The controller reset inputs (1CLR and 2CLR) are active-High asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level
on the nCLR input overrides the clock and sets the four outputs Low.
7.2 Functional Block Diagram
nCLKB
Q
Q
Q
Q
nCLKA
R
R
R
R
nCLR
VCC = 16
GND = 8
2QB
2QA
2QC
2QD
Figure 7-1. Functional Block Diagram
nCLKA
nQA
÷2
COUNTER
nCLR
nQB
÷5
COUNTER
nCLKB
nQC
nQD
Figure 7-2. Functional Pinout
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7.3 Device Functional Modes
Table 7-1. Truth Table(1)
INPUTS
(1)
CLK
CLR
↑
L
ACTION
No Change
↓
L
Count
X
H
All Qs Low
H = High voltage level.
L = Low voltage level.
X = Dont care.
↑ = Transition from low to high level.
↓ = Transition from high to low.
Table 7-2. BCD Count Sequence For ½ the 390(1)
OUTPUTS
COUNT
(1)
QD
QC
QB
QA
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
Ouput nQA connected to nCLK B with counter input on nCLK A.
Table 7-3. B-Quinary Count Sequence For ½ the 390(1)
COUNT
(1)
10
OUTPUTS
QD
QC
QB
QA
0
L
1
L
L
L
L
L
H
L
2
L
3
L
H
L
L
H
H
L
4
5
H
L
L
L
L
L
L
H
6
7
L
L
H
H
L
H
L
H
8
L
H
H
H
9
H
L
L
H
Output nQD connected to nCLK A with counter input on nCLK B.
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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8-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
5962-9098401MEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9098401ME
A
CD54HCT390F3A
CD54HCT390F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9098401ME
A
CD54HCT390F3A
CD74HC390E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC390E
CD74HC390EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC390E
CD74HC390M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC390M
CD74HC390M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC390M
CD74HCT390E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT390E
CD74HCT390EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT390E
CD74HCT390M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT390M
CD74HCT390M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT390M
CD74HCT390MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT390M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of