CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
CDx4HC4020, CDx4HCT4020 CDHigh-Speed CMOS Logic 14-Stage Binary Counter
1 Features
2 Description
•
•
•
•
•
The ’HC4020 and ’HCT4020 are 14-stage ripple-carry
binary counters. All counter stages are controller/
peripheral flip- flops. The state of the stage advances
one count on the negative clock transition of each
input pulse; a high voltage level on the MR line resets
all counters to their zero state. All inputs and outputs
are buffered.
•
•
•
•
•
Fully static operation
Buffered inputs
Common reset
Negative edge clocking
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: -55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
Logic ICs
HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility, VIL = 0.8
V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 µA at VOL,VOH
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD54HC4020
J (CDIP, 16)
24.38 mm × 6.92 mm
CD74HC4020CD74
HC4020
D (SOIC, 16)
9.90 mm × 3.90 mm
N (PDIP, 16)
19.31 mm × 6.35 mm
CD54HCT4020
J (CDIP, 16)
24.38 mm × 6.92 mm
CD74HCT4020CD7
4HCT4020
D (SOIC, 16)
9.90 mm × 3.90 mm
N (PDIP, 16)
19.31 mm × 6.35 mm
(1)
For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics.................. 6
5.6 Switching Characteristics ...........................................6
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Receiving Notification of Documentation Updates..12
10.2 Support Resources................................................. 12
10.3 Trademarks............................................................. 12
10.4 Electrostatic Discharge Caution..............................12
10.5 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2003) to Revision D (August 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
4 Pin Configuration and Functions
J, N, or D package
16-PIN CDIP, PDIP, or SOIC
Top View
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
5 Specifications
5.1 Absolute Maximum Ratings
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
IIK
Input diode current
For VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IOK
Output diode current
For VO < –0.5 V or VO > VCC + 0.5 V
±20
mA
IO
Output source or sink current per output pin
For VO> –0.5 V or VO < VCC + 0.5 V
±25
mA
±50
mA
150
°C
150
°C
300
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
– 65
Lead temperature (Soldering 10s) (SOIC - lead tips only)
V
5.2 Recommended Operating Conditions
MIN
VCC
Supply voltage range
VI, VO
DC input or output voltage
HC types
HCT types
MAX
2
6
4.5
5.5
0
VCC
2V
Input rise and fall time
TA
UNIT
V
V
1000
4.5 V
500
6V
400
Temperature range
–55
125
ns
℃
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance
(1)
D (SOIC)
N (PDIP)
16 PINS
16 PINS
UNIT
73
67
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
5.4 Electrical Characteristics
TEST
CONDITIONS(2)
PARAMETER
VCC (V)
25℃
MIN
TYP
-40℃ to 85℃
MAX
MIN
MAX
-55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
High level input
voltage
VIH
VIL
Low level input voltage
2
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6
4.2
4.2
V
4.2
2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6
1.8
1.8
1.8
V
High level output
voltage
CMOS loads
IOH = – 20 μA
2
1.9
1.9
1.9
IOH = – 20 μA
4.5
4.4
4.4
4.4
IOH = – 20 μA
6
5.9
5.9
5.9
High level output
voltage
TTL loads
IOH – 4 mA
4.5
3.98
3.84
3.7
IOH – 5.2 mA
6
5.48
5.34
5.2
Low level output
voltage
CMOS loads
IOL = 20 μA
2
0.1
0.1
0.1
IOL = 20 μA
4.5
0.1
0.1
0.1
IOL = 20 μA
6
0.1
0.1
0.1
Low level output
voltage
TTL loads
IOL = 4 mA
4.5
0.26
0.33
0.4
IOL = 5.2 mA
6
0.26
0.33
0.4
II
Input leakage current
VCC or GND
6
±0.1
±1
±1
µA
ICC
Supply current
VCC or GND
6
8
80
160
µA
VOH
VOL
V
V
V
V
HCT TYPES
VIH
High level input
voltage
4.5 to
5.5
VIL
Low level input voltage
4.5 to
5.5
VOH
VOL
0.8
2
0.8
V
0.8
V
IOH = – 20 μA
4.5
4.4
4.4
4.4
V
High level output
voltage
TTL loads
IOH = – 4 mA
4.5
3.98
3.84
3.7
V
Low level output
voltage
CMOS loads
IOL = 20 μA
4.5
0.1
0.1
0.1
V
Low level output
voltage
TTL loads
IOL = 4 mA
4.5
0.26
0.33
0.4
V
VCC and GND
5.5
±0.1
±1
±1
µA
8
80
160
µA
Input leakage current
ICC
Supply current
(1)
(2)
2
High level output
voltage
CMOS loads
II
ΔICC (1)
2
Additional supply
current per input pin
VCC or GND
5.5
MR input held at
VCC -2.1
4.5 to
5.5
100
234
292.5
318.5
µA
CP input held at
VCC – 2.1
4.5 to
5.5
100
180
225
245
µA
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
VI = VIH or VIL, unless otherwise noted.
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
5.5 Prerequisite for Switching Characteristics
25℃
-40℃ to 85℃
-55℃ to 125℃
PARAMETER
VCC (V)
2
6
5
4
Maximum input pulse
frequency
4.5
30
25
20
6
35
29
24
2
80
100
120
4.5
16
20
24
6
14
17
20
2
50
65
75
4.5
10
13
15
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
HC TYPES
fMAX
tW
tREM
tW
Input pulse width
Reset removal time
Reset pulse width
6
9
11
13
2
80
100
120
4.5
16
20
24
6
14
17
20
MHz
ns
ns
ns
HCT TYPES
fMAX
Maximum input pulse
frequency
4.5
25
20
16
MHz
tW
Input pulse width
4.5
20
25
30
ns
tREC
Reset recovery time
4.5
10
13
15
ns
tW
Reset pulse width
4.5
20
25
30
ns
5.6 Switching Characteristics
Input tr, tf = 6 ns. See Parameter Measurement Information
PARAMETER
TEST
V (V)
CONDITIONS CC
25℃
MIN
TYP
-40℃ to 85℃
MAX
MIN
MAX
-55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
Propagation delay time
CP to Q1' Output
CL = 50 pF
MR to Qn
140
175
210
28
35
42
CL = 15 pF
5
CL = 50 pF
6
24
30
36
2
75
95
110
4.5
15
19
22
CL = 50 pF
Qn to Qn + 1
2
4.5
11
CL = 15 pF
5
CL = 50 pF
6
13
16
19
2
170
215
255
34
43
51
6
29
37
43
2
75
95
110
4.5
15
19
22
6
13
16
19
10
10
10
CL = 50 pF
tTLH,
tTHL
Output transition time
CIN
Input capacitance
CL = 50 pF
CPD
Power dissipation capacitance(1) (2)
CL = 15 pF
CL = 50 pF
6
4.5
5
5
14
30
ns
ns
ns
ns
pF
pF
HCT TYPES
6
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
5.6 Switching Characteristics (continued)
Input tr, tf = 6 ns. See Parameter Measurement Information
PARAMETER
TEST
V (V)
CONDITIONS CC
CL = 50 pF
4.5
CL = 15 pF
5
CL = 50 pF
4.5
CL = 15 pF
5
CL = 50 pF
4.5
CL = 15 pF
5
Output transition
CL = 50 pF
4.5
CIN
Input capacitance
CL = 50 pF
CPD
Power dissipation capacitance(1) (2)
CL = 15 pF
tPLH,
tPHL
Propagation delay time
CP to Q1' Output
tPLH,
tPHL
Qn to Qn + 1
tPLH,
tPHL
MR to Qn
tTLH,
tTHL
(1)
(2)
5
25℃
MIN
TYP
-40℃ to 85℃
MAX
MIN
MAX
-55℃ to 125℃
MIN
MAX
UNIT
40
50
60
15
19
22
40
50
60
15
19
22
ns
10
10
10
pF
17
6
17
30
ns
ns
ns
pF
CPD is used to determine the dynamic power consumption, per package.
PD = VCC 2fi(CPD + CL) where fi = Input frequency, CL = Output load capacitance, VCC = Supply Voltage.
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
VCC
Input
50%
90%
tPLH
tPHL
tr(1)
(1)
VOH
Output
50%
10%
10%
tr(1)
tPLH(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
VOH
50%
VOH
90%
Output
VOL
Output
0V
tf(1)
90%
50%
tPHL(1)
10%
10%
0V
(1)
VCC
90%
Input
50%
Figure 6-3. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
3V
Input
1.3V
1.3V
0V
tPLH
(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
8
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
7 Detailed Description
7.1 Overview
The ’HC4020 and ’HCT4020 are 14-stage ripple-carry binary counters. All counter stages are controller flipflops.
The state of the stage advances one count on the negative clock transition of each input pulse; a high voltage
level on the CLR line resets all counters to their zero state. All inputs and outputs are buffered.
7.2 Functional Block Diagram
Figure 7-1. Functional Diagram
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
7.3 Device Functional Modes
Table 7-1. Truth Table
(1)
10
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CP COUNT(1)
MR
↑
L
No change
↓
L
Advance to next state
X
H
All outputs are low
OUTPUT STATE
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
↑ = Transition from Low to High Level, ↓ = Transition from High
to Low.
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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SCHS201D – FEBRUARY 1998 – REVISED AUGUST 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8945801EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8945801EA
CD54HCT4020F3A
Samples
CD54HC4020F
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC4020F
Samples
CD54HC4020F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8500301EA
CD54HC4020F3A
Samples
CD54HCT4020F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8945801EA
CD54HCT4020F3A
Samples
CD74HC4020E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4020E
Samples
CD74HC4020EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4020E
Samples
CD74HC4020M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4020M
Samples
CD74HC4020M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4020M
Samples
CD74HC4020M96E4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4020M
Samples
CD74HCT4020E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4020E
Samples
CD74HCT4020M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4020M
Samples
CD74HCT4020M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4020M
Samples
CD74HCT4020MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4020M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Aug-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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