CD74HC4060PWE4

[ /Title (CD74 HC406 0, CD74 HCT40 60) /Subject (High Speed CMOS CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 Data sheet acquired from Harris Semiconductor SCHS207G High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator February 1998 - Revised October 2003 the negative transition of φI (and φO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times. Features • Onboard Oscillator • Common Reset In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels. • Negative-Edge Clocking • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC TEMP. RANGE (oC) PACKAGE CD54HC4060F3A -55 to 125 16 Ld CERDIP CD54HCT4060F3A -55 to 125 16 Ld CERDIP CD74HC4060E -55 to 125 16 Ld PDIP CD74HC4060M -55 to 125 16 Ld SOIC CD74HC4060MT -55 to 125 16 Ld SOIC CD74HC4060M96 -55 to 125 16 Ld SOIC CD74HC4060PW -55 to 125 16 Ld TSSOP CD74HC4060PWR -55 to 125 16 Ld TSSOP CD74HC4060PWT -55 to 125 16 Ld TSSOP CD74HCT4060E -55 to 125 16 Ld PDIP CD74HCT4060M -55 to 125 16 Ld SOIC CD74HCT4060MT -55 to 125 16 Ld SOIC CD74HCT4060M96 -55 to 125 16 Ld SOIC PART NUMBER • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4060, CD54HCT4060 (CERDIP) CD74HC4060 (PDIP, SOIC, TSSOP) CD74HCT4060 (PDIP, SOIC) TOP VIEW Q12 1 16 VCC Q13 2 15 Q10 Q14 3 14 Q8 Q6 4 13 Q9 Q5 5 12 MR Q7 6 11 φI Q4 7 10 φO GND 8 9 φO CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54/74HC4060, CD54/74HCT4060 Functional Diagram 7 Q4 5 Q5 4 12 Q6 MR 6 Q7 φI 14 14-STAGE RIPPLE COUNTER AND OSCILLATOR 11 Q8 13 Q9 15 Q10 1 Q12 2 Q13 3 Q14 φO φO øO øO ø1 9 GND = 8 VCC = 16 10 9 ø1 ø4 Q1 FF1 11 ø1 FF4 ø4 Q1 R MR ø5 Q4 ø14 Q13 Q14 10 FF5 - FF13 ø5 Q4 R FF14 ø14 Q13 Q14 R R 12 7 2 Q4 5, 4, 6, 14, 13, 15, 1 Q13 Q5 - Q10, Q12 FIGURE 1. LOGIC BLOCK DIAGRAM TRUTH TABLE øI MR OUTPUT STATE ↑ L No Change ↓ L Advance to Next State X H All Outputs are Low 2 3 Q14 CD54/74HC4060, CD54/74HCT4060 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 108 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage Q Outputs CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage Q Outputs TTL Loads Low Level Output Voltage Q Outputs CMOS Loads VOL VIH or VIL Low Level Output Voltage Q Outputs TTL Loads High-Level Output Voltage φO Output (Pin 10) CMOS Loads VOH VCC or GND - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V 3 CD54/74HC4060, CD54/74HCT4060 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) High-Level Output Voltage φO Output (Pin 10) TTL Loads (Note 2) VOH VCC or GND -2.6 4.5 3.98 - - 3.84 - 3.7 - V -3.3 6 5.48 - - 5.34 - 5.2 - V Low-Level Output Voltage φO Output (Pin 10) CMOS Loads VOL VCC or GND 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V Low-Level Output Voltage φO Output (Pin 10) TTL Loads VOL VCC or GND 2.6 4.5 - - 0.26 - 0.33 - 0.4 V 3.3 6 - - 0.26 - 0.33 - 0.4 V High-Level Output Voltage φO Output (Pin 9) TTL Loads VOH VIL or VIH -3.2 4.5 3.98 - - 3.84 - 3.7 - V -4.2 6 5.48 - - 5.34 - 5.2 - V Low-Level Output Voltage φO Output (Pin 9) TTL Loads VOL -2.6 4.5 - - 0.26 - 0.33 - 0.4 V -3.3 6 - - 0.26 - 0.33 - 0.4 V PARAMETER VIL or VIH MIN TYP MAX MIN MAX MIN MAX UNITS II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage Q Outputs CMOS Loads VOH VIH or VIL (Note 3) -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V Input Leakage Current Quiescent Device Current HCT TYPES High Level Output Voltage Q Outputs TTL Loads Low Level Output Voltage Q Outputs CMOS Loads VOL VIH or VIL (Note 3) Low Level Output Voltage Q Outputs TTL Loads High-Level Output Voltage φO Output (Pin 10) CMOS Loads VOH VCC or GND -0.02 4.5 4.4 - - 4.4 - 4.4 - V High-Level Output Voltage φO Output (Pin 10) TTL Loads (Note 2) VOH VCC or GND -2.6 4.5 3.98 - - 3.84 - 3.7 - V Low-Level Output Voltage φO Output (Pin 10) CMOS Loads VOL VCC or GND 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 CD54/74HC4060, CD54/74HCT4060 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) Low-Level Output Voltage φO Output (Pin 10) TTL Loads VOL VCC or GND 2.6 4.5 - - 0.26 - 0.33 - 0.4 V High-Level Output Voltage φO Output (Pin 9) TTL Loads VOH VIL or VIH -3.2 4.5 3.98 - - 3.84 - 3.7 - V Low-Level Output Voltage φO Output (Pin 9) TTL Loads VOL VIH or VIL (Note 3) 3.2 4.5 - 0.26 - 0.33 - 0.4 V II Any Voltage Between VCC and GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 4) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA PARAMETER Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load MIN TYP MAX MIN MAX MIN MAX UNITS NOTES: 2. Limits not valid when pin 12 (instead of pin 11) is used as control input. 3. For pin 11 VIH = 3.15V, VIL = 0.9V. 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS MR 0.35 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications Table, e.g. 360µA max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS fmax 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns HC TYPES Maximum Input Pulse Frequency Input Pulse Width Reset Removal Time tW tREM 5 CD54/74HC4060, CD54/74HCT4060 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER Reset Pulse Width -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns HCT TYPES Maximum Input, Pulse Frequency fmax 4.5 30 - - 25 - - 20 - - MHz Input Pulse Width tW 4.5 16 - - 20 - - 24 - - ns tREM 4.5 26 - - 33 - - 39 - - ns tW 4.5 25 - - 31 - - 38 - - ns Reset Removal Time Reset Pulse Width Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 300 - 375 - 450 ns 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 6 - - 51 - 64 - 78 ns CL = 50pF 2 - - 80 - 100 - 120 ns 4.5 - - 16 - 20 - 24 ns CL = 15pF 5 - 6 - - - - - ns CL = 50pF 6 - - 14 - 17 - 20 ns CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - - - - - pF HC TYPES Propagation Delay φI to Q4 Qn to Qn+1 MR to Qn Output Transition Time Input Capacitance Propagation Dissipation Capacitance (Notes 5, 6) tPLH, tPHL tPHL tTHL, tTLH CI (TBD) CPD - - - 40 tPLH, tPHL CL = 50pF 2 - - - - - - - -ns 4.5 - - 66 - 83 - 100 ns CL = 15pF 5 - 25 - - - - - -ns CL = 50pF 6 - - - - - - - -ns HCT TYPES Propagation Delay φI to Q4 6 CD54/74HC4060, CD54/74HCT4060 Switching Specifications PARAMETER Qn to Qn+1 Input tr, tf = 6ns (Continued) -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - - - - - - ns 4.5 - - 16 - 20 - 24 ns CL = 15pF 5 - 6 - - - - - ns CL = 50pF 6 - - - - - - - ns CL = 50pF 2 - - - - - - - ns 4.5 - - 44 - 55 - 66 ns CL = 15pF 5 - 17 - - - - - ns CL = 50pF 6 - - - - - - - ns CL = 50pF 2 - - - - - - - ns 4.5 - - 15 - 19 - 22 ns 6 - - - - - - - ns - - 40 - - - - - pF MR to Qn tPHL Output Transition Time -40oC TO 85oC 25oC tTHL, tTLH Input Capacitance CI (TBD) Propagation Dissipation Capacitance (Notes 5, 6) CPD - NOTES: 5. CPD is used to determine the dynamic power consumption, per package. 6. PD = CPD VCC2 fi ∑(CL VCC2 fi/M) where M = 21, 22, 23, ...214, fi = input frequency, CL = output load capacitance. TYPICAL LIMIT VALUES FOR RX AND CX RX Minimum RX Maximum CX Minimum Maximum Astable Oscillator Frequency CX > 1000pF 102 VOLTAGE TYPICAL MAXIMUM LIMITS 2 1KΩ 10 CX > 10pF 4.5 CX > 10pF 6 CX > 10pF 2 CX > 10pF 4.5 CX > 10pF 6 RX > 10KΩ 2 RX > 10KΩ 4.5 RX > 10KΩ 6 TA = 25oC RX = 1KΩ 10KΩ 100KΩ 1MΩ 10MΩ 1 CX (µF) PARAMETER TEST CONDITIONS 20MΩ 10-1 10-2 10-3 10pF 10-4 RX = 1KΩ 2 1000pF RX = 1KΩ 4.5 10pF RX = 1KΩ 6 10pF CX = 1000pF, RX = 1KΩ 2 0.5MHz (Note 7) CX = 100pF, RX = 1KΩ 4.5 3MHz (Note 7) CX = 100pF, RX = 1KΩ 6 3MHz (Note 7) 10-5 10-1 100 103 10 102 104 OSCILLATOR FREQUENCY (Hz) 105 106 NOTE: OSC Frequency ≈ 1/2.2 RXCX For 1MΩ > RX > 1KΩ, CX > 10pF, f < 1MHz FIGURE 2. FREQUENCY OF ON-BOARD OSCILLATOR AS A FUNCTION OF CX AND RX NOTE: 7. At very high frequencies f = 1/2.2 RXCX no longer gives an accurate approximation. 7 CD54/74HC4060, CD54/74HCT4060 Typical Performance Curves tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL 50% CLOCK 50% 1.3V 0.3V tWH tf = 6ns GND tTLH 3V 2.7V 1.3V 0.3V INPUT GND tTHL 90% 50% 10% INVERTING OUTPUT GND tr = 6ns VCC tTHL 1.3V FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns 90% 50% 10% I fCL NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns 1.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL 2.7V 0.3V GND tWL INPUT tfCL = 6ns 3V VCC 50% 10% tWL + tWH = trCL = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 5. HC AND HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8 PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8768001EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8768001EA CD54HC4060F3A Samples 5962-8977101EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8977101EA CD54HCT4060F3A Samples CD54HC4060F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8768001EA CD54HC4060F3A Samples CD54HCT4060F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8977101EA CD54HCT4060F3A Samples CD74HC4060E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4060E Samples CD74HC4060M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M Samples CD74HC4060M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M Samples CD74HC4060M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M Samples CD74HC4060MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M Samples CD74HC4060MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M Samples CD74HC4060PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 Samples CD74HC4060PWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 Samples CD74HC4060PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 Samples CD74HC4060PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 Samples CD74HC4060PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 Samples CD74HCT4060E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4060E Samples CD74HCT4060EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4060E Samples CD74HCT4060M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M Samples CD74HCT4060M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 12-Jul-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD74HCT4060M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M Samples CD74HCT4060MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of