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CD74HC564M96G4

CD74HC564M96G4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC20_300MIL

  • 描述:

    IC D-TYPE POS TRG SNGL 20SOIC

  • 数据手册
  • 价格&库存
CD74HC564M96G4 数据手册
CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 CDx4HC534, CDx4HCT534, CDx4HC564, CDx4HCT564 High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered 1 Features 2 Description • • • • • The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL loads. Due to the large output drive capability and the threestate feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. The two types are functionally identical and differ only in their pinout arrangements. • • • • • • Buffered inputs Common three-state output-enable control Three-state outputs Bus line driving capability Typical propagation delay = 13 ns at VCC = 5 V, CL = 15 pF, TA = 25℃ (clock to output) Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads Wide operating temperature range: –55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min) – CMOS input compatibility, II ≤ 1 μA at VOL, VOH Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC564M SOIC (20) 12.80 mm × 7.50 mm CD74HCT564M SOIC (20) 12.80 mm × 7.50 mm CD74HC534E PDIP (20) 25.40 mm × 6.35 mm CD74HC564E PDIP (20) 25.40 mm × 6.35 mm CD74HCT534E PDIP (20) 25.40 mm × 6.35 mm CD74HCT564E PDIP (20) 25.40 mm × 6.35 mm CD54HC534F3A CDIP (20) 26.92 mm × 6.92 mm CD54HCT534F3A CDIP (20) 26.92 mm × 6.92 mm CD54HCT564F3A CDIP (20) 26.92 mm × 6.92 mm (1) For all available packages, see the orderable addendum at the end of the data sheet Functional Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings(1) .................................... 4 5.2 Recommended Operating Conditions ........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Prerequisite for Switching Characteristics.................. 6 5.6 Switching Characteristics............................................7 6 Parameter Measurement Information............................ 8 7 Detailed Description......................................................10 7.1 Overview................................................................... 10 7.2 Functional Block Diagram......................................... 10 7.3 Device Functional Modes..........................................10 8 Power Supply Recommendations................................11 9 Layout............................................................................. 11 9.1 Layout Guidelines..................................................... 11 10 Device and Documentation Support..........................12 10.1 Receiving Notification of Documentation Updates..12 10.2 Support Resources................................................. 12 10.3 Trademarks............................................................. 12 10.4 Electrostatic Discharge Caution..............................12 10.5 Glossary..................................................................12 11 Mechanical, Packaging, and Orderable Information.................................................................... 12 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (January 2022) to Revision E (October 2022) Page • Increased RθJA for packages: DW (58 to 109.1); N (69 to 84.6)....................................................................... 4 Changes from Revision C (April 2004) to Revision D (January 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 4 Pin Configuration and Functions HC/HCT534 J or N package 20-Pin CDIP or PDIP Top View Copyright © 2022 Texas Instruments Incorporated HC/HCT564 J, N, or DW package 20-Pin CDIP, PDIP, or SOIC Top View Submit Document Feedback Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 3 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 5 Specifications 5.1 Absolute Maximum Ratings(1) MIN MAX –0.5 7 UNIT VCC Supply voltage V IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Drain current, per output For –0.5 V < VO < VCC + 0.5 V ±35 mA IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA Continuous current through VCC or GND ±50 mA TJ Junction temperature 150 °C Tstg Storage temperature range 150 °C 300 °C –65 Lead temperature (Soldering 10s) (SOIC - lead tips only) (1) Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 5.2 Recommended Operating Conditions VCC Supply voltage range VI, VO Input or output voltage tt Input rise and fall time TA Temperature range HC types HCT types MIN MAX 2 6 4.5 5.5 0 VCC 2V UNIT V V 1000 4.5 V 500 6V ns 400 –55 125 ℃ 5.3 Thermal Information THERMAL METRIC N (PDIP) 20 PINS 20 PINS UNIT 109.1 84.6 °C/W RθJA Junction-to-ambient thermal resistance RθJC (top) Junction-to-case (top) thermal resistance 76 72.5 °C/W RθJB Junction-to-board thermal resistance 77.6 65.3 °C/W ΨJT Junction-to-top characterization parameter 51.5 55.3 °C/W ΨJB Junction-to-board characterization parameter 77.1 65.2 °C/W RθJC (bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 4 (1) DW (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS(2) VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES VIH VIL VOH High level input voltage Low level input voltage High level output voltage High level output voltage VOL Low level output voltage Low level output voltage 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = –20 µA 2 1.9 1.9 1.9 IOH = –20 µA 4.5 4.4 4.4 4.4 IOH = –20 µA 6 5.9 5.9 5.9 IOH = –6 mA 4.5 3.98 3.84 3.7 IOH = –7.8 mA 6 5.48 IOL = 20 µA 2 0.1 0.1 0.1 IOL = 20 µA 4.5 0.1 0.1 0.1 IOL = 20 µA 6 0.1 0.1 0.1 5.34 V V 5.2 IOL = 6 mA 4.5 0.26 0.33 0.4 IOL = 7.8 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 µA ICC Supply current VI = VCC or GND 6 8 80 160 µA IOZ Three-state leakage current VO = VCC or GND 6 ±0.5 ±5.0 ±10 µA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 2 2 0.8 2 0.8 V 0.8 High level output voltage VOH = –20 µA 4.5 4.4 4.4 4.4 High level output voltage VOH = –6 mA 4.5 3.98 3.84 3.7 Low level output voltage VOL = 20 µA 4.5 0.1 0.1 0.1 Low level output voltage VOL = 6 mA 4.5 0.26 0.33 0.4 V V V II Input leakage current VI = VCC and GND 5.5 ±0.1 ±1 ±1 µA ICC Supply current VI = VCC and GND 5.5 8 80 160 µA IOZ Three-state leakage current VO = VCC or GND 5.5 ±0.5 ±5.0 ±10 µA Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 5 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 5.4 Electrical Characteristics (continued) TEST CONDITIONS(2) VCC (V) D0 - D7 inputs held at VCC –2.1 PARAMETER Additional supply current per input pin ΔICC (1) (1) (2) 25℃ MIN –40℃ to 85℃ MIN –55℃ to 125℃ TYP MAX MAX MIN MAX 4.5 to 5.5 100 54 67.5 73.5 CP input held at VCC –2.1 4.5 to 5.5 100 108 135 147 OE input held at VCC –2.1 4.5 to 5.5 100 198 247.5 269.5 UNIT µA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL. 5.5 Prerequisite for Switching Characteristics PARAMETER VCC(V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN TYP –55℃ to 125℃ MAX MIN TYP MAX UNIT HC TYPES fMAX tW tSU tH Maximum clock frequency Clock pulse width Setup time data to clock Hold time data to clock 2 6 5 4 4.5 30 25 20 6 35 29 23 2 80 100 120 4.5 16 20 24 6 14 17 20 2 60 75 90 4.5 12 15 18 6 10 13 15 2 5 5 5 4.5 5 5 5 6 5 5 5 MHz ns ns ns HCT TYPES 6 fMAX Maximum clock frequency 4.5 25 20 16 MHz tW Clock pulse width 4.5 20 25 30 ns tSU Setup time data to clock 4.5 20 25 30 ns tH Hold time Data to clock (534) 4.5 5 5 5 ns tH Hold time Data to clock (564) 4.5 3 3 3 ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 5.6 Switching Characteristics CL = 50 pF, Input tr, tf = 6 ns PARAMETER VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES 2 tPLH, tPHL Propagation delay clock to output tPL, tPHZ Output disable to Q (534) 4.5 13 (3) 28 35 43 190 225 30 38 45 26 33 38 135 170 205 27 34 41 23 29 35 150 190 225 30 38 45 26 33 38 4.5 12 (3) 4.5 12 (3) 2 4.5 12 (3) 60 (4) 6 Maximum clock frequency tTHL, tTLH Output transition time 5 Input capacitance CO Three-state output capacitance CPD Power dissipation capacitance(1) (2) ns ns ns ns MHz 2 60 75 90 4.5 12 15 18 10 13 15 10 10 10 pF 20 20 20 pF 6 CI 50 150 6 fMAX 250 41 2 2 tPZL, tPZH Output enable to Q 205 33 6 6 tPLZ, tPHZ Output disable to Q (564) 165 10 20 5 32 ns pF HCT TYPES tPHL, tPLH Propagation delay clock to output 4.5 14 (3) 35 44 53 ns 30 38 45 ns 35 44 53 ns 12 15 18 ns tPLZ, tPHZ Output disable to Q 4.5 12 (3) tPHL, tPZH Output enable to Q 4.5 14 (3) 50 (4) fMAX Maximum clock frequency tTLH, tTHL Output transition time 5 4.5 MHz CI Input capacitance 10 10 10 10 pF CO Three-state output capacitance 20 20 20 20 pF CPD (1) (2) (3) (4) Power dissipation capacitance(1) (2) 5 36 pF CPD is used to determine the dynamic power consumption, per package. PD = CPD VCC 2 fi + Σ CL VCC 2 fO where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V. CL = 15 pF. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 7 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. VCC Test Point Test Point S1 RL From Output Under Test CL(1) From Output Under Test CL(1) S2 (1) CL includes probe and test-fixture capacitance. (1) CL includes probe and test-fixture capacitance. Figure 6-2. Load Circuit for Push-Pull Outputs Figure 6-1. Load Circuit for 3-State Outputs VCC Input 50% VCC Output Control 50% 50% 50% 0V 0V tPHL(1) tPLH(1) tPZL(3) VOH Output 50% VOL tPHL (1) tPLH 50% 50% 10% VOL (1) tPZH VOH Output § 9CC Output Waveform 1 S1 at VLOAD(1) 50% Output Waveform 2 S1 at GND(2) 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. tPLZ(4) (3) tPHZ (4) 90% VOH 50% §0V (1) S1 = CLOSED; S2 = OPEN. (2) S1 = OPEN; s2 = CLOSED. (3) tPLZ and tPHZ are the same as tdis. (4) tPZL and tPZH are the same as ten. Figure 6-3. Voltage Waveforms, Propagation Delays for Standard CMOS Inputs Figure 6-4. Voltage Waveforms, Standard CMOS Inputs Propagation Delays 90% VCC 90% Input 10% 10% tr(1) 0V tf(1) 90% VOH 90% Output 10% 10% tr(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. Figure 6-5. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 3V Input 1.3V 1.3V 3V Input 1.3V 1.3V 0V tPLH(1) VOH Output Waveform 1 50% 50% VOL 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-6. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs Copyright © 2022 Texas Instruments Incorporated Output Waveform 2 S1 OPEN, S2 CLOSED tPLZ(2)  VCC 50% 10% VOL tPZH(1) VOH 50% Output Waveform 1 S1 CLOSED, S2 OPEN tPLH(1) tPHL(1) Output Waveform 2 0V tPZL(1) tPHL(1) tPHZ(2) 90% VOH 50% 0V (1) tPLZ and tPHZ are the same as tdis. (2) tPZL and tPZH are the same as ten. Figure 6-7. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays Submit Document Feedback Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 9 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 7 Detailed Description 7.1 Overview The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL loads. Due to the large output drive capability and the three-state feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. The two types are functionally identical and differ only in their pinout arrangements. The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are inverted and transferred to the Q outputs on the positive going transition of the CLOCK input. When a high logic level is applied to the OUTPUT ENABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The HCT logic family is speed, function, and pin compatible with the standard LS logic family. 7.2 Functional Block Diagram 7.3 Device Functional Modes Table 7-1. Truth Table(1) INPUTS (1) 10 Submit Document Feedback OUTPUT OE CP Dn Qn L ↑ H L L ↑ L H L L X No change H X X Z H = high level (steady state), L = low level (steady state), X= don’t care, ↑ = transition from low to high level, Z = High impedance state Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 11 CD54HC534, CD74HC534, CD54HC564, CD74HC564 CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564 www.ti.com SCHS188E – NOVEMBER 1998 – REVISED OCTOBER 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC534 CD74HC534 CD54HC564 CD74HC564 CD54HCT534 CD74HCT534 CD54HCT564 CD74HCT564 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8681401RA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8681401RA CD54HC534F3A Samples 5962-8681501RA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8681501RA CD54HC564F3A Samples 5962-8984901RA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8984901RA CD54HCT534F3A Samples CD54HC534F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8681401RA CD54HC534F3A Samples CD54HC564F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8681501RA CD54HC564F3A Samples CD54HCT534F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8984901RA CD54HCT534F3A Samples CD54HCT564F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT564F3A Samples CD74HC534E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC534E Samples CD74HC564E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC564E Samples CD74HC564M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC564M Samples CD74HC564M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC564M Samples CD74HCT534E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT534E Samples CD74HCT564E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT564E Samples CD74HCT564M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT564M Samples CD74HCT564MG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT564M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2022 OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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