CD74HC595
SCHS353A – JANUARY 2004 – REVISED FEBRUARY 2022
CD74HC595 8-Bit Shift Registers With 3-State Output Registers
1 Features
2 Description
•
•
•
The CD74HC595 is an 8-bit serial-input paralleloutput shift register with output registers and 3-state
outputs.
•
•
•
•
•
8-Bit serial-in, parallel-out shift
Wide operating voltage range of 2 V to 6 V
High-current 3-state outputs can drive up to 15
LSTTL loads
Low power consumption, 80-µA max ICC
Typical tPD = 14 ns
±6-mA output drive at 5 V
Low input current of 1 µA max
Shift register has direct clear
Device Information
PACKAGE
BODY SIZE (NOM)
CD74HC595E
PDIP (16)
19.31 mm × 6.35 mm
CD74HC595DW
SOIC-DW (16) 10.30 mm × 7.50 mm
CD74HC595M
SOIC-D (16)
9.90 mm × 3.90 mm
CD74HC595NS
SO (16)
10.20 mm × 5.30 mm
CD74HC595SM
SSOP (16)
6.20 mm × 5.30 mm
(1)
OE
RCLK
SRCLR
SRCLK
SER
(1)
PART NUMBER
For all available packages, see the orderable addendum at
the end of the data sheet.
13
12
10
11
14
D
Q
D
Q
15
QA
R
D
Q
D
Q
1
QB
R
2
QC
3
QD
4
QE
5
QF
6
QG
D
Q
D
Q
7
QH
R
9
QH’
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD74HC595
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SCHS353A – JANUARY 2004 – REVISED FEBRUARY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
(1)
5.2 Recommended Operating Conditions ..................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements ................................................. 6
5.6 Switching Characteristics ...........................................8
5.7 Operating Characteristics........................................... 9
6 Parameter Measurement Information.......................... 10
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Device Functional Modes..........................................12
8 Power Supply Recommendations................................13
9 Layout.............................................................................13
9.1 Layout Guidelines..................................................... 13
10 Device and Documentation Support..........................14
10.1 Documentation Support.......................................... 14
10.2 Receiving Notification of Documentation Updates..14
10.3 Support Resources................................................. 14
10.4 Trademarks............................................................. 14
10.5 Electrostatic Discharge Caution..............................14
10.6 Glossary..................................................................14
11 Mechanical, Packaging, and Orderable
Information.................................................................... 14
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (January 2004) to Revision A (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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4 Pin Configuration and Functions
QB
1
16
VCC
QC
2
QA
QD
QE
3
15
14
4
13
QF
5
12
RCLK
QG
QH
6
11
SRCLK
7
8
10
SRCLR
QH¶
GND
9
SER
OE
D, DW, N, NS, or DB Package
16-Pin SOIC, PDIP, SO, or SSOP
Top View
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SCHS353A – JANUARY 2004 – REVISED FEBRUARY 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
VCC
Supply voltage
IIK
Input clamp current
IOK
Output clamp current
IO
Continous output current
MAX
-0.5
(2)
(2)
7
(1)
(2)
V
For VI < 0 or VI > VCC
±20
mA
For VO < 0 or VO > VCC
±20
mA
For -0.5V < VO = 0 to VCC
±35
mA
±70
mA
150
°C
Continuous current through VCC or GND
Tstg
UNIT
Storage temperature
-65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
5.2 Recommended Operating Conditions
VCC
NOM
MAX
2
5
6
Supply voltage
VCC = 2V
VIH
MIN
High-level input voltage
VCC = 4.5V
V
3.15
4.2
VCC = 2V
Low-level input voltage
V
1.5
VCC = 6V
VIL
UNIT
0.5
VCC = 4.5V
1.35
VCC = 6V
V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2V
tt
(2)
Input transition rise and fall time
1000
VCC = 4.5V
500
VCC = 6V
TA
(1)
(2)
ns
400
Operating free-air temperature
-55
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state
from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal
(1)
resistance
N (PDIP)
DW (SOIC)
D (SOIC)
NS (SO)
DB (SSOP)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
67
57
73
64
82
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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5.4 Electrical Characteristics
PARAMETER
(1)
TEST CONDITIONS
VCC (V)
25°C
-40°C to 85°C
MAX
MIN
MAX
-55°C to 125°C
MIN
TYP
MIN
2
1.9
1.998
1.9
1.9
4.5
4.4
4.499
4.4
4.4
MAX
UNIT
HC TYPES
IOH = – 20 µA
6
QH', IOH = – 4 mA
VOH
4.5
QA-QH, IOH = – 6 mA
QH', IOH= – 5.2 mA
QA-QH, IOH = – 57.8 mA
IOL = 20 µA
VOL
QH', IOL = 4 mA
QA-QH, IOL = 6 mA
QH', IOL= 5.2 mA
QA-QH, IOL = 7.8 mA
6
5.9
5.999
5.9
5.9
3.98
4.3
3.84
3.7
3.98
4.3
3.84
3.7
5.48
5.8
5.34
5.2
5.48
5.8
5.34
V
5.2
2
0.002
0.1
0.1
0.1
4.5
0.001
0.1
0.1
0.1
6
0.001
0.1
0.1
0.1
0.17
0.26
0.33
0.4
V
0.17
0.26
0.33
0.4
V
0.15
0.26
0.33
0.4
V
0.15
0.26
0.33
0.4
V
4.5
6
V
II
VI = VCC or 0
6
±0.1
±100
±1000
±1000
nA
IOZ
VO = VCC or 0, QA-QH
6
±0.01
±0.5
±5
±10
µA
ICC
VI = VCC or 0, IO = 0
8
80
160
µA
3
10
10
10
pF
Ci
(1)
6
2 to 6
VI = VIH or VIL
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SCHS353A – JANUARY 2004 – REVISED FEBRUARY 2022
5.5 Timing Requirements
VCC
(V)
PARAMETER
25°C
MIN
-40°C to 85°C
MAX
MIN
MAX
-55°C to 125°C
MIN
MAX
UNIT
HC TYPES
fclock
Clock frequency
2
6
5
4.2
4.5
31
25
21
6
SRCLK or RCLK high or
low
tW
Pulse duration
SRCLR low
SER before SRCLK↑
SRCLK↑ before RCLK↑
(1)
tSU
Setup time
SRCLR low before
RCLK↑
SRCLR high (inactive)
before SRCLK↑
th
(1)
6
Hold time, SER after SRCLK↑
36
29
MHz
25
2
80
100
120
4.5
16
20
24
6
14
17
20
2
80
100
120
4.5
16
20
24
6
14
17
20
2
100
125
150
4.5
20
25
30
6
17
21
25
2
75
94
113
4.5
15
19
23
6
13
16
19
2
50
65
75
4.5
10
13
15
6
9
11
13
2
50
60
75
4.5
10
12
15
6
9
11
13
2
0
0
0
4.5
0
0
0
6
0
0
0
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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SCHS353A – JANUARY 2004 – REVISED FEBRUARY 2022
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH’
NOTE:
implies that the output is in 3-State mode.
Timing Diagram
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5.6 Switching Characteristics
over operating free-air temperature range, CL = 50pF (unless otherwise noted) (Figure 6)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
SRCLK
QH'
tpd
RCLK
tPHL
SRCLR
ten
OE
tdis
OE
QA-QH
QH'
QA-QH
QA-QH
QA-QH
tt
QH'
VCC
TA=-40oC to
85oC
TA = 25oC
MAX
MIN
TA = -55oC to
125oC
UNIT
MAX
MIN MAX
MIN
TYP
2
6
26
5
4.2
4.5
31
38
25
21
6
36
42
29
25
MHz
2
50
160
200
240
4.5
17
32
40
48
6
14
27
34
41
2
50
150
187
225
4.5
17
30
37
45
6
14
26
32
38
2
51
175
219
261
4.5
18
35
44
52
6
15
30
37
44
2
40
150
187
225
4.5
15
30
37
45
6
13
26
32
38
2
42
200
250
300
4.5
23
40
50
60
6
20
34
43
51
2
28
60
75
90
4.5
8
12
15
18
6
6
10
13
15
2
28
75
95
110
4.5
8
15
19
22
6
6
13
16
19
ns
ns
ns
ns
ns
5.6 Switching Characteristics
over operating free-air temperature range, CL = 150pF (unless otherwise noted) (Figure 6)
PARAMETER
FROM
(INPUT)
fpd
RCLK
TO
(OUTPUT)
QA-QH
VCC
MIN
OE
tt
8
QA-QH'
QA-QH
MAX
MIN
UNIT
MAX
2
60
200
250
4.5
22
40
50
60 MHz
6
19
34
43
51
70
200
250
298
2340
40
50
60
4.5
MIN
TA = -55oC to
125oC
TYP
2
ten
TA=-40oC to
85oC
TA = 25oC
MAX
300
6
19
34
43
51
2
45
210
265
315
4.5
17
42
53
63
6
13
36
45
53
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ns
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5.7 Operating Characteristics
TA = 25°C
Cpd
Power dissipation capacitance
TEST CONDITIONS
TYP
UNIT
No load
400
pF
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6 Parameter Measurement Information
Figure 6-1. Load Curcuit and Voltage Waveforms
10
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7 Detailed Description
7.1 Overview
The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and
storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial
output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
7.2 Functional Block Diagram
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
D
Q
D
Q
15
QA
R
D
Q
D
Q
1
QB
R
2
QC
3
QD
4
QE
5
QF
6
QG
D
Q
D
Q
7
QH
R
9
QH’
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7.3 Device Functional Modes
Table 7-1 lists the functional modes of the CD74HC595.
Table 7-1. Function Table
INPUTS
SER
12
SRCLK
SRCLR
RCLK
OE
FUNCTION
X
X
X
X
H
Outputs QA – QH are disabled
X
X
X
X
L
Outputs QA – QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage,
respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage,
respectively.
X
X
H
↑
X
Shift-register data is stored in the storage register.
X
↑
H
↑
X
Data in shift register is stored in the storage
register, the data is then shifted through.
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD74HC595DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC595M
Samples
CD74HC595DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC595M
Samples
CD74HC595E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC595E
Samples
CD74HC595M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC595M
Samples
CD74HC595M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC595M
Samples
CD74HC595MG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC595M
Samples
CD74HC595MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC595M
Samples
CD74HC595NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC595M
Samples
CD74HC595SM96
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ595
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of