CD74HC640EG4

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 CDx4HC640 CDx4HCT640 High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting 1 Features 2 Description • • • • The CDx4HC640 and CDx4HCT640 are inverting octal bus transceivers with 3-state outputs. • • • • • Buffered inputs Three-state outputs Applications in multiple-data-bus architecture Fanout (over temperature range) – Standard outputs : 10 LSTTL loads – Bus driver outputs : 15 LSTTL loads Wide operating temperature range : -55oC to 125oC Balanced propagation delay and transition times Significant power reduction compared to LSTTL logic IC's HC types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V(Max), VIH = 2 V(Min) – CMOS input compatibility, II ≤ 1µA at VOL, VOH Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD54HC640 J (CDIP, 20) 26.92 mm × 6.92 mm CD74HC640 N (PDIP, 20) 25.4 mm × 6.35 mm DW (SOIC, 20) 12.80 mm × 7.50 mm CD54HCT640 J (CDIP, 20) 26.92 mm × 6.92 mm CD74HCT640 N (PDIP, 20) 25.40 mm × 6.35 mm DW (SOIC, 20) 12.80 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 (2) 5.5 Switching Characteristics ........................................ 6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Documentation Support.......................................... 10 10.2 Receiving Notification of Documentation Updates..10 10.3 Support Resources................................................. 10 10.4 Trademarks............................................................. 10 10.5 Electrostatic Discharge Caution..............................10 10.6 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2003) to Revision C (July 2022) Page • Updated the numbering, formatting, tables, figures and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 4 Pin Configuration and Functions J, N and DW Package 20-Pin CDIP, PDIP or SOIC Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 3 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX -0.5 7 UNIT VCC Supply voltage V IIK Input diode current For VI < -0.5V or VI > VCC + 0.5V ±20 mA IOK Output diode current For VO < -0.5V or VO > VCC + 0.5V ±20 mA IO Drain current, per output For -0.5V < VO < VCC + 0.5V ±35 mA IO Output source or sink current per For VO > -0.5V or VO < VCC + 0.5V output pin ±25 mA Continuous current through VCC or GND ±50 mA TJ Junction Temperature 150 °C Tstg Storage temperature 150 °C 300 °C -65 Lead temperature (Soldering 10s)(SOIC - lead tips only) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions VCC Supply voltage VI Input voltage VO Output voltage MIN MAX 2 6 4.5 5.5 0 VCC V VCC V HC types HCT types 0 VCC = 2V tt TA Input rise and fall time UNIT V 1000 VCC = 4.5V 500 VCC = 6V 400 Temperature range -55 125 ns °C 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance (1) N (PDIP) DW (SOIC) 20 PINS 20 PINS UNIT 69 58 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 5.4 Electrical Characteristics TEST (1) CONDITIONS PARAMETER VCC (V) 25°C MIN TYP -40°C to 85°C MAX MIN MAX -55°C to 125°C MIN MAX UNIT HC TYPES VIH High-level input voltage VIL Low-level input voltage High-level output voltage CMOS loads VOH 2 1.5 1.5 1.5 V 4.5 3.15 3.15 3.15 V 6 4.2 4.2 4.2 V 2 0.5 0.5 0.5 V 4.5 1.35 1.35 1.35 V 6 1.8 1.8 1.8 V IOH = – 20 µA 2 1.9 1.9 1.9 V IOH = – 20 µA 4.5 4.4 4.4 4.4 V IOH = – 20 µA 6 5.9 5.9 5.9 V IOH= – 6 mA 4.5 3.98 3.84 3.7 V IOH = – 7.8 mA 6 5.48 IOL = 20 µA 2 0.1 0.1 0.1 V IOL = 20 µA 4.5 0.1 0.1 0.1 V IOL = 20 µA 6 0.1 0.1 0.1 V Low-level output voltage TTL loads IOL= 6 mA 4.5 0.26 0.33 0.4 V IOL = 7.8 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 µA ICC Quiescent device current VI = VCC or GND 6 8 80 160 µA IOZ Three-state leakage current VO = VCC or GND 6 ±0.5 ±5 ±10 µA High-level output voltage TTL loads Low-level output voltage CMOS loads VOL 5.34 5.2 V HCT TYPES VIH High-level input voltage 4.5 to 5.5 VIL Low-level input voltage 4.5 to 5.5 2 2 0.8 2 0.8 V 0.8 V High-level output voltage CMOS loads VOH = – 20 µA 4.5 4.4 4.4 4.4 V High-level output voltage TTL loads VOH = – 6 mA 4.5 3.98 3.84 3.7 V Low-level output voltage CMOS loads VOL = 20 µA 4.5 0.1 0.1 0.1 V Low-level output voltage TTL VOL = 6 mA 4.5 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 µA ICC Quiescent device current VI = VCC or GND 5.5 8 80 160 µA IOZ Three-state leakage current VO = VCC or GND 5.5 ±0.5 ±5 ±10 VOH VOL ∆ICC (1) (1) Additional quiescent device current per input pin DIR input held at VCC – 2.1 4.5 to 5.5 100 324 405 441 OE and A inputs held at vCC – 2.1 4.5 to 5.5 100 540 675 735 B input held at VCC – 2.1 4.5 to 5.5 100 540 675 735 µA For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 5 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 (2) 5.5 Switching Characteristics Input tt = 6ns. Unless otherwise specified, CL = 50pF PARAMETER VCC (V) tpd Propagation delay A to B B to A 4.5 tpd Propagation delay Output High-Z To high level, low level 4.5 Propagation delay Output high level Output lowe level to high Z 4.5 25°C MIN -40°C to 85°C TYP MAX MIN MAX -55°C to 125°C MIN MAX UNIT HC TYPES tpd tt Output transition time Ci Input Capacitance CO Three-state output capacitance Power dissipation capacitance Cpd (3) (4) 2 (1) 7 90 115 135 18 23 27 ns 6 15 20 23 2 150 190 225 30 38 45 26 33 38 150 190 225 30 38 45 6 26 33 38 2 60 75 90 4.5 12 15 18 6 10 13 15 10 10 10 pF 20 20 20 pF (1) 12 6 2 (1) 12 10 5 38 ns ns ns pF HCT TYPES tpd Propagation delay A to B B to A 4.5 9 tpd Propagation delay Output High-Z To high level, low level 4.5 12 tpd Propagation delay Output high level Output lowe level to high Z 4.5 12 tt Transition times 4.5 Ci Input capacitance CO Three-state output capacitance Cpd (1) (2) (3) (4) 6 Power dissipation capacitance (3) (4) (1) 22 28 (1) 30 38 ns (1) 30 38 ns 12 15 ns 10 10 pF 20 20 pF 10 5 41 33 ns pF Typical value tested at 5V, CL = 15pF. For details on CMOS power calculation see, SCAA053B CPD is used to determine the dynamic power consumption, per channel PD = VCC 2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 6 Parameter Measurement Information tPD is the maximum between tPLH and tPHL tt is the maximum between tTLH and tTHL Figure 6-1. HC transition times and propagation delay times, combination logic Figure 6-2. HCT transition times and propagation delay times, combination logic Figure 6-3. HC three-state propagation delay waveform Figure 6-4. HCT three-state propagation delay waveform NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is output RL = 1kΩ to VCC, CL = 50pF. Figure 6-5. HC and HCT three-state propagation delay test circuit Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 7 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 7 Detailed Description 7.1 Overview The CDx4HC640 and CDx4HCT640 silicon-gate CMOS three-state bidirectional inverting and non-inverting buffers are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high-speed operation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits, and have speeds comparable to low power Schottky TTL circuits. They can drive 15 LSTTL loads. The CDx4HC640 and CDx4HCT640 devices have inverting buffers. The direction of data flow (A to B, B to A) is controlled by the DIR input. Outputs are enabled by a low on the Output Enable input (OE); a high OE puts these devices in the high impedance mode. 7.2 Functional Block Diagram 7.3 Device Functional Modes (2) Table 7-1. Function Table Control Inputs(1) OE (1) (2) 8 Submit Document Feedback Data Port Status DIR An Bn L L O I H H Z Z H L Z Z L H I O H = High level. L = Low level. I = Input. O = Output (inversion of input level). Z = High impedance. To prevent excess currents in the High-Z modes all I/O terminals should be terminated with 1kΩ to 1MΩ resistors. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 9 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 www.ti.com SCHS192C – NOVEMBER 1998 – REVISED JULY 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 PACKAGE OPTION ADDENDUM www.ti.com 20-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8974001RA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8974001RA CD54HCT640F3A Samples CD54HC640F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8780901RA CD54HC640F3A Samples CD54HCT640F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8974001RA CD54HCT640F3A Samples CD74HC640E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC640E Samples CD74HC640M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC640M Samples CD74HCT640E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT640E Samples CD74HCT640M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT640M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of