CD74HC646M

CD74HC646 S IGN OR Data sheet acquired from Harris Semiconductor SCHS193A January 1998 - Revised May 2003 NE E OMM REC NOT DF NDE ES WD High-Speed CMOS Logic Octal Bus Transceiver/Register, Three-State Features Description • Independent Registers for A and B Buses The CD74HC646 is an octal bus transceiver/register with three-state non-inverting outputs. This device is a bus transceiver with D-type flip-flops which act as internal storage registers. Data on the A bus or the B bus can be clocked into the registers on the Low-to-High transition of either CAB or CBA clock inputs. Outputs enable (OE) and direction (DIR) inputs control the transceiver functions. Data present at the high impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The direction control determines which data bus will receive data when the output enable (OE) is Low. In the high impedance mode (output enable High), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the direction (DIR) and output enable (OE) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time. • Non-Inverting • Three-State Outputs • Drives 15 LSTTL Loads • Typical Propagation Delay = 12ns (A to B, B to A) at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Ordering Information PART NUMBER Pinout CD74HC646 (SOIC) TOP VIEW TEMP. RANGE (oC) CD74HC646M -55 to 125 24 Ld SOIC CD74HC646M96 -55 to 125 24 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. CAB 1 24 VCC SAB 2 23 CBA DIR 3 22 SBA A0 4 21 OE A1 5 20 B0 A2 6 19 B1 A3 7 18 B2 A4 8 17 B3 A5 9 16 B4 A6 10 15 B5 A7 11 14 B6 GND 12 13 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE 1 CD74HC646 Functional Diagram A0 A1 A2 A3 A DATA PORT A4 A5 A6 A7 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 21 OE DIR FLIP-FLOP CLOCKS DATA SOURCE SELECTION INPUTS CAB CLOCK CBA CLOCK SAB SOURCE SBA SOURCE B0 B1 B2 B3 B4 B DATA PORT B5 B6 B7 GND = PIN 12 VCC = PIN 24 3 1 23 2 22 FUNCTION TABLE INPUTS DATA I/O (NOTE 1) OE DIR CAB CBA SAB SBA A0 THRU A7 B0 THRU B7 OPERATION OR FUNCTION X X ↑ X X X Input Not Specified Store A, B Unspecified X X X ↑ X X Not Specified Input Store B, A Unspecified H X ↑ ↑ X X Input Input Store A and B Data H X H or L H or L X X L L X X X L L L X H or L X H L H X X L X L H H or L X H X Isolation, Hold Storage Output Input Real-Time B Data to A Bus Stored B Data to A Bus Input Output Real-Time A Data to B Bus Stored A Data to B Bus NOTE: 1. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data inputs functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. To prevent excess currents in the High-Z modes all I/O terminals should be terminated with 10kΩ resistors. 2 CD74HC646 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical) θJA (oC/W) M (SOIC) Package (Note 2). . . . . . . . . . . . . . . . . . . 46 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Output Voltage CMOS Loads VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V V 6 4.2 - - 4.2 - 4.2 - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V V -6 4.5 3.98 - - 3.84 - 3.7 - -7.8 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 6 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 µA Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 6 - - ±0.5 - ±5 - ±10 µA Input Leakage Current 3 CD74HC646 Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS fMAX 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz 2 60 - - 75 - - 90 - - ns 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns 2 35 - - 45 - - 55 - - ns 4.5 7 - - 9 - - 11 - - ns 6 6 - - 8 - - 9 - - ns 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns HC TYPES Maximum Frequency Setup Time Data to Clock Hold Time Data to Clock Clock Pulse Width tSU tH tW Switching Specifications CL = 50pF, Input tr, tf = 6ns -40oC TO 85oC 25oC PARAMETER SYMBOL TEST CONDITIONS tPHL, tPLH CL = 50pF -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 220 - 275 - 330 ns 4.5 - - 44 - 55 - 66 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 6 - - 37 - 47 - 56 ns CL = 50pF 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns CL = 50pF 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 29 - 37 - 43 ns HC TYPES Propagation Delay Store A Data to B Bus Store B Data to B Bus A Data to B Bus B Data to A Bus Select to Data tPLH, tPHL tPLH, tPHL 4 CD74HC646 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC PARAMETER Three-State Disabling Time Bus to Output or Register to Output Three-State Enabling Time Bus to Output or Register to Output Output Transition Time -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLZ, tPHZ CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns CL = 50pF 6 - - 10 - 13 - 15 ns tPZL, tPZH tTLH, tTHL Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output Capacitance CO - - - - 20 - 20 - 20 pF Maximum Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Power Dissipation Capacitance (Notes 3, 4) CPD - 5 - 52 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 CPD fi Σ VCC2 CL fo where fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5 CD74HC646 Test Circuits and Waveforms tr = 6ns tWL + tWH = tfCL trCL 50% 10% 10% 50% 50% GND tTHL tTLH GND tWH tWL 90% 50% 10% INVERTING OUTPUT NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPLH tPHL FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 2. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tfCL trCL CLOCK INPUT VCC 90% 50% 10% INPUT VCC 90% CLOCK I fCL tf = 6ns VCC 90% 50% 10% GND tH(H) tH(L) VCC DATA INPUT 50% GND tSU(H) tSU(L) tTLH 90% OUTPUT 6ns OUTPUT DISABLE 50% tPHZ GND OUTPUT HIGH TO OFF CL 50pF 50% OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 4. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS OUTPUT DISABLE tPZH 90% OUTPUTS ENABLED IC WITH THREESTATE OUTPUT GND tPZL 10% 50% OTHER INPUTS TIED HIGH OR LOW 10% tPLZ OUTPUT LOW TO OFF IC VCC 90% 50% tPHL tPLH tREM VCC SET, RESET OR PRESET 6ns tTHL 90% 50% 10% OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5. HC THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6 PACKAGE OPTION ADDENDUM www.ti.com 2-Mar-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CD74HC646EN OBSOLETE PDIP NT 24 TBD Call TI Call TI CD74HC646ENE4 OBSOLETE PDIP NT 24 TBD Call TI Call TI CD74HC646M OBSOLETE SOIC DW 24 TBD Call TI Call TI CD74HC646M96 OBSOLETE SOIC DW 24 TBD Call TI Call TI CD74HC646M96E4 OBSOLETE SOIC DW 24 TBD Call TI Call TI CD74HC646ME4 OBSOLETE SOIC DW 24 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD74HC646 : • Military: CD54HC646 NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CD74HC646EN OBSOLETE PDIP NT 24 TBD Call TI Call TI Samples Not Available CD74HC646ENE4 OBSOLETE PDIP NT 24 TBD Call TI Call TI Samples Not Available CD74HC646M OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available CD74HC646M96 OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available CD74HC646M96E4 OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available CD74HC646ME4 OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD74HC646 : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 • Military: CD54HC646 NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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