CD74HC7266MT

CD74HC7266, CD54HC7266 ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 CDx4HC7266 四路 2 输入异或非门 1 特性 3 说明 • • • • • 此器件包含四个独立双输入或非门。每个逻辑门以正逻 辑执行布尔函数 Y = A ⊕ B。 缓冲输入 宽工作电压范围：2V 至 6V 宽工作温度范围：-55°C 至 +125°C 支持多达 10 个 LSTTL 负载的扇出 与 LSTTL 逻辑 IC 相比，可显著降低功耗 器件信息(1) 2 应用 • 检测输入信号中的相位差 • 创建可选的逆变器/缓冲器 封装 CD74HC7266M SOIC (14) 8.70mm × 3.90mm CD74HC7266E PDIP (14) 19.30mm × 6.40mm CD54HC7266F CDIP (14) 21.30mm × 7.60mm (1) 1A 1B 1Y 2Y 2A 2B GND 封装尺寸（标称值） 器件型号 如需了解所有可用封装，请参阅数据表末尾的可订购产品附 录。 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3Y 3B 3A 功能引脚分配 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SCHS219 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 Table of Contents 1 特性................................................................................... 1 2 应用................................................................................... 1 3 说明................................................................................... 1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 Recommended Operating Conditions.........................4 6.3 Thermal Information....................................................4 6.4 Electrical Characteristics.............................................5 6.5 Switching Characteristics............................................5 6.6 Operating Characteristics........................................... 6 6.7 Typical Characteristics................................................ 6 7 Parameter Measurement Information............................ 7 8 Detailed Description........................................................8 8.1 Overview..................................................................... 8 8.2 Functional Block Diagram........................................... 8 8.3 Feature Description.....................................................8 8.4 Device Functional Modes............................................9 9 Application and Implementation.................................. 10 9.1 Application Information............................................. 10 9.2 Typical Application.................................................... 10 10 Power Supply Recommendations..............................12 11 Layout........................................................................... 13 11.1 Layout Guidelines................................................... 13 11.2 Layout Example...................................................... 13 12 Device and Documentation Support..........................14 12.1 Documentation Support.......................................... 14 12.2 支持资源..................................................................14 12.3 Trademarks............................................................. 14 12.4 静电放电警告.......................................................... 14 12.5 术语表..................................................................... 14 13 Mechanical, Packaging, and Orderable Information.................................................................... 14 4 Revision History 注：以前版本的页码可能与当前版本的页码不同 Changes from Revision D (September 2003) to Revision E (June 2021) Page • 更新至全新的数据表标准.................................................................................................................................... 1 • RθJA increased for the D package (86 to 133.6 ℃/W) and decreased for the N package (80 to 64.8 ℃/W).....4 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 5 Pin Configuration and Functions 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2Y 4 11 4Y 2A 5 10 3Y 2B 6 9 3B GND 7 8 3A D, N, or J Package 14-Pin SOIC, PDIP, or CDIP Top View Pin Functions PIN NAME NO. I/O DESCRIPTION 1A 1 Input Channel 1, Input A 1B 2 Input Channel 1, Input B 1Y 3 Output Channel 1, Output Y 2Y 4 Output Channel 2, Output Y 2A 5 Input Channel 2, Input A 2B 6 Input Channel 2, Input B GND 7 — 3A 8 Input Channel 3, Input A Channel 3, Input B Ground 3B 9 Input 3Y 10 Output Channel 3, Output Y 4Y 11 Output Channel 4, Output Y 4A 12 Input Channel 4, Input A 4B 13 Input Channel 4, Input B VCC 14 — Positive Supply Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 3 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output clamp current(2) VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Continuous output current VO > –0.5 V or VO < VCC + 0.5 V ±25 mA Continuous current through VCC or GND ±50 mA Junction temperature(3) 150 °C 300 °C 150 °C TJ Lead temperature (soldering 10s) Tstg (1) (2) (3) SOIC - lead tips only Storage temperature –65 V Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Guaranteed by design. 6.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VIH High-level input voltage MIN NOM MAX 2 5 6 VCC = 2 V VCC = 4.5 V V 4.2 VCC = 2 V 0.5 VCC = 4.5 V Low-level input voltage V 1.5 3.15 VCC = 6 V VIL UNIT 1.35 VCC = 6 V V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V tt Input transition time TA Operating free-air temperature VCC = 2 V 1000 VCC = 4.5 V 500 VCC = 6 V ns 400 –55 125 °C 6.3 Thermal Information CD74HC7266 THERMAL METRIC(1) 4 N (PDIP) D (SOIC) UNIT 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 64.8 133.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.6 89.0 °C/W RθJB Junction-to-board thermal resistance 44.6 89.5 °C/W ΨJT Junction-to-top characterization parameter 32.2 45.5 °C/W ΨJB Junction-to-board characterization parameter 44.3 89.1 °C/W Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 CD74HC7266 THERMAL METRIC(1) RθJC(bot) (1) N (PDIP) D (SOIC) 14 PINS 14 PINS N/A N/A Junction-to-case (bottom) thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.4 Electrical Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) PARAMETER TEST CONDITIONS VCC 25°C MIN 2V VOH High-level output voltage IOH = –20 4.5 V µA 6V VI = VIH or IOH = –4 VIL mA 4.5 V IOH = –5.2 6V mA VOL MAX MIN TYP UNIT –55°C to 125°C MAX MIN 1.9 1.9 1.9 4.4 4.4 4.4 5.9 5.9 5.9 3.98 3.84 3.7 5.48 5.34 5.2 TYP MAX V 2V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 6V 0.1 0.1 0.1 IOL = 4 mA 4.5 V 0.26 0.33 0.4 IOL = 5.2 mA 6V 0.26 0.33 0.4 IOL = 20 µA Low-level output VI = VIH or voltage VIL TYP –40°C to 85°C V II Input leakage current VI = VCC or 0 6V ±0.1 ±1 ±1 µA ICC Supply current VI = VCC or IO = 0 0 6V 2 20 40 µA Ci Input capacitance 5V 10 10 10 pF 6.5 Switching Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER FROM TO TEST CONDITIO NS Operating free-air temperature (TA) VCC 25°C –40°C to 85°C –55°C to 125°C UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 2V tpd Propagation delay A or B A or B tt Transition-time Y CL = 50 pF Y CL = 15 pF Y CL = 50 pF 115 145 150 4.5 V 23 29 35 6V 30 25 30 2V 75 95 110 4.5 V 15 19 22 6V 13 16 19 5V ns 9 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 ns 5 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 6.6 Operating Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS Power dissipation capacitance No load per gate Cpd VCC MIN 2 V to 6 V TYP MAX UNIT 33 pF 6.7 Typical Characteristics TA = 25°C 0.3 7 VOL Output Low Voltage (V) VOH Output High Voltage (V) 6 5 4 3 2 2-V 4.5-V 6-V 1 0 0.25 0.2 0.15 0.1 0.05 0 0 1 2 3 4 IOH Output High Current (mA) 5 6 图 6-1. Typical output voltage in the high state (VOH) 6 2-V 4.5-V 6-V 0 1 2 3 4 IOL Output Low Current (mA) 5 6 图 6-2. Typical output voltage in the low state (VOL) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 7 Parameter Measurement Information • Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. • The outputs are measured one at a time, with one input transition per measurement. Test Point 90% VCC 90% Input 10% 10% tr(1) From Output Under Test CL(1) 0V tf(1) 90% VOH 90% Output 10% A. 10% tr(1) CL= 50 pF and includes probe and jig capacitance. A. 图 7-1. Load Circuit tf(1) VOL tt is the greater of tr and tf. 图 7-2. Voltage Waveforms Transition Times VCC Input 50% 50% 0V tPHL(1) tPLH(1) VOH Output 50% 50% VOL tPLH(1) tPHL(1) VOH Output 50% 50% VOL A. The maximum between tPLH and tPHL is used for tpd. 图 7-3. Voltage Waveforms Propagation Delays Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 7 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 8 Detailed Description 8.1 Overview This device contains four independent 2-input XNOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic. 8.2 Functional Block Diagram xA xY xB 8.3 Feature Description 8.3.1 Balanced CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the 节 6.1 must be followed at all times. The CD74HC7266 can drive a load with a total capacitance less than or equal to the maximum load listed in the 节 6.5 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output and the capacitor to limit output current to the values given in the 节 6.1. 8.3.2 Standard CMOS Inputs Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the 节 6.4. The worst case resistance is calculated with the maximum input voltage, given in the 节 6.1, and the maximum input leakage current, given in the 节 6.4, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the 节 6.2 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input. 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in 图 8-1. CAUTION Voltages beyond the values specified in the 节 6.1 table can cause damage to the device. The recommended input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. Device VCC +IIK +IOK Logic Input -IIK Output -IOK GND 图 8-1. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes 表 8-1. Function Table INPUTS A OUTPUT B Y L L H L H L H L L H H H Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 9 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 9 Application and Implementation 备注 以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定 器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 9.1 Application Information In this application, a 2-input XNOR gate is used as a phase difference detector as shown in 图 9-1. The remaining three gates can be used for other applications in the system, or the inputs can be grounded and the channels left unused. The device is used to identify phase difference between a reference clock and another input clock. Whenever the clock states are different, the XNOR output will pulse HIGH until the clocks return to the same state. The output is fed into a low-pass filter to obtain a DC representation of the phase difference. 9.2 Typical Application Input Clock R Output Reference Clo ck C 图 9-1. Typical application schematic 9.2.1 Design Requirements 9.2.1.1 Power Considerations Ensure the desired supply voltage is within the range specified in the 节 6.2. The supply voltage sets the device's electrical characteristics as described in the 节 6.4. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the CD74HC7266 plus the maximum supply current, ICC, listed in the 节 6.4. The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the 节 6.1. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the 节 6.1, is an additional limitation to prevent damage to the device. Do not violate any values listed in the 节 6.1. These limits are provided to prevent damage to the device. 9.2.1.2 Input Considerations Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the CD74HC7266, as specified in the 节 6.4, and the desired input transition rate. A 10-kΩ resistor value is often used due to these factors. 10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 The CD74HC7266 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the 节 6.2. Refer to the 节 8.3 for additional information regarding the inputs for this device. 9.2.1.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the 节 6.4. Similarly, the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the 节 6.4. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to 节 8.3 for additional information regarding the outputs for this device. 9.2.2 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the 节 11. 2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC7266 to the receiving device. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the 节 6.1 is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation 9.2.3 Application Curves Ref. Clock Input Clock Out 图 9-2. Typical application timing diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 11 CD74HC7266, CD54HC7266 ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 www.ti.com.cn 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the 节 6.2. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in 图 11-1. 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 CD74HC7266, CD54HC7266 www.ti.com.cn ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 0.1 F Avoid 90° corners for signal lines Bypass capacitor placed close to the device 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2Y 4 11 4Y 2A 5 10 3Y 2B 6 9 3B GND 7 8 3A Unused inputs tied to VCC Unused output left floating 图 11-1. Example layout for the CD74HC7266 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 13 CD74HC7266, CD54HC7266 ZHCSOB5E – NOVEMBER 1998 – REVISED JUNE 2021 www.ti.com.cn 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • HCMOS Design Considerations • CMOS Power Consumption and CPD Calculation • Designing with Logic 12.2 支持资源 TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解 答或提出自己的问题可获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. 所有商标均为其各自所有者的财产。 12.4 静电放电警告 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理 和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参 数更改都可能会导致器件与其发布的规格不相符。 12.5 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: CD74HC7266 CD54HC7266 PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 8404302CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404302CA CD54HC7266F3A CD54HC7266F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404302CA CD54HC7266F3A CD74HC7266E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC7266E CD74HC7266M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC7266M CD74HC7266M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC7266M CD74HC7266MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC7266M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of