CD74HC85PWE4

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 CDx4HC85, CDx4HCT85 High-Speed CMOS Logic 4-Bit Magnitude Comparator 1 Features 2 Description • • The ’HC85 and ’HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. • • • • • • • Buffered inputs and outputs Typical propagation delay: 13 ns (data to output at VCC = 5 V, CL = 15 pF, TA = 25℃) Serial or parallel expansion without external gating Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads Wide operating temperature range: –55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min) – CMOS input compatibility, II ≤ 1 μA at VOL, VOH These 4-bit devices compare two binary, BCD, or other monotonic codes and present the three possible magnitude results at the outputs (A > B, A < B, and A = B). The 4-bit input words are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD54HC85F3A CDIP (16) 24.38 mm × 6.92 mm CD54HCT85F3A CDIP (16) 24.38 mm × 6.92 mm CD74HC85M SOIC (16) 9.90 mm × 3.90 mm CD74HCT85M SOIC (16) 9.90 mm × 3.90 mm CD74HC85E PDIP (16) 19.31 mm × 6.35 mm CD74HCT85E PDIP (16) 19.31 mm × 6.35 mm CD74HC85NS SO (16) 6.20 mm × 5.30 mm CD74HC85PW TSSOP (16) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings(1) .................................... 4 5.2 Recommended Operating Conditions ........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Specifications............................................. 6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Device Functional Modes..........................................10 8 Power Supply Recommendations................................11 9 Layout............................................................................. 11 9.1 Layout Guidelines..................................................... 11 10 Device and Documentation Support..........................12 10.1 Receiving Notification of Documentation Updates..12 10.2 Support Resources................................................. 12 10.3 Trademarks............................................................. 12 10.4 Electrostatic Discharge Caution..............................12 10.5 Glossary..................................................................12 11 Mechanical, Packaging, and Orderable Information.................................................................... 12 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2003) to Revision F (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 4 Pin Configuration and Functions J, N, D, NS, or PW package 16-Pin CDIP, PDIP, SOIC, SO, or TSSOP Top View Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 Submit Document Feedback 3 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 5 Specifications 5.1 Absolute Maximum Ratings(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA ICC Continuous current through VCC or GND ±50 mA TJ Junction temperature 150 °C Tstg Storage temperature range 150 °C 300 °C –65 Lead temperature (Soldering 10s) (SOIC - lead tips only) (1) V Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 5.2 Recommended Operating Conditions MIN VCC Supply voltage range VI, VO Input or output voltage HC types HCT types MAX 2 6 4.5 5.5 0 VCC 2V Input rise and fall time TA UNIT V V 1000 4.5 V 500 6V 400 Temperature range –55 125 ns ℃ 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal (1) resistance D (SOIC) N (PDIP) NS (SO) PW (TSSOP) 16 PINS 16 PINS 16 PINS 16 PINS UNIT 73 67 64 108 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS(1) VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES VIH VIL VOH High level input voltage Low level input voltage High level output voltage High level output voltage VOL Low level output voltage Low level output voltage II Input leakage current ICC Supply current 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = – 20 μA 2 1.9 1.9 1.9 IOH = – 20 μA 4.5 4.4 4.4 4.4 IOH = – 20 μA 6 5.9 5.9 5.9 IOH = – 4 mA 4.5 3.98 3.84 3.7 IOH = – 5.2 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 5.34 V V 5.2 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 IOL = 4 mA 4.5 0.26 0.33 0.4 IOL = 5.2 mA 6 0.26 0.33 0.4 V 6 ±0.1 ±1 ±1 μA 6 8 80 160 μA VI = VCC or GND V HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 0.8 V 0.8 V 4.5 4.4 4.4 4.4 High level output voltage IOH = – 4 μA 4.5 3.98 3.84 3.7 Low level output voltage IOL = 20 μA 4.5 Low level output voltage IOL = 4 μA 4.5 0.26 0.33 0.4 VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA 8 80 160 μA ICC Supply current (1) (2) (3) 0.8 2 IOH = – 20 μA Input leakage current (2) 2 High level output voltage II ΔICC 2 Additional supply current per input pin V 0.1 0.1 0.1 V VI = VCC or GND 5.5 A0 - A3, B0 - B3 and (A = B) IN(3) 4.5 to 5.5 100 540 675 735 μA (A > B) IN, (A < B) IN(3) 4.5 to 5.5 100 360 450 490 μA VI = VIH or VIL, unless otherwise noted. For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. Inputs held at VCC – 2.1. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 Submit Document Feedback 5 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 5.5 Switching Specifications Input tr, tf = 6 ns PARAMETER VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES 2 Propagation delay, tPLH, tPHL An, Bn to (A > B) OUT, (A < B) OUT 4.5 (3) 42 50 240 265 35 44 53 30 37 45 140 175 210 28 35 42 24 30 36 120 150 180 24 30 36 20 26 31 14 (3) 4.5 11 (3) 2 4.5 (3) 9 6 Power dissipation capacitance(1) (2) CPD tTLH, tTHL Output transition times (Figure 6-1) CIN 59 33 6 tPLH, tPHL (A > B) IN to (A = B) OUT 295 47 175 2 (A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT 245 39 2 6 tPLH, tPHL 195 6 4.5 tPLH, tPHL An, Bn to (A = B) OUT 16 5 24 ns ns ns ns pF 2 75 95 110 4.5 15 19 22 6 13 16 19 10 10 10 pF Input capacitance ns HCT TYPES Propagation delay, An, Bn to (A > B) OUT, (A < B) OUT 4.5 15 (3) 37 46 56 ns 4.5 17 (3) 40 50 60 ns 4.5 12 (3) 30 38 45 ns tPLH, tPHL (A > B) IN to (A = B) OUT 4.5 13 (3) 31 39 47 ns tTLH, tTHL Output transition times (Figure 6-1) 4.5 15 19 22 ns 10 10 10 tPLH, tPHL tPLH, tPHL An, Bn to (A = B) OUT tPLH tPHL CPD Power dissipation CIN Input capacitance (1) (2) (3) 6 (A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT capacitance(1) (2) 5 26 pF pF CPD is used to determine the dynamic power consumption, per gate/package. PD = VCC 2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 6 Parameter Measurement Information Figure 6-1. HC and HCU Transition Times and Propagation Delay Times, Combination Logic Figure 6-2. HCT Transition Times and Propagation Delay Times, Combination Logic Figure 6-3. Series Cascading - Comparing 12-Bit Words Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 Submit Document Feedback 7 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 Figure 6-4. Parallel Cascading - Comparing 12-Bit Words 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 7 Detailed Description 7.1 Overview The ’HC85 and ’HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. These 4-bit devices compare two binary, BCD, or other monotonic codes and present the three possible magnitude results at the outputs (A > B, A < B, and A = B). The 4-bit input words are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. The devices are expandable without external gating, in both serial and parallel fashion. The upper part of the truth table indicates operation using a single device or devices in a serially expanded application. The parallel expansion scheme is described by the last three entries in the truth table. 7.2 Functional Block Diagram Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 Submit Document Feedback 9 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 7.3 Device Functional Modes Table 7-1. Truth Table(1) COMPARING INPUTS A3, B3 A2, B2 CASCADING INPUTS A1, B1 OUTPUTS A0, B0 A>B AB A B3 X X X X X X H L L A3 < B3 X X X X X X L H L A3 = B3 A2 >B2 X X X X X H L L A3 = B3 A2 < B2 X X X X X L H L A3 = B3 A2 = B2 A1 > B1 X X X X H L L A3 = B3 A2 = B2 A1 < B1 X X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H PARALLEL CASCADING (1) 10 A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H A3 = B3 A2 = B2 A1 = B1 A0 = B0 H H L L L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L L H H L H = high voltage level, L = low voltage level, X = don’t care Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 Submit Document Feedback 11 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 www.ti.com SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) (1) 5962-8867201EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8867201EA CD54HCT85F3A Samples 8601301EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8601301EA CD54HC85F3A Samples CD54HC85F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8601301EA CD54HC85F3A Samples CD54HCT85F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8867201EA CD54HCT85F3A Samples CD74HC85E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC85E Samples CD74HC85EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC85E Samples CD74HC85M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC85M Samples CD74HC85M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC85M Samples CD74HC85M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC85M Samples CD74HC85MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC85M Samples CD74HC85MTE4 ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC85M Samples CD74HC85NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC85M Samples CD74HC85PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ85 Samples CD74HC85PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ85 Samples CD74HC85PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ85 Samples CD74HCT85E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT85E Samples CD74HCT85M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT85M Samples CD74HCT85MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT85M Samples The marketing status values are defined as follows: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of