CD74HC93M96

[ /Title (CD74 HC93, CD74 HCT93 ) /Subject (High Speed CMOS Logic 4-Bit Binary Ripple Counte r) CD74HC93, CD74HCT93 Data sheet acquired from Harris Semiconductor SCHS138C High-Speed CMOS Logic 4-Bit Binary Ripple Counter August 1997 - Revised September 2003 Features Description • Can Be Configured to Divide By 2, 8, and 16 The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. • Asynchronous Master Reset • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops. • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Pinout Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, Q3 outputs. Independent use of the first flipflop is available if the reset function coincides with the reset of the 3-bit ripple-through counter. CD74HC93 (PDIP, SOIC) CD74HCT93 (PDIP) TOP VIEW Ordering Information CP1 1 14 CPO MR1 2 13 NC MR2 3 12 Q0 NC 4 11 Q3 VCC 5 PART NUMBER 10 GND NC 6 9 Q1 NC 7 8 Q2 TEMP. RANGE (oC) PACKAGE CD74HC93E -55 to 125 14 Ld PDIP CD74HC93M -55 to 125 14 Ld SOIC CD74HC93MT -55 to 125 14 Ld SOIC CD74HC93M96 -55 to 125 14 Ld SOIC CD74HCT93E -55 to 125 14 Ld PDIP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD74HC93, CD74HCT93 TRUTH TABLE OUTPUTS COUNT Q0 Q1 Q2 Q3 0 L L L L 1 H L L L 2 L H L L 3 H H L L 4 L L H L 5 H L H L 6 L H H L 7 H H H L 8 L L L H 9 H L L H 10 L H L H 11 H H L H 12 L L H H 13 H L H H 14 L H H H 15 H H H H H = High Voltage Level, L = Low Voltage Level MODE SELECTION RESET OUTPUTS OUTPUTS MR1 MR2 Q0 Q1 Q2 Q3 H H L L L L L H Count Count Count Count H L L L H = High Voltage Level, L = Low Voltage Level 2 CD74HC93, CD74HCT93 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD74HC93, CD74HCT93 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS CP0, CP1 0.6 MR1, MR2 0.4 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN MAX MIN MAX MIN MAX UNITS fMAX 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns HC TYPES Maximum Clock Frequency Clock Pulse Width CP0, CP1 tw 4 CD74HC93, CD74HCT93 Prerequisite For Switching Specifications PARAMETER (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN MAX MIN MAX MIN MAX UNITS tW 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns Reset Pulse Width Reset Removal Time tREM HCT TYPES Maximum Clock Frequency fMAX 4.5 30 - 24 - 20 - mHz Clock Pulse Width CP0, CP1 tW 4.5 16 - 20 - 24 - ns Reset Pulse Width tW 4.5 16 - 20 - 24 - ns tREM 4.5 10 - 13 - 15 - ns Reset Removal Time Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CL = 50pF 2 - - 125 - 155 - 190 ns CL = 50pF 4.5 - - 25 - 31 - 38 ns CL = 15pF 5 - 10 - - - - ns CL = 50pF 6 - - 21 - 26 - 32 ns CL = 50pF 2 - 135 - 170 - 205 ns CL = 50pF 4.5 - 27 - 34 - 41 ns CL = 50pF 6 - 23 - 29 - 35 ns HC TYPES Propagation Delay Time tPLH, tPHL CP0 to Q0 CP1 to Q1 CP1 to Q2 CP1 to Q3 MR1, MR2 to Qn Output Transition Time tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL Input Capacitance CIN Power Dissipation Capacitance CPD CL = 50pF 2 - 185 - 230 - 280 ns CL = 50pF 4.5 - 37 - 46 - 56 ns CL = 50pF 6 - 31 - 39 - 48 ns CL = 50pF 2 - 245 - 305 - 370 ns CL = 50pF 4.5 - 49 - 61 - 74 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 42 - 52 - 63 ns CL = 50pF 2 - 155 - 195 - 235 ns CL = 50pF 4.5 - 31 - 39 - 47 ns CL = 15pF 5 - - - ns CL = 50pF 6 - CL = 50pF 2 - 4.5 CL = 50pF - 13 26 - 33 - 40 ns - 75 - 95 - 110 ns - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - - - 10 - 10 - 10 pF - - 25 - - 10 - 19 pF 5 CD74HC93, CD74HCT93 Switching Specifications PARAMETER Input tr, tf = 6ns (Continued) SYMBOL 25oC -40oC TO 85oC -55oC TO 125oC TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CL = 50pF 4.5 - - 34 - 43 - 51 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 4.5 - - 34 - 43 - 51 ns CL = 15pF 5 - - - - - - - ns CL = 50pF 4.5 - - 46 - 58 - 69 ns CL = 15pF 5 - - - - - - - ns CL = 50pF 4.5 - - 58 - 73 - 87 ns CL = 15pF 5 - 24 - - - - - ns CL = 50pF 4.5 - - 33 - 41 - 50 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 4.5 - - 15 - 19 - 22 ns CL = 50pF - - - 10 - 10 - 10 pF - - 25 - - - - - pF HCT TYPES Propagation Delay Time tPLH, tPHL CP0 to Q0 CP1 to Q1 tPLH, tPHL CP1 to Q2 tPLH, tPHL CP1 to Q3 tPLH, tPHL MR1, MR2 to Qn tPLH, tPHL Output Transition Time tTLH, tTHL Input Capacitance CIN Power Dissipation Capacitance CPD - Test Circuits and Waveforms CLOCK INPUT trCL tfCL trCL VCC 90% CLOCK INPUT 50% 10% GND tH(H) 3V 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET tfCL 2.7V CL 50pF FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD74HC93E ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC93E CD74HC93EE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC93E CD74HC93M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC93M CD74HC93M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC93M CD74HC93MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC93M CD74HCT93E ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT93E CD74HCT93EE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT93E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of