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CD74HCT125M96G4

CD74HCT125M96G4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC14_150MIL

  • 描述:

    Buffer, Non-Inverting 4 Element 1 Bit per Element Push-Pull Output 14-SOIC

  • 数据手册
  • 价格&库存
CD74HCT125M96G4 数据手册
CD74HCT125, CD54HCT125 SCHS415 – JUNE 2020 CDx4HCT125 Quadruple Buffers with 3-State Outputs 1 Features 3 Description • This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic. • • • • • • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V CMOS input logic compatible – II ≤ 1 µA at VOL, VOH Buffered inputs 4.5 V to 5.5 V operation Wide operating temperature range: -55°C to +125°C Supports fanout up to 10 LSTTL loads Significant power reduction compared to LSTTL logic ICs Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT125M SOIC (14) 8.70 mm × 3.90 mm CD74HCT125E PDIP (14) 19.30 mm × 6.40 mm CD54HCT125F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • Enable digital signals 1 14 VCC 2 13 4OE 3 4 12 11 4A 2A 5 10 3OE 2Y 6 7 9 8 1OE 1A 1Y 2OE GND 4Y 3A 3Y Functional pinout An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 Recommended Operating Conditions.........................4 6.3 Thermal Information....................................................4 6.4 Electrical Characteristics.............................................5 6.5 Switching Characteristics............................................5 6.6 Operating Characteristics........................................... 5 6.7 Typical Characteristics................................................ 5 7 Parameter Measurement Information............................ 7 8 Detailed Description........................................................8 8.1 Overview..................................................................... 8 8.2 Functional Block Diagram........................................... 8 8.3 Feature Description.....................................................8 8.4 Device Functional Modes............................................9 9 Application and Implementation.................................. 10 9.1 Application Information............................................. 10 9.2 Typical Application.................................................... 10 10 Power Supply Recommendations..............................12 11 Layout........................................................................... 13 11.1 Layout Guidelines................................................... 13 11.2 Layout Example...................................................... 13 12 Device and Documentation Support..........................14 12.1 Documentation Support.......................................... 14 12.2 Support Resources................................................. 14 12.3 Trademarks............................................................. 14 12.4 Electrostatic Discharge Caution..............................14 12.5 Glossary..................................................................14 13 Mechanical, Packaging, and Orderable Information.................................................................... 14 4 Revision History 2 DATE REVISION NOTES June 2020 * Initial release. Moved the HCT devices from the SCHS143 to a standalone data sheet. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 5 Pin Configuration and Functions 1 14 VCC 2 13 4OE 3 4 12 11 4A 2A 5 10 3OE 2Y 6 7 9 8 1OE 1A 1Y 2OE GND 4Y 3A 3Y Figure 5-1. D, N, or J Package 14-Pin SOIC, PDIP, or CDIP Top View Pin Functions PIN NAME NO. I/O DESCRIPTION 1 OE 1 Input Channel 1, Output Enable, Active Low 1A 2 Input Channel 1, Input A 1Y 3 Output 2 OE 4 Input Channel 2, Output Enable, Active Low 2A 5 Input Channel 2, Input A 2Y 6 Output GND 7 — 3Y 8 Output 3A 9 Input Channel 3, Input A 3 OE 10 Input Channel 3, Output Enable, Active Low 4Y 11 Output 4A 12 Input Channel 4, Input A 4 OE 13 Input Channel 4, Output Enable, Active Low VCC 14 — Copyright © 2021 Texas Instruments Incorporated Channel 1, Output Y Channel 2, Output Y Ground Channel 3, Output Y Channel 4, Output Y Positive Supply Submit Document Feedback 3 CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output clamp current(2) VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Continuous output current VO > –0.5 V or VO < VCC + 0.5 V ±35 mA ±70 mA Continuous current through VCC or GND TJ Junction temperature(3) Lead temperature (soldering 10s) Tstg (1) (2) (3) SOIC - lead tips only Storage temperature –65 V 150 °C 300 °C 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Guaranteed by design. 6.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage 4.5 VIH High-level input voltage VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V NOM MAX UNIT 5.5 V 0.8 V 2 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V tt Input transition time TA Operating free-air temperature VCC = 4.5 V 500 VCC = 5.5 V 400 –55 125 ns °C 6.3 Thermal Information CD74HCT125 THERMAL N (PDIP) D (SOIC) 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 61.5 96.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.3 53.3 °C/W RθJB Junction-to-board thermal resistance 41.3 52.4 °C/W ΨJT Junction-to-top characterization parameter 28.9 15.8 °C/W ΨJB Junction-to-board characterization parameter 41.0 52.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 4 METRIC(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 6.4 Electrical Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) PARAMETER TEST CONDITIONS VCC 25°C MIN VOH VOL High-level output voltage IOH = –20 VI = VIH or µA VIL IOH = –4 mA TYP –40°C to 85°C MAX MIN TYP –55°C to 125°C MAX MIN 4.5 V 4.4 4.4 4.4 4.5 V 3.98 3.84 3.7 TYP UNIT MAX V IOL = 20 4.5 V Low-level output VI = VIH or µA voltage VIL IOL = 4 mA 4.5 V 0.1 0.1 0.1 0.26 0.33 0.4 5.5 V ±0.1 ±1 ±1 µA V II Input leakage current VI = VCC and GND IOZ Three-state leakage current VI = VIH or VIL 5.5 V ±0.5 ±5 ±10 µA ICC Supply current VI = VCC or IO = 0 GND 5.5 V 8 80 160 µA (1) Additional Quiescent Device Current Per Input Pin. VI = VCC – 2.1 4.5 V to 5.5 V 360 450 490 µA Ci Input capacitance 10 10 10 pF Co Three-state output capacitance 20 20 20 pF ΔICC (1) IO = 0 100 For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. 6.5 Switching Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER FROM TO tpd Propagation delay A Y ten Enable delay OE Y tdis Disable delay OE Y tt Transition-time Y Operating free-air temperature (TA) TEST CONDITIO NS VCC CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V 25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX 25 31 38 25 31 38 28 35 42 12 15 18 UNIT ns 10 ns 10 ns 11 ns 6.6 Operating Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load per gate VCC 5V MIN TYP 34 MAX UNIT pF 6.7 Typical Characteristics TA = 25°C Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 CD74HCT125, CD54HCT125 www.ti.com 7 0.3 6 0.25 VOL Output Low Voltage (V) VOH Output High Voltage (V) SCHS415 – JUNE 2020 5 4 3 2 2-V 4.5-V 6-V 1 0 0.2 0.15 0.1 0.05 0 0 1 2 3 4 IOH Output High Current (mA) 5 6 Figure 6-1. Typical output voltage in the high state (VOH) 6 2-V 4.5-V 6-V Submit Document Feedback 0 1 2 3 4 IOL Output Low Current (mA) 5 6 Figure 6-2. Typical output voltage in the low state (VOL) Copyright © 2021 Texas Instruments Incorporated CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 7 Parameter Measurement Information • • Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. The outputs are measured one at a time, with one input transition per measurement. VCC Test Point 90% Input 10% 10% S1 tr(1) RL From Output Under Test CL(1) 90% S2 0V tf(1) VOH 90% Output 10% A. VCC 90% 10% tr(1) CL= 50 pF and includes probe and jig capacitance. A. Figure 7-1. Load Circuit tf(1) VOL tt is the greater of tr and tf. Figure 7-2. Voltage Waveforms Transition Times VCC Output Control 50% 50% 0V tPZL(3) Output Waveform 1 S1 at VLOAD(1) § 9CC 50% 10% VOL tPZH(3) Output Waveform 2 S1 at GND(2) A. tPLZ(4) tPHZ(4) 90% VOH 50% §0V The maximum between tPLH and tPHL is used for tpd. Figure 7-3. Voltage Waveforms Propagation Delays Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 8 Detailed Description 8.1 Overview This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic. 8.2 Functional Block Diagram xOE xA xY 8.3 Feature Description 8.3.1 Balanced CMOS 3-State Outputs A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to over-current. The electrical and thermal limits defined in the Section 6.1 must be followed at all times. The CD74HCT125 can drive a load with a total capacitance less than or equal to the maximum load listed in the Section 6.5 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output and the capacitor to limit output current to the values given in the Section 6.1. 3-State outputs can be placed into a high-impedance state. In this state, the output will neither source nor sink current, and leakage current is defined by the IOZ specification in the Section 6.4. A pull-up or pull-down resistor can be used to ensure that the output remains HIGH or LOW, respectively, during the high-impedance state. 8.3.2 TTL-Compatible CMOS Inputs TTL-Compatible CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the Section 6.4. The worst case resistance is calculated with the maximum input voltage, given in the Section 6.1, and the maximum input leakage current, given in the Section 6.4, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Section 6.2 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the TTL-compatible CMOS input. TTL-Compatible CMOS inputs have a lower threshold voltage than standard CMOS inputs to allow for compatibility with older bipolar logic devices. See the Section 6.2 for the valid input voltages for the CD74HCT125. 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1. CAUTION Voltages beyond the values specified in the Section 6.1 table can cause damage to the device. The recommended input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. Device VCC +IIK +IOK Logic Input -IIK Output -IOK GND Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes Table 8-1. Function Table INPUTS Copyright © 2021 Texas Instruments Incorporated OUTPUT OE A Y L H H L L L H X Z Submit Document Feedback 9 CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information In this application, a 3-state buffer is used to enable or disable a data connection as shown in Figure 9-1. It is common to see all four channels of a device used together for controlling a 4-bit data bus, however each channel of the device can be used independently. Unused channels should have the inputs terminated at ground or VCC and the output left unconnected. When the output of the device is active, the data signal will be replicated at the output. When the output of the device is disabled, the output will be in a high-impedance state, and the output voltage will be determined by the circuit connected to the output pin. This circuit is most commonly used when a bus must be completely disabled. One example of this situation is when the circuitry connected to the output is to be powered off for an extended period of time to save system power, and the inputs to that circuitry cannot have a voltage present due to protective clamp diodes. 9.2 Typical Application System Controller OE Data A Y Output Figure 9-1. Typical application schematic 9.2.1 Design Requirements 9.2.1.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Section 6.2. The supply voltage sets the device's electrical characteristics as described in the Section 6.4. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the CD74HCT125 plus the maximum supply current, ICC, listed in the Section 6.4. The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the Section 6.1. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Section 6.1, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Section 6.1. These limits are provided to prevent damage to the device. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 9.2.1.2 Input Considerations Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the CD74HCT125, as specified in the Section 6.4, and the desired input transition rate. A 10-kΩ resistor value is often used due to these factors. Refer to the Section 8.3 for additional information regarding the inputs for this device. 9.2.1.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Section 6.4. Similarly, the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Section 6.4. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to Section 8.3 for additional information regarding the outputs for this device. 9.2.2 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11. 2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the CD74HCT125 to the receiving device. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation 9.2.3 Application Curves OE Data Output Figure 9-2. Typical application timing diagram Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 CD74HCT125, CD54HCT125 SCHS415 – JUNE 2020 www.ti.com 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Section 6.2. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 0.1 F Avoid 90° corners for signal lines Bypass capacitor placed close to the device 1OE 1 14 VCC 1A 2 13 4OE 1Y 3 12 4A 2OE 4 11 4Y 2A 5 10 3OE 2Y 6 9 3A GND 7 8 3Y Unused inputs tied to VCC Unused output left floating Figure 11-1. Example layout for the CD74HCT125 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 CD74HCT125, CD54HCT125 www.ti.com SCHS415 – JUNE 2020 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • HCMOS Design Considerations • CMOS Power Consumption and CPD Calculation • Designing with Logic 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 17-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD54HCT125F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT125F3A Samples CD74HCT125E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT125E Samples CD74HCT125M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M Samples CD74HCT125M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HCT125M Samples CD74HCT125M96E4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M Samples CD74HCT125MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
CD74HCT125M96G4 价格&库存

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