CD74HCT243M

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 CDx4HC243, CDx4HCT243 High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs 1 Features 2 Description • The CDx4HC243 and CDx4HCT243 are quad bus transceivers with 3-state outputs. The OEA and OEB inputs control both the high-impedance state as well as the direction of communication through the device. • • • • • • • • Typical propagation delay (A to B, B to A) of 7ns at VCC = 5 V, CL = 15pF, TA = 25oC Three-state outputs Buffered inputs Fanout (over temperature range) – Standard outputs : 10 LSTTL loads – Bus driver outputs : 15 LSTTL loads Wide operating temperature range : -55oC to 125oC Balanced propagation delay and transition times Significant power reduction compared to LSTTL logic ICs HC types – 2 V to 6 V Operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min) – CMOS input compatibility, Il ≤ 1µA at VOL, VOH Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD54HC243F CDIP (14) 19.55 mm × 6.71 mm CD74HC243E PDIP (14) 19.31 mm × 6.35 mm CD74HC243M SOIC (14) 8.65 mm × 3.90 mm CD74HCT243E PDIP (14) 19.31 mm × 6.35 mm CD74HCT243M SOIC (14) 8.65 mm × 3.90 mm (1) For all packages see the orderable addendum at the end of the datasheet. OEA OEB Ax Bx 1 of 4 Channels Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics............................................6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Documentation Support.......................................... 10 10.2 Receiving Notification of Documentation Updates..10 10.3 Support Resources................................................. 10 10.4 Trademarks............................................................. 10 10.5 Electrostatic Discharge Caution..............................10 10.6 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2003) to Revision E (March 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 4 Pin Configuration and Functions J, N, or D Package 14-Pin CDIP, PDIP, or SOIC Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 3 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 5 Specifications 5.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX -0.5 7 UNIT VCC Supply voltage IIK Input diode current For VI < -0.5V or VO > VCC + 0.5V ±20 mA IOK Output diode current For VC < -0.5V or VO > VCC + 0.5V ±20 mA IO Drian Current, per output For -0.5V < VO < VCC + 0.5V ±35 mA IO Output source or sink current per output pin For VO > -0.5V or VO < VCC + 0.5V ±25 mA Continuous current through VCC or GND ±70 mA 150 °C Junction temperature 150 °C Lead temperature (Soldering 10s)(SOIC - Lead Tips Only) 300 °C Tstg Storage temperature range TJ (1) V -65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions VCC Supply voltage range VI Input voltage VO Output voltage HC Types HCT Types MIN MAX 2 6 4.5 5.5 0 VCC V VCC V 0 VCC = 2V tt TA Input rise and fall time UNIT V 1000 VCC = 4.5V 500 VCC = 6V 400 Temperature Range -55 125 ns °C 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance(1) N (PDIP) D (SOIC) 14 PINS 14 PINS UNIT 80 86 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 5.4 Electrical Characteristics TEST (1) CONDITIONS PARAMETER VCC (V) 25°C MIN TYP -40°C to 85°C MAX MIN MAX -55°C to 125°C MIN MAX UNIT HC TYPES VIH VIL VOH High-level input voltage Low-level input voltage IOH = – 20μA High-level output voltage IOH = – 20μA CMOS loads IOH = – 20μA High-level output voltage IOH = – 6mA TTL loads IOH = – 7.8mA 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 2 1.9 1.9 1.9 4.5 4.4 4.4 4.4 6 5.9 5.9 5.9 4.5 3.98 3.84 3.7 6 5.48 5.34 V V 5.2 IOL = 20μA 2 0.1 0.1 0.1 IOL = 20μA 4.5 0.1 0.1 0.1 IOL = 20μA 6 0.1 0.1 0.1 Low-level output voltage TTL IOL = 6mA 4.5 0.26 0.33 0.4 IOL = 7.8mA 6 0.26 0.33 0.4 II Input leakage current VCC or GND 6 ±0.1 ±1 ±1 µA ICC Supply Current VCC or GND 6 8 80 160 µA IOZ Three-state leakage current VIL or VIH 6 ±0.5 ±0.5 ±10 µA Low-level output voltage CMOS loads VOL V HCT TYPES VIH High-level input voltage 4.5 to 5.5 VIL Low-level input voltage 4.5 to 5.5 2 2 0.8 2 0.8 V 0.8 V High-level output voltage IOH = – 20μA CMOS loads 4.5 4.4 4.4 4.4 High-level output voltage IOH = – 6mA TTL loads 4.5 3.98 3.84 3.7 Low-level output voltage CMOS loads IOL = 20μA 4.5 0.1 0.1 0.1 Low-level output voltage TTL loads IOL = 6mA 4.5 0.26 0.33 0.4 II Input leakage current VCC to GND 5.5 ±0.1 ±1 ±1 µA ICC Supply current VCC or GND 5.5 8 80 160 µA VOH VOL V One of An or Bn ∆ICC (2) Additional supply current (3) One of OEA or per input pin OEB IOZ (1) (2) (3) Three-state leakage current V VIL or VIH 4.5 to 5.5 100 396 495 539 4.5 to 5.5 100 216 270 294 ±0.5 ±5 ±10 5.5 µA µA VI = VIH or VIL, unless otherwise noted. For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. Inputs held at VCC – 2.1. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 5 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 5.5 Switching Characteristics Input tt = 6ns. Unless otherwise specified, CL = 50pF PARAMETER VCC (V) -40°C to 85°C 25°C TYP -55°C to 125°C MAX MAX MAX 90 115 135 18 23 27 UNIT HC TYPES 2 tpd Propagation delay data to outputs tPZL, tPZH Output high-Z, to high level to low level 4.5 7 (1) 6 15 20 23 2 150 190 225 30 38 45 26 33 38 150 190 225 30 38 45 6 26 33 38 2 60 75 90 4.5 12 15 18 6 10 13 15 4.5 12 (1) 6 2 tPHZ, tPLZ tt Output high level, output low level to high-Z Output transition times 4.5 12 (1) ns ns ns ns Ci Input capacitance 10 10 10 pF CO Three-state output capacitance 20 20 20 pF Cpd (2) (3) Power dissipation capacitance 5 80 pF HCT TYPES tpd Propagation delay data to outputs 4.5 9 (1) 22 28 33 ns tPZH, tPLZ Output high-Z to high level to low level 4.5 14 (1) 34 43 51 ns tPHZ, tPLZ Output high level, output low level to high-Z 4.5 14 (1) 35 44 53 ns tt Output transition times 4.5 12 15 18 ns Ci Input capacitance 10 10 10 pF CO Three-state output capacitance 20 20 20 pF Cpd (2) (3) Power dissipation capacitance (1) (2) (3) 6 5 91 pF Typical value tested at 5V, CL = 15pF. CPD is used to determine the dynamic power consumption, per channel. PD = VCC 2fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 6 Parameter Measurement Information tPD is the maximum between tPLH and tPHL tt is the maximum between tTLH and tTHL Figure 6-1. HC and HCT transition times and propagation delay times, combination logic Figure 6-3. HC three-state propagation delay waveform Figure 6-2. HCT transition times and tpopationg delay times, combination logic Figure 6-4. HCT three-state propagation delay waveform NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. Figure 6-5. HC and HCT three-state propagation delay test circuit Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 7 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 7 Detailed Description 7.1 Overview The CDx4HC243 and CDx4HCT243 silicon-gate CMOS three-state bidirectional noninverting buffers are intended for two-way asynchronous communication between data buses. They have high-drive-current outputs that enable high-speed operation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits and have speeds comparable to low-power Schottky TTL circuits. They can drive 15 LSTTL loads. The states of the output-enable (OEB, OEA) inputs determine both the direction of flow (A to B, B to A), and the three-state mode. 7.2 Functional Block Diagram OEA OEB Ax Bx 1 of 4 Channels Figure 7-1. Functional Diagram 7.3 Device Functional Modes (1)(2) Table 7-1. Truth Table HC, HCT243 Series Control Inputs (1) (2) 8 Submit Document Feedback Data port status OEB OEA An Bn H H O I L H Z Z H L Z Z L L I O H = High voltage level. L = Low voltage level. I = Input. O = Output (Same level as input). Z = High Impedance To prevent excess currents in the High Z modes all I/O terminals hsould be terminated with 10kΩ to 1MΩ resistors. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 9 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 www.ti.com SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 8409001CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8409001CA CD54HC243F3A Samples CD54HC243F ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HC243F Samples CD54HC243F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8409001CA CD54HC243F3A Samples CD74HC243E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E Samples CD74HC243EE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E Samples CD74HC243M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M Samples CD74HC243M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M Samples CD74HC243MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M Samples CD74HCT243E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT243E Samples CD74HCT243M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT243M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of