CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset
1 Features
2 Description
•
•
•
•
The ’HC273 and ’HCT273 high speed octal D-Type
flip-flops with a direct clear input are manufactured
with silicon-gate CMOS technology. They possess the
low power consumption of standard CMOS integrated
circuits.
•
•
•
•
•
Common clock and asynchronous controller reset
Positive edge triggering
Buffered inputs
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: –55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
Logic ICs
HC types:
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5V
HCT types:
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility, VIL = 0.8
V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 μA at VOL,VOH
Information at the D input is transferred to the Q
outputs on the positive-going edge of the clock pulse.
All eight flip-flops are controlled by a common clock
(CLK) and a common reset (CLR). Resetting is
accomplished by a low voltage level independent of
the clock. All eight Q outputs are reset to a logic 0.
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD54HC273F
CDIP (20)
26.92 mm × 6.92 mm
CD74HC273M
SOIC (20)
12.80 mm × 7.50 mm
CD74HC273E
PDIP (20)
25.40 mm × 6.35 mm
CD74HCT273M
SOIC (20)
12.80 mm × 7.50 mm
CD74HCT273
PDIP (20)
25.40 mm × 6.35 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Shared Control Logic
CLR
CLK
R
xD
D
Q
xQ
One of Eight D-Type Flip-Flops
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics.................. 6
5.6 Switching Characteristics............................................7
6 Detailed Description........................................................8
6.1 Overview..................................................................... 8
6.2 Functional Block Diagram........................................... 8
6.3 Device Functional Modes............................................8
7 Parameter Measurement Information............................ 9
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Receiving Notification of Documentation Updates..12
10.2 Support Resources................................................. 12
10.3 Trademarks............................................................. 12
10.4 Electrostatic Discharge Caution..............................12
10.5 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2003) to Revision C (January 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-refrences throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
• Updated pin names to match current TI naming conventions. MR is now CLR, Q0 is now 1Q, D0 is now 1D,
D1 is now 2D, Q1 is now 2Q, Q2 is now 3Q, D2 is now 3Q, D3 is now 4D, Q3 is now 4Q, CP is now CLK, Q4
is now 5Q, D4 is now 5D, D5 is now D6, Q5 is now 6Q, Q6 is now 7Q, D6 is now 7D, D7 is now 8D, Q7 is
now 8Q............................................................................................................................................................... 1
2
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
4 Pin Configuration and Functions
CLR
1
20
VCC
1Q
2
19
8Q
1D
3
18
8D
2D
4
17
7D
2Q
5
16
7Q
3Q
6
15
6Q
6D
3D
7
14
4Q
8
13
5D
4D
9
12
5Q
10
11
CLK
GND
J, DW or N package
20-Pin CDIP, PDIP or SOIC
Top View
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
– 0.5
7
UNIT
VCC
Supply voltage
V
IIK
Input clamp diode current
For VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IOK
Output clamp diode current
For VO < –0.5 V or VO > VCC + 0.5 V
±20
mA
IO
Drain current, per output
For –0.5 V < VO < VCC + 0.5 V
±25
mA
IO
Output source or sink current per output pin
For VO > –0.5 V or VO < VCC + 0.5 V
±25
mA
Continuous current through VCC or ground current
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature range
150
°C
300
°C
– 65
Lead temperature (Soldering 10s) (SOIC - Lead Tips Only)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 Recommended Operating Conditions
TA
Temperature range
VCC
Supply voltage range
VI, VO
DC input or output voltage
tt
Input rise and fall time
MIN
MAX
UNIT
–55
125
℃
2
6
4.5
5.5
0
VCC
HC types
HCT types
2V
V
V
1000
4.5 V
500
6V
400
ns
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance
(1)
DW (SOIC)
N (PDIP)
20 PINS
20 PINS
UNIT
58
69
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
5.4 Electrical Characteristics
PARAMETER
TEST
(2)
CONDITIONS
VCC (V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
VIH
VIL
VOH
VOL
High level input
voltage
Low level input
voltage
2
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6
4.2
4.2
V
4.2
2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6
1.8
1.8
1.8
High level output
voltage
CMOS loads
IOH = – 20 μA
2
1.9
1.9
1.9
IOH = – 20 μA
4.5
4.4
4.4
4.4
IOH = – 20 μA
6
5.9
5.9
5.9
High level output
voltage
TTL loads
IOH = – 4 mA
4.5
3.98
3.84
3.7
IOH = – 5.2 mA
6
5.48
5.34
5.2
Low level output
voltage
CMOS loads
IOL = 20 μA
2
0.1
IOL = 20 μA
4.5
0.1
IOL = 20 μA
6
0.1
0.1
0.1
Low level output
voltage
TTL loads
IOL = 4 mA
4.5
0.26
0.33
0.4
IOL = 5.2 mA
6
0.26
0.33
0.4
0.1
-
0.1
V
V
V
0.1
-
0.1
V
V
II
Input leakage
current
VI = VCC or GND
6
±0.1
±1
±1
mA
ICC
Quiescent device
current
VI = VCC or GND
6
8
80
160
mA
HCT TYPES
VIH
High level input
voltage
4.5 to
5.5
VIL
Low level input
voltage
4.5 to
5.5
VOH
VOL
2
2
0.8
2
0.8
V
0.8
High level output
voltage
CMOS loads
IOH = – 20 μA
High level output
voltage
TTL loads
IOH = – 4 mA
4.5
Low level output
voltage
CMOS loads
IOL = 20 μA
4.5
Low level output
voltage
TTL loads
IOL = 4 mA
4.5
0.26
0.33
0.4
4.5
4.4
4.4
V
4.4
V
3.98
3.84
0.1
3.7
0.1
0.1
V
II
Input leakage
current
VI = VCC or GND
5.5
±0.1
±1
±1
μA
ICC
Quiescent device
current
VI = VCC or GND
5.5
8
80
160
μA
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
5.4 Electrical Characteristics (continued)
PARAMETER
ΔICC (1)
(1)
(2)
Additional quiescent
device current per
input pin
TEST
(2)
CONDITIONS
VCC (V)
CLR input held at
VCC –2.1
25℃
MIN
–40℃ to 85℃
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
TYP
MAX
4.5 to
5.5
100
540
675
735
μA
Data inputs held at
VCC –2.1
4.5 to
5.5
100
144
180
196
μA
CLK inputs held at
VCC –2.1
4.5 to
5.5
100
540
675
735
μA
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8mA.
VI = VIH or VIL, unless otherwise noted.
5.5 Prerequisite for Switching Characteristics
See Parameter Measurement Information
PARAMETER
VCC (V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
fMAX
tW
tW
tSU
tH
tREM
Maximum clock frequency
CLR pulse width
Clock pulse width
Set-up time data to clock
Hold time, data to clock
Removal time, CLR to clock
2
6
5
4
4.5
30
25
20
6
35
29
23
2
60
75
90
4.5
12
15
18
6
10
13
15
2
80
100
120
4.5
16
20
24
6
14
17
20
2
60
75
70
4.5
12
15
18
6
10
13
15
2
3
3
3
4.5
3
3
3
6
3
3
3
2
50
65
75
4.5
10
13
15
6
9
11
13
MHz
ns
ns
ns
ns
ns
HCT TYPES
6
fMAX
Maximum clock frequency
4.5
25
20
16
MHz
tw
CLR pulse width
4.5
12
15
18
ns
tw
Clock pulse width
4.5
20
25
30
ns
tSU
Set-up time data to clock
4.5
12
15
18
ns
tH
Hold time, data to clock
4.5
3
3
3
ns
tREM
Removal time, CLR to clock
4.5
10
13
15
ns
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
5.6 Switching Characteristics
Input tr, tf = 6 ns (See Parameter Measurement Information)
PARAMETER
TEST
CONDITIONS
VCC(V)
CL = 50 pF
6
25℃
TYP
–40℃ to 85℃ –55℃ to 125℃
MAX
MAX
MAX
2
150
190
225
4.5
30
38
45
26
30
38
UNIT
HC TYPES
tPLH, tPHL
Propagation delay
Clock to output
Propagation delay
CLR to output
tPHL
tTLH, tTHL
Output transition time
CIN
Input capacitance
fMAX
Maximum clock frequency
CPD
Power dissipation capacitance(1) (2)
CL = 15 pF
5
2
150
190
225
CL = 50 pF
4.5
30
38
45
6
26
30
38
2
75
95
110
4.5
15
19
22
6
13
16
19
10
10
10
CL = 50 pF
CL = 15 pF
ns
12
ns
ns
pF
5
60
MHz
5
25
pF
HCT TYPES
CL = 50 pF
4.5
CL = 15 pF
5
Propagation delay,
CLR to output
CL = 50 pF
tTLH, tTHL
Output transition time
CL = 50 pF
CIN
Input capacitance
fMAX
Maximum clock frequency
CPD
Power dissipation capacitance(1) (2)
tPLH, tPHL
Propagation delay,
Clock to output
tPHL
(1)
(2)
CL = 15 pF
30
38
45
4.5
32
40
48
4.5
15
19
22
ns
10
10
10
pF
12
ns
ns
5
50
MHz
5
25
pF
CPD is used to determine the dynamic power consumption, per flip-flop.
PD = CPD VCC 2 fi + Σ (CL VCC 2 + fO) where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply
voltage.
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
6 Detailed Description
6.1 Overview
The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with
silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits.
Information at the D input is transferred to the Q outputs on the positive-going edge of the clock pulse. All eight
flip-flops are controlled by a common clock (CLK) and a common reset (CLR). Resetting is accomplished by a
low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.
6.2 Functional Block Diagram
Shared Control Logic
CLR
CLK
R
xD
D
Q
xQ
One of Eight D-Type Flip-Flops
6.3 Device Functional Modes
Table 6-1. Truth Table(1)
INPUTS
RESET (CLR)
CLOCK CLK
DATA Dn
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
(1)
8
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OUTPUT
H = high voltage level, L = low voltage level, X = don’t care, ↑ =
transition from low to high level, Q0 = level before the indicated
steady-state input conditions were established
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
tw
VCC
Clock
Input
VCC
Input
50%
50%
50%
0V
0V
Figure 7-2. Voltage Waveforms, Standard CMOS
Inputs Pulse Duration
th
tsu
VCC
Data
Input
50%
50%
0V
Figure 7-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC
Input
50%
90%
Input
50%
tPLH
tPHL
tr(1)
(1)
VOH
Output
50%
VOL
tPHL
tPLH
(1)
VOH
Output
50%
0V
tf(1)
90%
VOH
90%
Output
50%
(1)
10%
10%
0V
(1)
VCC
90%
50%
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-5. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
tw
3V
Clock
Input
3V
Input
1.3V
1.3V
1.3V
0V
0V
tsu
Figure 7-6. Voltage Waveforms, TTL-Compatible
CMOS Inputs Pulse Duration
th
3V
Data
Input
1.3V
1.3V
0V
Figure 7-7. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input
1.3V
1.3V
0V
tPLH(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-8. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
10
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SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8772501RA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8772501RA
CD54HCT273F3A
Samples
CD54HC273F
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC273F
Samples
CD54HC273F3A
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8409901RA
CD54HC273F3A
Samples
CD54HCT273F
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HCT273F
Samples
CD54HCT273F3A
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8772501RA
CD54HCT273F3A
Samples
CD74HC273E
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC273E
Samples
CD74HC273M
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC273M
Samples
CD74HC273M96
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC273M
Samples
CD74HC273M96E4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC273M
Samples
CD74HCT273E
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT273E
Samples
CD74HCT273EE4
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT273E
Samples
CD74HCT273M
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT273M
Samples
CD74HCT273M96
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT273M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of