CD74HCT356M96

CD74HCT356 Semiconductor High-Speed CMOS Logic 8-Input Multiplexer/Register, Three-State SCLS459A - June 2001 - Revised May 2003 Features Description • Edge-Triggered Data Flip-Flops - Transparent Select Latches • Buffered Inputs • 3-State Complementary Outputs • Bus Line Driving Capability • Typical Propagation Delay: VCC = 5V, CL = 15pF, TA = 25oC - Clock to Output = 22ns • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • 4.5V to 5.5V Operation • Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The CD74HCT356 consists of data selectors/multiplexers that select one of eight sources. The data select bits (S0, S1, and S2) are stored in transparent latches that are enabled by a low latch enable input (LE). The data is stored in edge-triggered flip-flops that are triggered by a low-to-high clock transition. In both types the 3-state outputs are controlled by three output-enable inputs (OE1, OE2, and OE3). Ordering Information PART NUMBER TEMP. RANGE (oC) CD74HCT356E -55 to 125 20 Ld PDIP CD74HCT356M96 -55 to 125 20 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. Pinout CD74HCT356 (PDIP or SOIC) TOP VIEW D7 1 20 VCC D6 2 19 Y D5 3 18 Y D4 4 17 OE3 D3 5 16 OE2 D2 6 15 OE1 D1 7 14 S0 D0 8 13 S1 CP 9 12 S2 GND 10 11 LE CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE 1 CD74HCT356 Functional Diagram S0 14 S1 13 S2 12 D0 D1 D2 D3 D4 D5 D6 D7 8 19 7 Y 6 5 4 3 18 2 Y 1 11 LE 15 OE1 16 OE2 17 OE3 9 CP TRUTH TABLE INPUTS SELECT (NOTE 1) CLOCK OUTPUT ENABLES OUTPUTS S2 S1 S0 CP OE1 OE2 OE3 Y Y X X X X H X X Z Z X X X X X H X Z Z X X X X X X L Z Z L L L ↑ L L H D0 D0 L L L H or L L L H D0n D0n L L H ↑ L L H D1 D1 L L H H or L L L H D1n D1n L H L ↑ L L H D2 D2 L H L H or L L L H D2n D2n L H H ↑ L L H D3 D3 L H H H or L L L H D3n D3n H L L ↑ L L H D4 D4 H L L H or L L L H D4n D4n H L H ↑ L L H D5 D5 H L H H or L L L H D5n D5n H H L ↑ L L H D6 D6 H H L H or L L L H D6n D6n 2 CD74HCT356 TRUTH TABLE (Continued) INPUTS SELECT (NOTE 1) CLOCK OUTPUT ENABLES OUTPUTS S2 S1 S0 CP OE1 OE2 OE3 Y Y H H H ↑ L L H D7 D7 H H H H or L L L H D7n D7n H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State); ↑ = Transition from Low to High Level; X = Don’t Care; Z = High-Impedance State (Off State); D0n...D7n = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of data control. NOTE: 1. This column shows the input address setup with LE low. Block Diagram 15 OE1 ENABLE LOGIC 16 OE2 17 OE3 9 CP 8 D0 7 D1 D A T A 6 D2 5 D3 4 D4 3 D5 2 1 O F S E L E C T O R D6 1 D7 11 LE 14 S0 13 S1 12 S2 A D D R E S S 19 8 R E G I S T E R S R E G I S T E R ADDRESS DECODE 3 Y 18 Y BUFFERS CD74HCT356 Logic Diagram 15 OE1 16 OE2 OE3 1 OF 8 F/Fs 8 (7,6,5,4, 3,2,1) D0 CP CP CP P N P N CP CP P N P 18 Y N GND CP P N CP VCC 17 P N CP CP CP VCC P 19 Y N 9 TO 7 OTHER F/Fs CP SEL0 FROM 7 OTHER F/Fs GND TO 7 OTHER F/Fs SEL0 SEL1 20 VCC 10 GND LE P N LE 14 S0 13 S1 12 S2 P N LE LE LE LE P N SL0 SL0 P N LE LE LE LE P N SL1 SL1 LE P N SL2 SL2 LE 11 LE LE LE FIGURE 1. LOGIC DIAGRAM 4 SEL2 SEL3 SEL4 SEL5 SEL6 SEL7 CD74HCT356 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 2) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -55oC TO 125oC SYMBOL VI (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load 3-State Leakage Current IO (mA) VCC (V) -40oC TO 85oC II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 3) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA IOZ VIL or VIH VO = VCC or GND 5.5 - - ±0.5 - ±5 - ±10 µA NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. 5 CD74HCT356 Input Loading Table INPUT UNIT LOADS D0-D7 0.50 S0, S1, S3 0.70 OE1, OE2 0.80 OE3 0.25 LE 0.25 CP 0.60 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CP Pulse Width tPLH, tPHL - 4.5 16 20 - 25 - 30 - ns LE Pulse Width PARAMETER tPLH, tPHL - 4.5 16 20 - 25 - 30 - ns Setup Times Dn → E tSU - 4.5 5 7 - 9 - 11 - ns Setup Times Sn → LE tSU - 4.5 5 7 - 9 - 11 - ns Hold Times Dn → E tH - 4.5 9 9 - 11 - 14 - ns Hold Times Sn → LE tH - 4.5 12 12 - 15 - 18 - ns 6 CD74HCT356 Switching Specifications Input tr, tf = 6ns SYMBOL TEST CONDITIONS Propagation Delay, CP→ Y, Y tPLH, tPHL Propagation Delay, Sn → Y, Y tPLH, tPHL Propagation Delay, LE → Y, Y tPLH, tPHL Output Disabling Time PARAMETER Output Enabling Time Output Transition Time 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS CL = 50pF 4.5 - 51 64 77 ns CL = 15pF 5 22 - - - ns CL = 50pF 4.5 - 59 74 89 ns CL = 15pF 5 25 - - - ns CL = 50pF 4.5 - 63 79 94 ns CL = 15pF 5 25 - - - ns tPLZ, tPHZ CL = 50pF 4.5 - 33 41 50 ns tPLZ CL = 15pF 5 13 - - - ns tPHZ CL = 15pF 5 15 - - - ns tPLZ, tPHZ CL = 50pF 4.5 - 34 43 51 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 12 15 18 ns tTLH, tTHL Input Capacitance CIN - - - 10 10 10 pF 3-State Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 4, 5) CPD - 5 52 - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per device. 5. PD = VCC2 (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tWL + tWH = trCL = 6ns tfCL = 6ns I fCL 2.7V 0.3V 1.3V 0.3V tWL 1.3V 3V 2.7V 1.3V 0.3V INPUT 3V CLOCK tf = 6ns tr = 6ns 1.3V GND GND tTHL tWH tTLH 90% 1.3V 10% INVERTING OUTPUT NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL FIGURE 2. CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tPLH FIGURE 3. TRANSITION TIMES AND PROPAGATION-DELAY TIMES, COMBINATION LOGIC 7 CD74HCT356 Test Circuits and Waveforms trCL (Continued) tfCL tr 3V 2.7V CLOCK INPUT 1.3V 0.3V tSU(H) tTLH 90% OUTPUTS ENABLED 90% 90% 1.3V 1.3V 10% tPLH tREM 3V SET, RESET OR PRESET OUTPUT HIGH TO OFF tTHL 0.3 GND 1.3V 10% tPHZ GND tSU(L) 3V tPZL tPLZ OUTPUT LOW TO OFF 1.3V 1.3V 6ns 2.7 1.3 tH(L) 3V 1.3V OUTPUT tf GND tH(H) DATA INPUT 6ns OUTPUT DISABLE tPZH 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 5. 3-STATE PROPAGATION-DELAY WAVEFORM tPHL 1.3V GND IC CL 50pF FIGURE 4. SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION-DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH 3-STATE OUTPUT OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open-drain waveforms tPLZ and tPZL are the same as those for 3-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 6. 3-STATE PROPAGATION-DELAY TEST CIRCUIT 8 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) CD74HCT356E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT356E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of