CD74HCT4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
SCHS281A – REVISED MAY 2003
D
D
D
D
D
D
D
D
D
E PACKAGE
(TOP VIEW)
4.5-V to 5.5-V VCC Operation
Input Latches for BCD Code Storage
Blanking Capability
Phase Input for Complementing Outputs
Fanout (Over Temperature Range)
– Standard Outputs – 10 LSTTL Loads
Balanced Propagation Delay and Transition
Times
Significant Power Reduction, Compared to
LSTTL Logic ICs
Direct LSTTL Input Logic Compatibility,
VIL = 0.8 V Maximum, VIH = 2 V Minimum
CMOS Input Compatibility, II ≤ 1 µA at VOL,
VOH
LD
D2
D1
BCD
Inputs
D3
D0
PH
BI
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
f
g
e
7-Segment
d
Outputs
c
b
a
DISPLAY
0
1
2
3
4
5
6
7
8
9
a
f
g
e
b
c
d
description/ordering information
The CD74HCT4543 high-speed silicon-gate is a BCD-to-7 segment latch/decoder/driver designed primarily for
directly driving liquid-crystal displays. While the latch enable (LD) is low, the latches are enabled to store the
BCD inputs. When the latch enable is high, the latches are disabled, making the outputs transparent to the BCD
inputs. The device has an active-high blanking input (BI) and a phase input (PH) to which a square wave is
applied for liquid-crystal applications. This square wave also is applied to the backplane of the liquid-crystal
display.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–55°C to 125°C
PDIP – E
Tube
CD74HCT4543E
CD74HCT4543E
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD74HCT4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
SCHS281A – REVISED MAY 2003
FUNCTION TABLE
LD
BI
PH
D3
D2
D1
D0
a
b
c
d
e
f
g
Display
X
H
L
X
X
X
X
L
L
L
L
L
L
L
Blank
H
L
L
L
L
L
L
H
H
H
H
H
H
L
0
H
L
L
L
L
L
H
L
H
H
L
L
L
L
1
H
L
L
L
L
H
L
H
H
L
H
H
L
H
2
H
L
L
L
L
H
H
H
H
H
H
L
L
H
3
H
L
L
L
H
L
L
L
H
H
L
L
H
H
4
H
L
L
L
H
L
H
H
L
H
H
L
H
H
5
H
L
L
L
H
H
L
H
L
H
H
H
H
H
6
H
L
L
L
H
H
H
H
H
H
L
L
L
L
7
H
L
L
H
L
L
L
H
H
H
H
H
H
H
8
H
L
L
H
L
L
H
H
H
L
H
L
H
H
9
H
L
L
H
L
H
L
L
L
L
L
L
L
L
Blank
H
L
L
H
L
H
H
L
L
L
L
L
L
L
Blank
H
L
L
H
H
L
L
L
L
L
L
L
L
L
Blank
H
L
L
H
H
L
H
L
L
L
L
L
L
L
Blank
H
L
L
H
H
H
L
L
L
L
L
L
L
L
Blank
H
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
X
X
X
X
L
†
Blank
†
As above H
As above
Inverse of above
† Depends on BCD code previously applied when LD = high.
As above
functional diagram
PH
6
BCD
Inputs
D2 2
9
10
11
12
13
a
b
c
d
e
15
f
14 g
D3 4
LD
Driver
D1 3
Decoder
5
Latch
D0
1
7
BI
GND = 8
VCC = 16
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7-Segment
Outputs
CD74HCT4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
SCHS281A – REVISED MAY 2003
logic diagram
7
BI
9
a
5
D0
D0 Q0
10
Latch
LD
LD
LD
LD
Q0
11
3
D
D1
b
c
Q1
Latch
LD
LD
LD
LD
12
Q1
LD
Dn
2
D2 Q2
D2
LD
4
LD
LD
Qn
LD Q
LD n
Latch
LD
d
≡
Dn
Qn
P
n
Qn
LD
LD
P
n
Q2
13
e
LD
D3 Q3
D3
Latch
15
Q3
LD
LD
LD
LD
f
1
LD
LD
14
LD
g
6
PH
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3
CD74HCT4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
SCHS281A – REVISED MAY 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input diode current, IIK (VI < –0.5 V or VI > VCC + 0.5 V) ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output diode current, IOK (VO < –0.5 V or VO > VCC + 0.5V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s maximum . . . . . . . . . . . . . . . . . . . . . 265°C
Unit inserted into a PC board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
VO
tt
Output voltage
High-level input voltage
TA = 25°C
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MAX
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
4.5
5.5
2
Input voltage
Input transition (rise and fall) time
2
2
UNIT
V
V
0.8
0.8
0.8
V
VCC
VCC
VCC
VCC
VCC
VCC
V
500
500
500
ns
V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
VOH
VI = VIH or VIL
IOH = –20 µA
IOH = –4 mA
45V
4.5
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 4 mA
45V
4.5
II
ICC
VI = VCC to GND
VI = VCC or 0,
∆ICC‡
IO = 0
One input at VCC – 2.1 V,
Other inputs at 0 or VCC
TYP
MAX
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MIN
MAX
4.4
4.4
4.4
3.98
3.7
3.84
UNIT
MAX
V
0.1
0.1
0.1
0.26
0.4
0.33
5.5 V
±0.1
±1
±1
µA
5.5 V
8
160
80
µA
360
490
450
µA
4.5 V to 5.5 V
100
V
Ci
10
10
10
pF
‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case
(VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
4
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CD74HCT4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
SCHS281A – REVISED MAY 2003
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS†
D0, D1, D2
1
D3, BI
0.5
PH
1.25
LD
1.5
† Unit Load is ∆ICC limit specified in electrical
characteristics table, e.g., 360 µA maximum
at 25°C.
timing requirements over recommended operating free-air temperature range VCC = 4.5 V (unless
otherwise noted) (see Figure 1)
TA = 25°C
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tw
tsu
Pulse duration, LD high
10
15
13
ns
Setup time, BCD inputs before LD↓
12
18
15
ns
th
Hold time, BCD inputs before LD↓
8
12
10
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Dn
Output
LD
Output
BI
Output
tpd
d
PH
tt
Output
Any
LOAD
CAPACITANCE
VCC
CL = 50 pF
4.5 V
TA = 25°C
MIN
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
TYP
MAX
TA = –55°C
TO 125°C
TA = –40°C
TO 85°C
MIN
MIN
MAX
UNIT
MAX
80
120
100
77
116
96
66
99
83
66
99
83
50
75
63
33
32
ns
27
27
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd‡
TYP
Power dissipation capacitance
54
UNIT
pF
‡ Cpd is used to determine the dynamic power consumption, per package.
PD = Cpd VCC2 fi + ∑ CL VCC2 fo
where: fi = input frequency
fo = output frequency
CL = output load capacitance
VCC = supply voltage
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5
CD74HCT4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
SCHS281A – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point
From Output
Under Test
PARAMETER
S1
ten
RL = 1 kΩ
tdis
CL
(see Note A)
S2
S1
S2
tPZH
Open
Closed
tPZL
Closed
Open
tPHZ
Open
Closed
tPLZ
Closed
Open
Open
Open
tpd or tt
tw
LOAD CIRCUIT
VCC
Input
50% VCC
50% VCC
0V
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
VCC
Reference
Input
VCC
50% VCC
50% VCC
0V
0V
tsu
trec
Data
50%
Input 10%
VCC
50% VCC
CLK
90%
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC
50% VCC
tPLH
tPHL
50%
10%
90%
90%
tr
tPHL
Out-of-Phase
Output
90%
tf
tf
VCC
VOH
50% VCC
10%
VOL
tf
50%
10%
90%
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
Output
Waveform 1
(see Note B)
50% VCC
Output
Waveform 2
(see Note B)
10%
VOL
tPHZ
tPZH
VOH
VOL
VCC
Output
Control
tPLH
50% VCC
10%
VCC
50% VCC
10% 0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
0V
In-Phase
Output
90%
tr
0V
Input
th
50% VCC
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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• DALLAS, TEXAS 75265
CD74HCT4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
SCHS281A – REVISED MAY 2003
APPLICATION CIRCUITS
Appropriate
Voltage
HCT4543
Output
PH
One of Seven
Segments
Common
Backplane
HCT4543
ÉÉÉÉÉ
ÉÉÉÉÉ
Output
PH
GND
Square Wave:
GND to VCC
Figure 2. Connection to Liquid-Crystal
Display (LCD)
Figure 3. Connection to Incandescent
Display
Appropriate
Voltage
HCT4543
HCT4543
Output
Output
PH
GND
To Filament
Supply
PH
GND
GND or Appropriate
Voltage Below GND
Figure 4. Connection to Gas-Discharge
Display
POST OFFICE BOX 655303
Figure 5. Connection to Fluorescent Display
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
CD74HCT4543E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4543E
CD74HCT4543EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4543E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of