CDC340DW

CDC340 1-LINE TO 8-LINE CLOCK DRIVER SCAS332B – DECEMBER 1992 – REVISED MAY 1997 D D D D D D D DW PACKAGE (TOP VIEW) Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight Outputs Distributed VCC and Ground Pins Reduce Switching Noise High-Drive Outputs (– 48-mA IOH, 48-mA IOL) State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (DW) and Shrink VCC 1G 2G A P0 P1 VCC 2Y4 2Y3 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Y1 1Y2 GND 1Y3 1Y4 GND 2Y1 2Y2 GND description The CDC340 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a high state regardless of the A input. The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC340 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS 1G 2G X L L OUTPUTS A 1Y1 – 1Y4 2Y1 – 2Y4 X L H H L H H H H H H L H L H L H H H H L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC340 1-LINE TO 8-LINE CLOCK DRIVER SCAS332B – DECEMBER 1992 – REVISED MAY 1997 logic symbol† 1G 2G 2 3 G1 G2 1 1 A 4 1 1 2 2 2 2 19 18 16 15 13 12 9 8 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1G 2G 2 19 3 18 16 15 A 1Y2 1Y3 1Y4 4 13 12 9 8 2 1Y1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Y1 2Y2 2Y3 2Y4 CDC340 1-LINE TO 8-LINE CLOCK DRIVER SCAS332B – DECEMBER 1992 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.6 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations Application Note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 3) MIN MAX UNIT 4.75 5.25 V VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC – 48 mA Low-level output current 48 mA fclock l k Input clock frequency High-level input voltage 2 V 0.8 Input voltage 0 One output back loaded 80 Both output banks loaded 40 TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. 0 70 V V MHz °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.75 V, VCC = 4.75 V, II = –18 mA IOH = – 3 mA VOH VCC = 5 V, VCC = 4.75 V, IOH = – 3 mA IOH = – 48 mA VOL II IO§ VCC = 4.75 V, VCC = 5.25 V, IOL = 48 mA VI = VCC or GND VCC = 5.25 V, VO = 2.5 V VCC = 5.25 V,, VI = VCC or GND IO = 0,, ICC MIN TA = 25°C TYP‡ MAX –1.2 2.5 2.5 3 3 2 2 MAX UNIT –1.2 V V 0.5 ±1 – 50 – 100 – 200 – 50 ±1 µA mA 2 3.5 Outputs low 24 33 • DALLAS, TEXAS 75265 V – 200 Outputs high Ci VI = 2.5 V or 0.5 V 3 ‡ All typical values are at VCC = 5 V. § No more than one output should be tested at a time, and the duration of the test should not exceed one second. POST OFFICE BOX 655303 MIN mA pF 3 CDC340 1-LINE TO 8-LINE CLOCK DRIVER SCAS332B – DECEMBER 1992 – REVISED MAY 1997 switching characteristics, CL = 50 pF (see Figure 1 and Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) A Y G Y A Y VCC = 5 V, TA = 25°C MIN TYP MAX VCC = 4.75 V to 5.25 V, TA = 0°C to 70°C MIN MAX tPLH tPHL Propagation delay time, low-to-high level tPLH tPHL Propagation delay time, low-to-high level tsk(o) tsk(p) Skew time, output tsk(pr) tr Skew time, process Rise time A Y 1.5 ns tf Fall time A Y 1.5 ns Propagation delay time, high-to-low level Propagation delay time, high-to-low level Skew time, pulse 3.4 4.5 3 4.8 3.2 4.3 2.8 4.7 2 3.8 2 4 2 3.8 2 4 UNIT 0.3 0.5 0.6 0.6 0.8 0.9 1.1 1.1 ns ns ns tpd performance information relative to VCC and temperature variation (see Note 4) ∆ change PARAMETER ∆tPLH(TA)† ∆tPHL(TA)† Temperature drift of tPLH from 0°C to 70°C Temperature drift of tPHL from 0°C to 70°C – 58 ps / 10°C ∆tPLH(VCC)‡ ∆tPHL(VCC)‡ VCC drift of tPLH from 4.75 V to 5.25 V VCC drift of tPHL from 4.75 V to 5.25 V 43 ps / 100 mV – 53 ps / 10°C – 33 ps / 100 mV † Virtually independent of VCC ‡ Virtually independent of temperature NOTE 4: The data extracted is from a wide range of characterization material. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC340 1-LINE TO 8-LINE CLOCK DRIVER SCAS332B – DECEMBER 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH Output 1.5 V 0.8 V 2V tr 1.5 V 0.8 V VOH VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms A 1G 2G 1Yn tPLH1 tPHL1 tPLH2 tPHL2 2Yn NOTES: A. Output skew, tsk(o), is calculated as the greater of: – The difference between the fastest and slowest of tPLHn (n = 1, 2) – The difference between the fastest and slowest of tPHLn (n = 1, 2) B. Pulse skew, tsk(p), is calculated as the greater of | tPLHn – tPHLn | (n = 1, 2). C. Process skew, tsk(pr), is calculated as the greater of: – The difference between the fastest and slowest of tPLHn (n = 1, 2) across multiple devices under identical operating conditions – The difference between the fastest and slowest of tPHLn (n = 1, 2) across multiple devices under identical operating conditions Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDC340DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CDC340 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of