CDC3RL02
SCHS371G – NOVEMBER 2009 – REVISED NOVEMBER 2022
CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer
1 Features
3 Description
•
The CDC3RL02 is a two-channel clock fan-out buffer
and is ideal for use in portable end-equipment, such
as mobile phones, that require clock buffering with
minimal additive phase noise and fan-out capabilities.
It buffers a single master clock, such as a temperature
compensated crystal oscillator (TCXO) to multiple
peripherals. The device has two clock request inputs
(CLK_REQ1 and CLK_REQ2), each of which enable
a single clock output.
•
•
•
•
•
Low Additive Noise:
– –149 dBc/Hz at 10-kHz Offset Phase Noise
– 0.37 ps (RMS) Output Jitter
Limited Output Slew Rate for EMI Reduction
(1- to 5-ns Rise/Fall Time for 10-pF to 50-pF
Loads)
Adaptive Output Stage Controls Reflection
Regulated 1.8-V Externally Available I/O Supply
Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP
(0.8 mm × 1.6 mm)
ESD Performance Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model
(JESD22-C101-A Level III)
2 Applications
•
•
•
•
•
•
Cellular Phones
Global Positioning Systems (GPS)
Wireless LAN
FM Radio
WiMAX
W-BT
VBATT
GND
MCLK_IN
VLDO
LDO
VCC
VCC
CLK_OUT1
EN
CLK_REQ1
CLK_OUT2
EN
CLK_REQ2
Switch/
Decoder
Copyright © 2017, Texas Instruments Incorporated
Simplified Block Diagram
The CDC3RL02 accepts square or sine waves at
the master clock input (MCLK_IN), eliminating the
need for an AC coupling capacitor. The smallest
acceptable sine wave is a 0.3-V signal (peak-topeak). CDC3RL02 has been designed to offer
minimal channel-to-channel skew, additive output
jitter, and additive phase noise. The adaptive clock
output buffers offer controlled slew-rate over a
wide capacitive loading range which minimizes EMI
emissions, maintains signal integrity, and minimizes
ringing caused by signal reflections on the clock
distribution lines.
The CDC3RL02 has an integrated Low-Drop-Out
(LDO) voltage regulator which accepts input voltages
from 2.3 V to 5.5 V and outputs 1.8 V, 50 mA.
This 1.8-V supply is externally available to provide
regulated power to peripheral devices such as a
TCXO.
The CDC3RL02 is offered in a 0.4-mm pitch waferlevel chip-scale (WCSP) package (0.8 mm × 1.6
mm) and is optimized for very low standby current
consumption.
Device Information
PART NUMBER
CDC3RL02
(1)
(1)
PACKAGE
DSBGA (8)
BODY SIZE (NOM)
0.80 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDC3RL02
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SCHS371G – NOVEMBER 2009 – REVISED NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 7
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 12
9.3 Power Supply Recommendations.............................13
9.4 Layout....................................................................... 13
10 Device and Documentation Support..........................14
10.1 Receiving Notification of Documentation Updates..14
10.2 Support Resources................................................. 14
10.3 Trademarks............................................................. 14
10.4 Electrostatic Discharge Caution..............................14
10.5 Glossary..................................................................14
11 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August 2019) to Revision G (November 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed MCLK_IN frequency maximum value from: 54 MHz to: 80 MHz.........................................................5
• Changed the x-axis range in Figure 7-3 ............................................................................................................ 7
• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation
section.............................................................................................................................................................. 13
Changes from Revision E (August 2018) to Revision F (August 2019)
Page
• Changed MCLK_IN frequency maximum value from: 52 MHz to: 54 MHz.........................................................5
Changes from Revision D (April 2017) to Revision E (August 2018)
Page
• Changed VLDO test conditions to VIH conditions in the Electrical Characteristics table ..................................... 5
• Added a tablenote to the Function Table ......................................................................................................... 10
• Added content to the LDO section ................................................................................................................... 11
• Changed the last sentence in the Detailed Design Procedure section ............................................................12
Changes from Revision C (January 2016) to Revision D (April 2017)
Page
• Updated clock request descriptions in the Pin Functions table.......................................................................... 3
• Added Receiving Notification of Documentation Updates section....................................................................14
Changes from Revision B (December 2015) to Revision C (January 2016)
Page
• Added the Device Comparison .......................................................................................................................... 3
Changes from Revision A (September 2015) to Revision B (November 2015)
Page
• Added Thermal Information table, Overview, Feature Description section, Power Supply Recommendations
section, and Layout section................................................................................................................................ 1
Changes from Revision * (November 2009) to Revision A (September 2015)
Page
• Formatted document to new standards.............................................................................................................. 1
2
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5 Device Comparison
Table 5-1. Device Comparison
(1)
(2)
TA
PACKAGE (1)
ORDERABLE PART NUMBER
BACKSIDE
COATING (2)
-40 C to 85 C
YFP
CDC3RL02BYFPR
Yes
-40 C to 85 C
YFP
CDC3RL02YFPR
No
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
CSP (DSBGA) devices manufactured with backside coating have an increased resistance to cracking due to the increased physical
strength of the package. Devices with backside coating are highly encouraged for new designs.
6 Pin Configuration and Functions
1
2
A
A1
A2
B
B1
B2
C
C1
C2
D
D1
D2
Figure 6-1. YFP Package 8-Pin DSBGA Top View
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VBATT
A1
I
Input to internal LDO
CLK_OUT1
A2
O
Clock output 1
VLDO
B1
O
1.8 V I/O supply for CDC3RL02 and external TCXO
CLK_REQ1
B2
I
Clock request 1 (from peripheral) for Clock output 1
MCLK_IN
C1
I
Master clock input
CLK_REQ2
C2
I
Clock request 2 (from peripheral) for Clock output 2
GND
D1
–
Ground
CLK_OUT2
D2
O
Clock output 2
Table 6-2. YFP Package Pin Assignments
1
2
A
VBATT
CLK_OUT1
B
VLDO
CLK_REQ1
C
MCLK_LIN
CLK_REQ2
D
GND
CLK_OUT2
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted. (1)
MIN
MAX
UNIT
–0.3
7
V
CLK_REQ_1/2, MCLK_IN
–0.3
VBATT + 0.3
VLDO, CLK_OUT_1/2(2)
–0.3
VBATT + 0.3
Voltage range(2)
VBATT
Voltage range(3)
V
IIK
Input clamp current at VBATT,
CLK_REQ_1/2, and MCLK_IN
VI < 0
–50
mA
IO
Continuous output current
CLK_OUT1/2
±20
mA
Continuous current through GND, VBATT, VLDO
±50
mA
150
°C
–40
85
°C
–55
150
°C
TJ
Operating virtual junction temperature
–40
TA
Operating ambient temperature range
Tstg
Storage temperature range
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
All voltage values are with respect to network ground pin.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
Machine Model
(1)
(2)
UNIT
V
200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
See (1)
MAX
2.3
5.5
V
MCLK_IN, CLK_REQ1/2
0
1.89
V
CLK_OUT1/2
0
1.8
V
High-level input voltage
CLK_REQ1/2
1.3
1.89
V
Low-level input voltage
CLK_REQ1/2
0
0.5
V
Input voltage to internal LDO
VI
Input voltage
VO
Output voltage
VIH
VIL
IOH
High-level output current, DC current
IOL
Low-level output current, DC current
(1)
4
MIN
VBATT
–8
UNIT
mA
8
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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7.4 Thermal Information
CDC3RL02
THERMAL
METRIC(1)
YFP (TSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
107.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.3
°C/W
RθJB
Junction-to-board thermal resistance
18.1
°C/W
ψJT
Junction-to-top characterization parameter
4.5
°C/W
ψJB
Junction-to-board characterization parameter
18.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.71
1.8
1.89
V
LDO
VOUT
LDO output voltage
CLDO
External load capacitance
IOUT(SC)
Short circuit output current
RL = 0 Ω
IOUT(PK)
Peak output current
VBATT = 2.3 V, VLDO = VOUT – 5%
PSR
tsu
Power supply rejection
LDO startup time
IOUT = 50 mA
1
VBATT = 2.3 V, IOUT = 2 mA,
10
100
100
fIN= 217 Hz and 1 kHz
60
fIN= 3.25 MHz
40
VBATT = 2.3 V , CLDO = 1 μF,
CLK_REQ_n to VIH = 1.71 V
μF
mA
mA
dB
0.2
ms
VBATT = 5.5 V , CLDO = 10 μF,
CLK_REQ_n to VIH = 1.71 V
1
POWER CONSUMPTION
ISB
Standby current
Device in standby (all VCLK_REQ_n = 0 V)
0.2
1
μA
ICCS
Static current consumption
Device active but not switching
0.4
1
mA
IOB
Output buffer average current
fIN = 26 MHz, CLOAD = 50 pF
4.2
CPD
Output power dissipation
capacitance
fIN = 26 MHz
mA
44
pF
1
μA
MCLK_IN INPUT
II
MCLK_IN, CLK_REQ_1/2 leakage
current
VI = VIH or GND
CI
MCLK_IN capacitance
fIN = 26 MHz
RI
MCLK_IN impedance
fIN = 26 MHz
fIN
MCLK_IN frequency range
4.75
pF
6
10
26
kΩ
80
MHz
MCLK_IN LVCMOS SOURCE
1-kHz offset
–140
10-kHz offset
–149
100-kHz offset
–153
1-MHz offset
–148
Additive phase noise
fIN = 26 MHz, tr/tf ≤ 1 ns
Additive jitter
fIN = 26 MHz, VPP = 0.8 V, BW = 10–5 MHz
tDL
MCLK_IN to CLK_OUT_n
propagation delay
DCL
Output duty cycle
dBc/Hz
0.37
ps (rms)
11
fIN = 26 MHz, DCIN = 50%
45%
50%
ns
55%
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCLK_IN SINUSOIDAL SOURCE
VMA
Input amplitude
0.3
fIN = 26 MHz, VMA = 1.8 VPP
Additive phase noise
fIN = 26 MHz, VMA = 0.8 VPP
Additive jitter
tDS
MCLK_IN to CLK_OUT_1/2
propagation delay
DCs
Output duty cycle
1.8
1-kHz offset
–141
10-kHz offset
–149
100-kHz offset
–152
1-MHz offset
–148
1-kHz offset
–139
10-kHz offset
–146
100-kHz offset
–150
1-MHz offset
–146
fIN = 26 MHz, VMA = 1.8 VPP, BW = 10–5 MHz
dBc/Hz
0.41
ps (RMS)
12
fIN = 26 MHz, VMA > 1.8 VPP
45%
50%
V
ns
55%
CLK_OUT_N OUTPUTS
6
tr
20% to 80% rise time
CL = 10 pF to 50 pF
tf
20% to 80% fall time
CL = 10 pF to 50 pF
tsk
Channel-to-channel skew
CL = 10 pF to 50 pF (CL1 = CL2)
VOH
High-level output voltage
IOH = –100 μA, reference to VLDO
–0.1
VOL
Low-level output voltage
IOH = –8 mA
1
5.2
ns
1
5.2
ns
–0.5
0.5
ns
V
1.2
IOL = 20 μA
0.2
IOL = 8 mA
0.55
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7.6 Typical Characteristics
-90
3.54
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
3.53
3.52
3.51
-110
3.50
3.49
-120
3.48
Square Wave 1.8 V 1 µF
ICC (mA)
Additive Phase Noise (dBc/Hz)
-100
-130
Sine Wave 0.8 Vpp 1 µF
-140
TA = 85°C
3.47
3.46
3.45
TA = 25°C
3.44
3.43
-150
3.42
3.41
Sine Wave 1.8 Vpp 1 µF
-160
-170
1.E+01
TA = -40°C
3.40
3.39
1.E+02 1.E+03
1.E+04
1.E+05 1.E+06
3.38
1.E+07
0.3
0.6
0.9
1.2
1.5
1.8
Offset Frequency (Hz)
Figure 7-1. Additive Phase Noise vs Offset
Frequency
Input Am plitude (Vpp)
Figure 7-2. Supply Current vs Input Amplitude
3.50
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
3.49
3.48
TA = 85°C
3.47
3.46
ICC (mA)
3.45
3.44
TA = 25°C
3.43
3.42
3.41
TA = -40°C
3.40
3.39
3.38
3.37
3.36
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
V BATT (V)
Figure 7-3. Supply Current vs Input Frequency
200
180
160
Figure 7-4. Supply Current vs Supply Voltage
0
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
-10
-20
5.5 V
-30
140
3.3 V
-40
PSRR (dB)
120
ISB (nA)
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
2.3 V
100
80
-50
-60
-70
60
-80
40
-90
20
0
-40
-100
-15
10
35
60
85
-110
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Tem perature (°C)
Figure 7-5. Standby Current vs Temperature
Figure 7-6. Power Supply Rejection vs Input
Frequency
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2.4
5.0
VBATT = 3.3 V CVLDO = 1 µF
CBATT = 0.1 µF COUT = 30 pF
2.2
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
4.5
2.0
1.8
4.0
1.6
3.5
TA = 25°C
TA = -40°C
Time (ns)
1.4
Voltage (V)
TA = 85°C
1.2
1.0
0.8
3.0
2.5
2.0
0.6
1.5
0.4
1.0
0.2
0.0
0.5
-0.2
MCLK_IN
CLK_OUT1
0.0
-0.4
0
10
20
30
40
50 60
Tim e (ns)
70
80
90
0
100
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
4.5
4.0
20
30
40
50
60
70
CLOAD (pF)
Figure 7-7. Sine-Wave Input vs Square-Wave
Output
5.0
10
Figure 7-8. Rise Time vs Load
MCLK_IN
0.5 V/div
CLK_OUT1
0.5 V/div
CLK_OUT2
10 mV/div
TA = 85°C
TA = 25°C
Time (ns)
3.5
TA = -40°C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
60
70
0
CLOAD (pF)
Figure 7-9. Fall Time vs Load
8
20
40
60
80
100
120
140
160
180
200
Time (ns)
Figure 7-10. Digital Cross-Talk Scope Shot
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8 Detailed Description
8.1 Overview
The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as
mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. It buffers
a single master clock, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The
device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output.
The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for
an AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to-peak). CDC3RL02 has
been designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The
adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes
EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock
distribution lines.
The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3
V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8-V supply is externally available to provide regulated power to
peripheral devices such as a TCXO.
8.2 Functional Block Diagram
VBATT
VLDO
LDO
VCC
GND
VCC
MCLK_IN
CLK_OUT1
EN
CLK_REQ1
CLK_OUT2
EN
CLK_REQ2
Switch/
Decoder
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8.3 Feature Description
8.3.1 Low Additive Noise
The CDC3RL02 features –149 dBc/Hz at 10 kHz offset phase noise and 0.37 ps (RMS) of output jitter, to make
sure that the buffered signals are clean.
8.3.2 Regulated 1.8-V Externally Available I/O Supply
The CDC3RL02 allows users to connect to the output of the internal LDO, for providing power to other ICs. For
more information, refer to LDO.
8.3.3 Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package
Using the ultra-small YFP package, the CDC3RL02 is very small and allows it to be placed on a board with
minimum work.
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8.4 Device Functional Modes
Table 8-1 is the function table for CDC3RL02.
Table 8-1. Function Table
INPUTS
CLK_REQ1(1)
(1)
10
CLK_REQ2(1)
OUTPUTS
MCLK_IN
CLK_OUT1
CLK_OUT2
L
L
X
L
L
L
H
CLK
L
CLK
H
L
CLK
CLK
L
H
H
CLK
CLK
CLK
If a CLK_OUT will always be enabled, it is acceptable to tie its CLK_REQ pin to an external 1.8 V source (not VLDO).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Input Clock Squarer
Figure 9-1 shows the input stage of the CDC3RL02. The input signal at MCLK_IN can be a square wave or
sine wave. CMCLK is an internal AC coupling capacitor that allows a direct connection from the TCXO to the
CDC3RL02 without an external capacitor.
MCLK _IN
CMCLK
Figure 9-1. Input Stage with Internal AC Coupling Capacitor
Any external component added in the series path of the clock signal will potentially add phase noise and
jitter. The error source associated with the internal decoupling capacitor is included in the specification of the
CDC3RL02. The recommended clock frequency band of the CDC3RL02 is 10 MHz to 80 MHz for specified
functionality. All performance metrics are specified at 26 MHz. The lowest acceptable sinusoidal signal amplitude
is 0.8 VPP for specified performance. Amplitudes as low as 0.3 VPP are acceptable but with reduced phase-noise
and jitter performance.
9.1.2 Output Stage
Each output drives 1.8-V LVCMOS levels. Adaptive output buffers limit the rise/fall time of the output to within
1 ns to 5 ns with load capacitance between 10 pF and 50 pF. Fast slew rates introduce EMI into the system.
Each output buffer limits EMI by keeping the rise/fall time above 1 ns. Slow rise/fall times can induce additive
phase noise and duty cycle errors in the load device. The output buffer limits these errors by keeping the rise/fall
time below 5 ns. In addition, the output stage dynamically alters impedance based on the instantaneous voltage
level of the output. This dynamic change limits reflections keeping the output signal monotonic during transitions.
Each output is active low when not requested to avoid false clocking of the load device.
9.1.3 LDO
A low noise 1.8-V LDO is integrated to provide the I/O supply for the output buffers. The LDO output is externally
available to power a clock source such as a TCXO. A clean supply is provided to the clock buffers and the clock
source for optimum phase noise performance. The input range of the LDO allows the device to be powered
directly from a single cell Li battery. The LDO is enabled by either of the CLK_REQ_N signals. When disabled,
the device enters a low power shutdown mode consuming less than 1 μA from the battery. The LDO requires
an output decoupling capacitor in the range of 1 μF to 10 μF with an equivalent series resistance (ESR) of at
least 0.1 Ω for compensation and high-frequency PSR. This capacitor must stay within the specified range for
capacitance and ESR over the entire operating temperature range. A ceramic capacitor can be used if a small
external resistance is added in series with it to increase the effective ESR. An input bypass capacitor of 1 μF or
larger is recommended.
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9.2 Typical Application
The CDC3RL02 is ideal for use in mobile applications as shown in Figure 9-2. In this example, a single low noise
TCXO system clock source is buffered to drive a mobile GPS receiver and WLAN transceiver. Each peripheral
independently requests an active clock by asserting a single clock request line (CLK_REQ_1 or CLK_REQ_2).
When both clock request lines are inactive, the CDC3RL02 enters a low current shutdown mode. In this mode,
the LDO output, CLK_OUT_1, and CLK_OUT_2 are pulled to GND and the TCXO will be unpowered.
VLDO
VBATT
LDO
2.2 µF
1 µF
Li
CLK_REQ_1
TCXO REQ
CLK_OUT_1
MCLK _IN
TCXO CLK
CLK_REQ_2
TCXO REQ
CLK_OUT_2
TCXO CLK
TCXO
CDC3RL02
GPS
WLAN
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 9-2. Mobile Application
When either peripheral requests the clock, the CDC3RL02 will enable the LDO and power the TCXO. The
TCXO output (square wave, sine wave, or clipped sine wave) is converted to a square wave and buffered to the
requested output.
9.2.1 Design Requirements
For the typical application, the user must know the following parameters.
Table 9-1. Design Parameters
PARAMETER
DESCRIPTION
EXAMPLE VALUE
VBATT
Input voltage from battery or power supply
3.7 V
MCLK_IN
Input frequency from a TCXO
26 MHz
9.2.2 Detailed Design Procedure
The designer must make sure that all parameters are within the ranges specified in Recommended Operating
Conditions.
Each device which receives a clock output from the CDC3RL02 should have the CLK request pin connected to
the appropriate CLK_REQ pin on the CDC3RL02. This will enable the output buffer when a device requests the
clock signal.
It is possible to have a control the outputs of the clock by using a GPIO from a controller to control the CLK_REQ
pins.
If one of the outputs is unused, then tie the CLK_REQ and CLK_OUT pins to ground. If the user wants a
CLK_OUT pin always enabled, it is acceptable to tie the paired CLK_REQ pin to an external 1.8-V source (not
VLDO because the LDO output is not enabled until at least one CLK_REQ pin is high).
12
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9.2.3 Application Curve
2.4
VBATT = 3.3 V CVLDO = 1 µF
CBATT = 0.1 µF COUT = 30 pF
2.2
2.0
1.8
1.6
Voltage (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
MCLK_IN
CLK_OUT1
-0.4
0
10
20
30
40
50 60
Tim e (ns)
70
80
90
100
Figure 9-3. Sine Wave Input vs Output
9.3 Power Supply Recommendations
General power supply recommendations are to be considered for the CDC3RL02. These include:
•
•
Decoupling capacitors placed close to the VBATT pin of typical values (1 μF)
VBATT be within the recommended voltage range
9.4 Layout
9.4.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
•
•
•
Bypass capacitors should be used on power supplies and should be placed as close as possible to the VBATT
pin
Short trace-lengths should be used to avoid excessive loading
For improved performance on the clock output lines, use a ground trace on the sides of the clock trace to
minimize crosstalk and EMI
9.4.2 Layout Example
CLK_OUT1
0402 Decoupling
Cap
VBATT
A1
VLDO
CLK_REQ1
MCLK_IN
CLK_REQ2
GND
= Via to GND Plane
CLK_OUT2
= GND Trace
Figure 9-4. Example Layout for YFP Package
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CDC3RL02BYFPR
ACTIVE
DSBGA
YFP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
4LN
Samples
CDC3RL02YFPR
ACTIVE
DSBGA
YFP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
4LN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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