CDC7005 (BGA Package)
Evaluation Module Manual
High Performance Analog/CDC
User’s Guide
2006
Clock Drivers
SCAU005E
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Copyright © 2005, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
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Copyright © 2004, Texas Instruments Incorporated
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It is important to operate this EVM within the supply voltage range of 3 V and 3.6 V.
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as the input and output ranges are maintained. These components include but are not limited
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Copyright © 2004, Texas Instruments Incorporated
Related Documentation From Texas Instruments
Preface
Read This First
About This Manual
This manual explains how to use the CDC7005 evaluation module and to provide the guidelines to build the customer’s own systems. The manual includes
schematics, layout, bill of materials, and a software description.
How to Use This Manual
This document contains the following chapters:
- Chapter 1—Introduction
- Chapter 2—Quick Start
- Chapter 3—EVM Hardware
- Chapter 4—Serial Peripheral Interface (SPI) Software
- Chapter 5—Schematics, Board Layout, and Parts List
Related Documentation From Texas Instruments
-
CDC7005 Data Sheet, SCAS685, Texas Instruments
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
If You Need Assistance. . .
If you need assitance with this device, please email
clocks_apps@list.ti.com
iii
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
CDC7005 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2
Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
3
EVM Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Board View and Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Power Supply (P1, P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Onboard Switches and Indicators (S1−S2, D1−D4) . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Programming Interfaces (J27, J28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Loop Filter (J29−J35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 High-Speed Outputs and Inputs (J6−J15 and J19−J20) . . . . . . . . . . . . . . . . . . .
3.3.6 VCXO Inputs and Outputs (J23−J28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Serial Peripheral Interface (SPI) Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2
Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
5
Application Level Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Passive Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 Active Loop Filter—Internal Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Active Loop Filter—External Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-2
5-3
5-4
6
Parts List, Board Layouts, and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-2
6-4
6-8
3-1
3-2
3-4
3-4
3-4
3-4
3-5
3-5
3-5
3-6
v
Contents
Figures
3−1
4−1
5−2
5−3
5−4
6−1
6−2
6−3
6−4
6−5
Board View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Screen View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDC7005 With a Passive Loop Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDC7005 With an Active Loop Filter Using a CDC7005 Integrated OPA . . . . . . . . . . . . . .
CDC7005 With an Active Loop Filter Using OPA341 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component View and Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top Layer View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bottom Layer View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground Plane View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Layer View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
4-2
5-2
5-3
5-4
6-4
6-5
6-6
6-7
6-8
Tables
3−1
3−2
vi
Connectors, Switches, and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Filter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Chapter 1
Introduction
The CDC7005 is a high-performance, low phase noise and low skew clock
synchronizer that synchronizes an on-board voltage controlled crystal
oscillator (VCXO) frequency to an external reference clock. The device
operates up to 800 MHz. The PLL loop bandwidth and damping factor can be
adjusted to meet different system requirements by selecting the external
VCXO, loop filter components, frequency for PFD, and charge pump current.
Each of the five differential LVPECL outputs can be programmed by a serial
peripheral interface (SPI). The SPI allows individual control of the frequency
and enable/disable state of each output. As the system requires external
components like a loop filter and VCXO, this EVM provides an excellent way
to evaluate and modify the performance and parameters of the clock system
in conjunction with the specific customer application. Loop bandwidth can be
selected as low as 10 Hz or less, allowing this device to clean the system’s
clock jitter. The CDC7005 can be used as a simple 1:5 LVPECL buffer with
output dividing options.
Topic
1.1
Page
CDC7005 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Introduction
1-1
CDC7005 Functional Block Diagram
1.1 CDC7005 Functional Block Diagram
OPA_IN
−
OPA_OUT
OPA
+
OPA_IP
STATUS_REF
STATUS_VCXO
STATUS_LOCK
HOLD
REF_IN
LVCMOS
Input
CTRL_LE
Prgm Divider
M
Prgm Delay
M
Prgm Divider
N
Prgm Delay
N
PFD
VI
Reference
SPI LOGIC
CTRL_DATA
CP_OUT
Charge
Pump
CTRL_CLK
I_REF
PECL-TOLVTTL
NPD
NRESET
MUX_SEL
VCXO_IN
VCXO_INB
PECL
Input
Y0
/1
PECL
MUX0
PECL
Latch
PECL
Output
Y0B
PECL
MUX1
PECL
Latch
PECL
Output
Y1B
PECL
MUX2
PECL
Latch
PECL
Output
PECL
MUX3
PECL
Latch
PECL
Output
Y3B
PECL
MUX4
PECL
Latch
PECL
Output
Y4B
/2
Y1
/4
/8
Y2
/16
P Divider
Y2B
Y3
Y4
1-2
Chapter 2
Quick Start
In order to setup the EVM quickly and to take some measurements at default
settings, the following actions are required:
- Supply 3.3 V to P1, LED D4 will be on.
- Apply a single-ended reference clock to the reference clock input
(REF_IN). For default setting, the reference clock must be 1/8th of VCXO
frequency (if VCXO frequency is 245.76 MHz, then the reference clock
must be 30.72 MHz for locking).
- Connect Y0/Y0B (or Y1/Y1B) to oscilloscope in order to check output sig-
nal. Ensure the oscilloscope has 50 Ω to ground termination.
After power up, D1 is on if there is a valid reference clock and D2 is on if there
is a valid VCXO clock for the CDC7005. If the reference clock and VCXO
clocks are phase locked, D3 is on.
Quick Start
2-1
Chapter 3
EVM Hardware
This chapter discusses the EVM hardware.
Topic
Page
3.1
Board View and Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3
Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
EVM Hardware
3-1
Board View and Connector Location
3.1 Board View and Connector Location
Figure 3−1. Board View
3-2
Connector Description
3.2 Connector Description
Table 3−1. Connectors, Switches, and Indicators
Reference
Description
P1
Power supply 3.3 V
P2
GND
J5
Status outputs (STATUS_LOCK, STATUS_VCXO, STATUS_REF)
J6, J7
Y0/Y0B PECL differential output
J8, J9
Y1/Y1B PECL differential output
J10, J11
Y2/Y2B PECL differential output
J12, J13
Y3/Y3B PECL differential output
J14, J15
Y4/Y4B PECL differential output
J17
VCXO enable
J36
Reference clock input sense enable (on or off)
J19
Reference clock input
J20
Reference clock input sense
J21, J22
VCXO_IN/VCXO_INB input selector/VCXO output selector
J23, J24
External VCXO_IN/VCXO_INB input/VCXO output sense
J27
External programming interface by parallel port
J28
External programming interface by universal pins
J29, J34
Filter type selector
J30
Non-inverted OPA input selector (external or internal OPA)
J31
Power supply for external OPA (on or off)
J32
Inverted OPA input selector (external or internal OPA)
J33
OPA output selector (internal or external OPA)
J35
VCXO control voltage sense
SW1
Power-down key
SW2
Reset key
D1
STATUS_REF indicator
D2
STATUS_VCXO indicator
D3
STATUS_LOCK indicator
3.3 Hardware Configuration
This section describes the board configuration using on-board jumpers and
solder bridges.
Note:
Default settings are in italics.
EVM Hardware
3-3
Hardware Configuration
3.3.1
Power Supply (P1, P2)
- Supply 3.3 V ±10% on P1 and P2 using a stabilized external power supply.
J
3.3.2
WARNING: Never supply more than 3.6 V on P1.
Onboard Switches and Indicators (P1, P2, D1−D4)
- Push SW1 to enter the power-down mode of the CDC7005 device. Then
all current sources are switched off, all outputs are switched into 3-state,
and all dividers (M, N, and P) are reset to default.
- Push SW2 to enter the reset mode of the device. Then the dividers (M, N,
and P) are reset to default.
- The three status outputs of the CDC7005 are fed to LED indicators and
to pin header J5. An D1 on condition indicates a valid reference input clock
signal, D2 is on if the VCXO input clock is valid, and D3 turns on if PLL has
been locked.
- D4 indicates power supply
Default setting: I_REF is connected to ground through a 12-kΩ resistor. For
default operation, the device uses an internal resistor.
Note:
In case of low input impedance of the VCXO control voltage input, there is
a possibility D3 may not turn on to indicate locking.
3.3.3
Programming Interfaces (J27, J28)
The SPI of the device is used for writing to the control register of the device.
It consists of three control lines CTRL_CLK, CTRL_DATA, and CTRL_LE.
There are four 30-bit wide RAM registers, which can be addressed by the two
LSBs of a transferred word. Every transmitted word must have 32 bits, starting
with MSB. After supplying power or activating the power-down mode, the
registers are loaded with the device default values internally (see the
CDC7005 data sheet, SCAS685). However, if specific register settings are
required for any applications, there are two ways to program the device
externally:
- Connect the parallel port cable to the PC and EVM parallel port. This
needs control S/W (see Chapter 5).
- Connecting an external pattern generator to J28. Connect pin 18 of J27
to the ground.
3-4
Hardware Configuration
3.3.4
Loop Filter (J29−J35)
The loop filter is one of the key elements determining the loop bandwidth of
the PLL. The loop filter converts the charge pump current into the control
voltage for the voltage controlled oscillator. The phase difference between the
input clocks of the phase frequency detector determines the width of the
charge pump output current pulses. These high frequency pulses are
transformed into a voltage to control the oscillator.
Basically, three types of loop filters are implemented on the EVM.
- Passive loop filter
- Active loop filter using an operational amplifier (OPA) implemented on the
CDC7005.
- Active loop filter using an external low-noise OPA.
Filter types can be selected by soldering the bridges J29−J30 and J32−J34,
see Table 3−2. Control voltage of the VCXO can be measured at J35. If an
external OPA is used, it needs to be switched on by connecting J31. For
example, passive filter operation is provided when pads 1 and 3 of J29 are
solder bridged and pads 1 and 3 of J34 are solder bridged.
Default setting: Passive Loop Filter
Note:
Using an active loop filter requires changing of the charge pump direction via
SPI programming.
Table 3−2. Filter Configurations
Bridge
Passive Filter
Active With An Internal OPA
Active With An External OPA
J29
1−3
1−2
1−2
J30
Don’t care
1−3
1−2
J31
Open
Open
Closed
J32
Don’t care
1−2
1−3
J33
Don’t care
1−2
1−3
J34
1−3
1−2
1−2
3.3.5
High-Speed Outputs and Inputs (J6−J15 and J19−J20)
The CDC7005 drives five differential LVPECL outputs. All PECL outputs are
ac-coupled and terminated with 150 Ω to GND. This is in contrast to typical
LVPECL termination, which requires VCC − 2 V as termination voltage. The
reason is to simplify the power supply scheme. The device output’s trace
impedance is 50 Ω and traces are matched in length. All outputs have options
for pull-up and pull-down resistors.
EVM Hardware
3-5
Hardware Configuration
The reference input clock signal has to be applied to J19. The reference input
clock signal can be sensed on J20. In this case, close the bridge J36 (the
oscilloscope’s 50 Ω may be used to terminate the 50-Ω trace). The reference
input clock sense line is matched to the LVPECL outputs line to avoid any
additional delay offset. The input is ac-coupled (C57) and properly biased with
100-Ω pull-up and 100-Ω pull-down resistors.
3.3.6
VCXO Inputs and Outputs (J23−J28)
The CDC7005 requires an external VCXO in order to complete the PLL loop.
The VCXO adjusts the frequency and phase depending on the control voltage
level coming from loop filter and provide the input clock to the LVPECL block.
The circuitry lets the user:
- Measure the on-board VCXO output from outside on J23 and J24 (close
1−3 of J21 and 1−3 of J22).
- Feed the LVPECL clock from an external source into the VCXO_IN/
VCXO_INB inputs of the CDC7005. If the CDC7005 is intended to be used
as a programmable clock buffer without PLL capabilities, then close 2−3
of J21 and J22. In case of using an external oscillator (or VCXO), close 2−3
of J21 and J22. The VCXO output clock has to be applied on J23 and J24
and VCXO control voltage can be taken on TP1.
Default settings: J17 is open, 1−2 of J21 and J22 are connected.
Note:
This EVM offers universal foot print for VCXO, so it allows the addition of
several VCXO’s.
3-6
Chapter 4
Serial Peripheral Interface (SPI) Software(1)
This chapter discusses the serial peripheral interface software.
Topic
Page
4.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2
Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
1) Copyright 2005 National Instruments Corporation. All Rights Reserved.
Copyright 2005 Texas Instruments Incorporated. All Rights Reserved.
Serial Peripheral Interface (SPI) Software (1)
4-1
Functional Description
4.1 Functional Description
Programming software is required for programming the internal control
register of the CDC7005 in the EVM. The software runs under Windows 2000
/ XP / XP *64. A quick installation is required prior to use. See Section 4.2
Software Installation.
There are several cases where programming is mandatory:
-
Figure 4−1. Screen View
4-2
Using an active loop filter
Reference clock and VCXO clock do not have a ratio of 1:8.
Changing of divider ratio or disabling of certain LVPECL output
Changing of phase offset, (delay M/N)
Changing of charge pump output current
Widening the lock detect window
Software Installation
4.2 Software Installation
Use the following steps to install the SPI control software.
1) Download the CDC7005 SPI Software from the TI Website (www.ti.com)
2) Run program setup.exe
3) Reboot your computer
4) Run the software from Start −> Programs −> CDC7005 SPI Parallel EVM
Serial Peripheral Interface (SPI) Software (1)
4-3
Chapter 5
Application Level Circuit Diagram
This chapter discusses the application level circuit diagram.
Topic
5.1
Page
Application Level Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Application Level Circuit Diagram
5-1
Application Level Circuit Diagram
5.1 Application Level Circuit Diagram
In the following applications sections all three loop filter configurations are
discussed.
5.1.1
Passive Loop Filter
The passive loop filter is a second order filter (two poles, one zero). The zero
is required for the overall loop stability. R1, C1, and C2 generate the dominant
pole of the system. A second pole is introduced by R2 and C3.
Figure 5−1. CDC7005 With a Passive Loop Filter Configuration
Low-Pass Filter
R2
160 Ω
VCXO
245.76 MHz; Gain = 26.5kHz/V
V_CTRL
PECL_OUT_B
PECL_OUT
C3
100 nF
CDC7005
REF_IN
OPA_OUT
OPA_IP
R1
4.7 kΩ
OPA_IN
CP_OUT
VCC
VCC
10 nF
130 Ω
130 Ω
Yn
5.1.2
10 nF
VCXO_IN
VCXO_IN_B
R
82 Ω
C1
22 μF
CTRL_LE
CTRL_DATA
CTRL_CLK STATUS_REF
STATUS_VCXO
STATUS_LOCK
SPI
R
82 Ω
C2
100 nF
YnB
R
150 Ω
R
150 Ω
Active Loop Filter—Internal Operational Amplifier
The active loop filter requires zero for loop stability, which is generated by R2
and C2 components. The first pole is introduced by R3 and C3 and the second
pole is introduced by R1 and C1.
5-2
Application Level Circuit Diagram
Figure 5−2. CDC7005 With an Active Loop Filter Using a CDC7005 Integrated OPA
VCXO
245.76 MHz; Gain = 26.5kHz/V
Low-Pass Filter
V_CTRL
PECL_OUT_B
C3
100 nF
PECL_OUT
Vcc
R3
10 KΩ
R2
4.7 KΩ
CDC7005
REF_IN
C2
10 μF
R5
10 KΩ
OPA_OUT
OPA_IP
OPA_IN
CP_OUT
STATUS_REF
CTRL_LE
CTRL_DATA STATUS_VCXO
STATUS_LOCK
CTRL_CLK
SPI
VCC
C1
100 nF
C3
100 nF
R6
10 KΩ
VCC
10 nF
130 Ω
130 Ω
Yn
VCXO_IN
VCXO_IN_B
10 nF
Yn_B
R
150 Ω
R
82 Ω
R1
180 Ω
R
150 Ω
R
82 Ω
Application Level Circuit Diagram
5-3
Application Level Circuit Diagram
5.1.3
Active Loop Filter—External Operational Amplifier
Figure 5−3. CDC7005 With an Active Loop Filter Using OPA341
Low-Pass Filter
R3
10 KΩ
VCXO
245.76 MHz; Gain = 26.5kHz/V
PECL_OUT_B
PECL_OUT
V_CTRL
C3
100 nF
Vcc
C2
10 μF
Vcc
CDC7005
REF_IN
R5
10 KΩ
OPA_OUT
InN
R1
180 Ω OPA341 Out
InP
OPA_IP
OPA_IN
CP_OUT
CTRL_LE
STATUS_REF
CTRL_DATA STATUS_VCXO
CTRL_CLK STATUS_LOCK
SPI
VCC
130 Ω
5-4
R6
10 KΩ
VCC
130 Ω
R
82 Ω
C1
100 nF
Yn
VCXO_IN
VCXO_IN_B
R
82 Ω
YnB
R
150 Ω
10 nF
10 nF
R
150 Ω
C1
100 nF
Chapter 6
Parts List, Board Layout, and Schematic
This chapter contains the parts list, board layout, and schematic for the
CDC7005 EVM.
Topic
Page
6.1
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Parts List, Board Layout, and Schematic
6-1
Parts List
6.1 Parts List
Item Qty
Reference Designator
Part
Part Number
1
3
C14, C15, C78
22 μF, 16 V 20%
tantalum TE SMD
Panasonic ECS−T1CC226R
2
4
C16, C64, C65, C79
10 μF, 16 V TANT
TEH SER SMD
Panasonic ECS−H1CC106R
3
4
C17, C80, C35, C55
0.1 μF, 16 V ceramic
Y5V 0402
Yageo 04022F104Z7B20D
4
2
C81, C18
0.033 uF, 10% 16 V
X5R 0402 ceramic
AVX 0402YD333KAT2A
5
22
C19, C23, C24, C25,
C26, C27, C28, C29,
C30, C31, C32, C57,
C58, C60, C62, C63,
C66, C67, C68, C69,
C82, C83
0.01 μF, 25 V
ceramic X7R 0402
Panasonic ECJ−0EB1E103K
6
2
C21, C20
0.01 μF, 50 V
ceramic Y5V 0402
Panasonic ECJ−0EF1H103Z
7
6
C34, C56, C74, C75,
C76, C77
100 pF, 25 V ceramic
X7R 0402
Panasonic ECJ−0EB1E101K
9
3
C39, C40, C41
Ceramic 10 pF, 25 V
C0G 0402
Panasonic ECD−G0E100C
10
7
C42, C47, C49, C50,
C52, C53, C54
0.1 μF, 16 V film
0805 20%
Panasonic
ECP−U1C104MA5
11
1
C43
NU
Panasonic
ECP−U1C104MA5
12
2
C44, C48
10 μF, 25 V 10% X5R Murata
1210 ceramic
GRM32DR61E106KA12L
13
1
C51
22 μF, 10 V 10% X7R Murata
1210 ceramic
GRM32ER71A226KE20L
14
4
C59, R60, R61, C61
0Ω
Panasonic ERJ−2GE0R00X
15
4
C70, C71, C72, C73
0.022 μF 10% 16 V
X7R 0402
AVX 0402YC223KAT2A
16
3
D1, D2, D3
LED, amber
Lite−On LTST−C150AKT
17
1
D4
LED, green
Lite−On LTST−C150KGKT
18
2
J5, J28
HDR4
Header 4 pos, 0.100 ctr
19
6
J6, J7, J8, J9, J19, J20
SMA CONN
Johnson Comp
142−0701−841
20
8
J10, J11, J12, J13, J14,
J15, J23, J24
NU SMA CONN
21
3
J17, J21, J22
HDR3
Header 3 pos, 0.100 ctr
22
1
J27
CONN 25-pin male
DSUB
SPC Technology
DB−25P−PCB
6-2
Note
Must be
film cap
Parts List
Item Qty
Reference Designator
Part
Part Number
Note
23
5
J29, J30, J32, J33, J34
NU HDR
Not used (header 3 pos,
0.100 ctr)
J29, J34
pin 1−3
shorted
23a
2
MP4
Jumper wire, 00.1”
long
3M/ESD 923345−01−C
To short pin
1 and 3 of
J29, J34
24
3
J31, J35, J36
HDR2
Header 2 pos, 0.1 ctr
25
1
L1
Inductor chip 20.2NH
20% SMT
J W Miller Magnetics
PM0805−2N2M
26
2
L3, L2
75 Ω at 100 MHz
Murata BLM31PG500SN1L
27
1
P1
PWR_IN banana jack Pomona Model 3267
28
1
P2
GND banana jack
Pomona Model 3267
29
9
R1, R2, R36, R45, R46,
R47, R51, R53, R54
100 kΩ 1/16W 1%
0402 SMD
Panasonic ERJ−2RKF1002X
30
3
R3, R4, R5
750 Ω 1/16W 5%
0402 SMD
Panasonic ERJ−2GEJ751X
31
1
R6
12 kΩ 1/16W 5%
0402 SMD
Panasonic ERJ−2GEJ123X
32
10
R7, R8, R11, R12, R15,
R16, R19, R20, R23,
R24
150 Ω 1/16W 1%
0402 SMD
Panasonic ERJ−2RKF1500X
33
20
R9, R10, R13, R14, R17,
R18, R21, R22, R25,
R26, R66, R67, R68,
R69, R70, R71, R72,
R73, R74, R75
NU RES
Panasonic ERJ−2RKF1000X
34
5
R37, R38, R39, R56,
R57
100 Ω 1/16W 1%
0402 SMD
Panasonic ERJ−2RKF1000X
35
4
R40, R41, R42, R50
100 kΩ 1/16W 1%
0402 SMD
Panasonic ERJ−2RKF1003X
36
1
R43
180 Ω 1/16W 5%
0402 SMD
Panasonic ERJ−2GEJ181X
37
2
R48, R44
40.7 kΩ 1/16W 5%
0402 SMD
Panasonic ERJ−2GEJ472X
38
1
R49
160 Ω 1/16W 5%
0402 SMD
Panasonic ERJ−2GEJ161X
39
1
R55
NU
Panasonic ERJ−2GEJ510X
40
2
R62, R58
130 Ω 1/16W 5%
0402 SMD
Panasonic ERJ−2GEJ131X
41
2
R59, R64
82 Ω 1/16W 5% 0402 Panasonic ERJ−2GEJ820X
SMD
42
1
R63
NU
NU
43
1
R65
10.5 kΩ 1/16W 1%
0402 SMD
Panasonic ERJ−2RKF1501X
44
2
SW2, SW1
SW pushbutton
KT11P3JM
Parts List, Board Layout, and Schematic
6-3
Parts List
Item Qty
Reference Designator
Part
Part Number
45
1
TP2
T point PC BLK
Keystone Elec 5011
45a
1
TP1
T point PC WHT
Keystone Elec 5012
46
1
U1
CDC7005ZVA
Texas Instruments
CDC7005ZVAT
47
1
U4
SN74LV125
Texas Instruments
SN74LV125AD
48
1
U5
OPA341
Texas Instruments
OPA341UA
49
1
VCXO1
TCO 2111
Epson Toyocom VCXO
50
4
MP3
Stand off
Legs for
PCB
51
4
MP2
Screw
Legs for
PCB
6.2 Board Layout
Figure 6−1. Component View and Silkscreen
PWR
P1
P2
6-4
Y4B
Y4
Y3B Y3
Note
Parts List
Figure 6−2. Top Layer View
Parts List, Board Layout, and Schematic
6-5
Parts List
Figure 6−3. Bottom Layer View
6-6
Parts List
Figure 6−4. Ground Plane View
Parts List, Board Layout, and Schematic
6-7
Parts List
Figure 6−5. Power Layer View
6.3 Schematic
The following page contains the schematic for the CDC7005.
6-8
A
B
C
1 1
GND
P2
1 1
PWR_IN
P1
2
1
SMA
5
R65
1.5K
D4
GREEN
CLK_SENSE
R55 NU
+ C14
GND
2
L2
C ircuits
4
10n
1
R50 2
100K
VCC
C35100n
1
2
C59
1
2
0 ohm
1
J21 2
3
GND
VCC
GND
22u
+ C15
GND
22u
+ C78
10u
+ C16
10u
+ C79
C80
100n
C17
100n
C81
100n
GND
4
C18
100n
R47 2
10K
C19
47n
2
R51 10K
1
R59
1
82
130
J29
C63
10n
C83
10n
GND
C21
1
RST
C20
1
2
2
2
PWRDWN 2
10n
10n
R2 10K
1
R1 10K
1
2
VCC R 62 130
1
2
1
0 ohm
2
J22 3
2
1
R64
82
GND
SW2
C82
47n
2
R 58
2
J36
1
GND
C51
22uF
GND
SW1
C61
1
VCC
3
1
J33 2
C48
10uF
C47
. 1uF
OPA341
U5
GND
6
C44
2
1 1 R44 2
4.7K
10uF C43
2
1
J30
NU
C42
R43
2
1
180
R48
. 1uF
4.7K GND
1 R56 2
100
1 R57 2
100
C52
. 1uF
R61
2 R60 1 2
1
0 ohm
0 ohm
1
VCC 2
R63
NU
VC XO_INB_SMA
AVCC
VCC
R49 2
160
C53
. 1uF
1
C50
1
. 1uF
GND
1
2
J34 1
3
V CHECK
J35
VC XO_IN_SMA
C58 10n
1
1
2
50 OHM @ 100MHZ
47u
2
C57 10n
1
.1uF
C54
2
1
V_CTRL
GND
VCXO_6
1
2
5 0 OHM @ 100MHZ
L3
Loop Filter
VCXO1
1
2
1 V_CTRLVCC 6C34
2 EN
5 100P
GND
3 GND OUTB
OUT 4
TP1
C62
1 VCXO_IN_EXT 1
2
10n
C60
VCXO_INB_EXT1
2
J23
PWR_IN
2
SMA
J24
1
GND
10K
2 R 36 1
1
2
J17 3
GND
TP2
REFCLK
1
2
VCC
J20 GND
1
J19
SMA
SMA
3
GND
GND
GND
2
GND
2
3
3
3
2
Passive Filter (Default Setting): short pin 1 & 3 on J29, J34
1
2
2
21
1
2
3
1
2
D
1
12
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
− 2
+ 3
VCXO_IN
VCXO_INB
OP A_IN
OPA_IP
REF _IN
GND
1
C64
22uF
C65
22uF
AVCC
2
2
L1
AVCC
10p
10p
R38
100
C69
100n
C66
100n
GND
3
VCC
J31
3
1
2 J32
2.2nH
SPI_DATA
SPI_CLK
SPI_LE
C39
1
C40
VCC
1
J28 2
3
4
HDR4
GND
R37
100
C 41 10p
1
2
PW R_DWN
RESET
3
1
2
2
1
OUT
OUTB
2
1
2
1
1
2
1
2
2
1
1
1
2
1
2
2
1
5
7
8
4
1
1
2
VCC
R45
10K
R46
10K
2
C49
.1uF
GND
1
1
1
2
1
2
CT RL_LE
1
2
CTRL_CLK
1
1
VCC
100K
1
VCC
C68
100n
C77
10n
C67
100n
3
GND
C73
39n
C70
39n
C71
39n
GND
1OE VCC 142
1A 4OE 13
1Y
4A 12
2OE 4Y 11
2A 3OE 10
2Y
3A 9
GND 3Y 8
SN74LV125
U4
1
2
C56100P
C55100n
1
2
R 40 100K
1
14
J27 15
16
17
18
19
20
21
22
23
24
25
26
27
GND
1
2
3
4
5
6
7
GND
2
R 41 100K
2
1
R42
PARALLEL PORT
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
LE
R39
100
2
GND
VCC
C75
10n
C72
39n
C74
10n
10KR54
1
2
GND
DATA
VCC
R53 10K
1
VCC
GND
C76
10n
1
J5 2
C7 AVCC
VCC G5
C6 AVCC
3
VCC G6
C5 AVCC
4
VCC G7
CP_OUT
HDR4
GND
C4 AVCC
OPA_OUT
C3 AVCC
CP_OUTA4
A7
OPA_OUT
R6
12K
S
TATUS_LOCK
A1
A8
STATUS_LOCK
I_ REF2
A2 CTRL_LE
C1
1
CTRL_CLK
I_REF C8
STATUS_REF
A3 CTRL_DATA
STATUS_REF
STATUS_VCXO
A5 OPA_IN STATUS_VCXO
D8
A6
Y0 F1
B1 OPA_IP
REF_IN
Y0B G1
Y1
H2
Y1
Y1B
D1 VCXO_IN
H3
Y1B H4
Y2
E1 VCXO_INB
Y2
Y2B
Y2B H5
Y3
H1 NPD
H6
Y3
Y3B
H8 NRESET
Y3B H7
Y4
Y4 G8
Y4B
U1
F8
CDC7005ZVA Y4B
B2 GND
GND F6
B3 GND
F5
GND
B4 GND
GND F4
B5 GND
GND F3
1
2
1
1
2
1
2
1
2
D7
E3
E4
E5
E6
E7
E8
F7
G2
G3
G4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2
R4
2
R5
2
R11
150
2
R15
150
2
R8
150
2
C 26 10n
1
R16
150
R20
150
GND
R24
150
2
2
2
C 32 10n
1
C 31 10n
1
2
C30 10n
1
C29 10n
1
2
C28 10n
1
C27 10n
1
2
2
GND
2
R14
NU
R69
NU
R18
NU
GND
R71
NU
GND
R25 VCC
NU
VCC
R22
NU Y3B_SMA
Y3_SMA
R21
NU GND
VCC
D a te:
C
Title
GND
1
2
GND
GND
SMA
J14 GND
2
2
GND
1
11
ofSheet
CDC7005EVM−SCH
F ri day, Se ptember 10, 2004
CDC7005 Evaluation Module
SMA
J15
2
1
GND
2
SMA
J7
SMA
J12 GND
Y4_SMA
1
GND
2
2
SMA
J8
1
3
SMA
J10 GND
1
GND
GND
GND
2
2
1
SMA
R73 J13
NU
1
R72
NU
Y4B_SMA
1
R75
NU
GND
R26
NU
R74
NU
SMA
J11
VCC
Y2B_SMA
1
2
SMA
J9
R70
NU Y2_SMA
VCC
GND
R67
NU
3
SMA
J6
VCC
R661
NU
Y1B_SMA 1
Y1_SMA
GND
VCC
R68
NU
R17 GND
NU
VCC
VCC
R9
NU
R10
Y0B_SMA NU
C 24 10n
VCC
1
C 23 10n
Y0_SMA
1
2
R13
NU
GND
GND
GND
R7
150
A mberD2
1
A mberD3
1
2
A mberD1
1
2
R12
150
GND
R19
150
R23
150
Y0
Y0B
750
1
C 25 10n
GND
1
2
750
1
R3
2
750
1
GND
1
1
2
2
1
CT RL_DATA
1
2
2
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
2
1
2
1
2
1
Parts List, Board Layout, and Schematic
2
2
1
1
B6
B7
B8
C2
D2
D3
D4
D5
D6
E2
F2
2
2
1
1
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
2
1
2
1
2
2
2
1
12
1
1
2
2
1
2
1
2
3
2
1
2
1
2
3
3
3
3
3
3
3
5
B
A
B
C
D
Parts List
6-9
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