CDC924DL

CDC924 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS607A – NOVEMBER 1998 – REVISED MAY 1999 D D D D D D D D D Supports Pentium III Class Motherboards Uses a 14.318-MHz Crystal Input to Generate Multiple Output Frequencies Includes Spread Spectrum Clocking (SSC), 0.5% Downspread for Reduced EMI Performance Power Management Control Terminals Low Output Skew and Jitter for Clock Distribution 2.5-V and 3.3-V Supplies Generates the Following Clocks: – 4 CPU (2.5 V, 100/133 MHz) – 7 PCI (3.3 V, 33.3 MHz) – 1 PCI_F (Free Running, 3.3 V, 33.3 MHz) – 2 CPU/2 (2.5 V, 50/66 MHz) – 3 APIC (2.5 V, 16.67 MHz) – 4 3V66 (3.3 V, 66 MHz) – 2 REF (3.3 V, 14.318 MHz) – 1 48MHz (3.3 V, 48 MHz) Packaged in 56-Pin SSOP Package Designed for Use with TI’s Direct Rambus Clock Generators (CDCR81, CDCR82, CDCR83) description The CDC924 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. DL PACKAGE (TOP VIEW) GND REF0 REF1 VDD3.3V XIN XOUT GND PCI_F PCI1 VDD3.3V PCI2 PCI3 GND PCI4 PCI5 VDD3.3V PCI6 PCI7 GND GND 3V66(0) 3V66(1) VDD3.3V GND 3V66(2) 3V66(3) VDD3.3V SEL133/100 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 VDD2.5V APIC2 APIC1 APIC0 GND VDD2.5V CPU_DIV2(1) CPU_DIV2(0) GND VDD2.5V CPU3 CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PCI_STOP CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state. The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel and Pentium III are trademarks of Intel Corporation. Direct Rambus and Rambus are trademarks of Rambus Inc. Copyright  1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC924 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS607A – NOVEMBER 1998 – REVISED MAY 1999 description (continued) Since the CDC924 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts. function tables SELECT FUNCTIONS INPUTS SEL133/ 100 SEL1 L L OUTPUTS FUNCTION SEL0 CPU CPU_DIV2 3V66 PCI, PCI_F 48MHz REF APIC L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 3-state L H N/A N/A N/A N/A N/A N/A N/A Reserved L H L 100 MHz 50 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off L H H 100 MHz 50 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on H L L TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 Test H L H N/A N/A N/A N/A N/A N/A N/A Reserved H H L 133 MHz 66 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off H H H 133 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on ENABLE FUNCTIONS INPUTS OUTPUTS INTERNAL CPU_STOP PWR_DWN PCI_STOP CPU CPU_DIV2 APIC 3V66 PCI PCI_F REF, 48MHz X L X L L L L L L L Off Off L H L L On On L L On On On On L H H L On On L On On On On On H H L On On On On L On On On On H H H On On On On On On On On On OUTPUT BUFFER SPECIFICATIONS 2 BUFFER NAME VDD RANGE (V) IMPEDANCE (Ω) BUFFER TYPE CPU, CPU_DIV2, APIC 2.375 – 2.625 13.5 – 45 TYPE 1 48MHz, REF 3.135 – 3.465 20 – 60 TYPE 3 PCI, PCI_F, 3V66 3.135 – 3.465 12 – 55 TYPE 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Crystal VCOs CDC924 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS607A – NOVEMBER 1998 – REVISED MAY 1999 Terminal Functions TERMINAL NAME 3V66 [0–3] 48MHz NO. I/O DESCRIPTION 21, 22, 25, 26 O 3.3 V, Type 5, 66-MHz clock outputs 30 O 3.3 V, Type 3, 48-MHz clock output APIC [0–2] 53, 54, 55 O 2.5 V, Type 1, APIC clock outputs CPU [0–3] 41, 42, 45, 46 O 2.5 V, Type 1, CPU clock outputs 49, 50 O 2.5 V, Type 1, CPU_DIV2 clock outputs 36 I Disables CPU clock to low state CPU_DIV2 [0–1] CPU_STOP GND PCI [1–7] 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 9, 11, 12, 14, Ground O 3.3 V, Type 5, 33-MHz PCI clock outputs 15, 17, 18 PCI_F 8 O Free-running 3.3-V, Type 5, 33-MHz PCI clock output PCI_STOP 37 I Disables PCI clock to low state PWR_DWN 35 I Power down for complete device with outputs forced low REF0, REF1 2, 3 O 3.3 V, Type 3, 14.318-MHz reference clock output SEL0, SEL1 32, 33 I LVTTL level logic select terminals for function selection SEL133/100 28 I LVTTL level logic select pins for enabling 100/133 MHz SPREAD 34 I Disables SSC function VDD3.3V 4, 10, 16, 23, 27, 31, 39 VDD2.5V XIN 43, 47, 51, 56 XOUT Power for the 3V66, 48MHz, PCI, REF outputs and CORE logic Power for CPU and APIC outputs 5 I Crystal input – 14.318 MHz 6 O Crystal output – 14.318 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CDC924 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS607A – NOVEMBER 1998 – REVISED MAY 1999 spread spectrum clock (SSC) implementation for CDC924 Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency, which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation of the CPU–PLL allows to distribute the energy to many different frequencies which reduces the power peak. A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in Figure 1. Highest Peak ∆ Non-SSC SSC δ of fnom fnom Figure 1. Frequency Power Spectrum With and Without the Use of SSC The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a “down-spread modulation”. The peak reduction depends on the modulation scheme and modulation profile. System performance and timing requirements are the limiting factors for actual design implementations. The implementation was driven to keep the average clock frequency closed to its upper specification limit. The modulation amount was set to approximately –0.5%. Period of Output Frequency – ns In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for CDC924 is shown in Figure 2. 10.03 10.02 10.01 10 9.99 9.98 9.97 5 10 15 20 25 30 35 Period of Modulation Signal – µs Figure 2. SSC Modulation Profile 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 40 45 CDC924 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS607A – NOVEMBER 1998 – REVISED MAY 1999 functional block diagram SEL133/100 28 SEL0 32 SEL1 33 3–State Control Logic 48–MHz Inactive Test SEL133/100 2*REF 14.318 MHz (2,3) XIN XOUT 5 6 1*48MHz 48 MHz (30) 48 MHz PLL Xtal Oscillator STOP /4 CPU_STOP 36 STOP SPREAD 34 Spread Logic CPU PLL /2 /2 Sync Logic & Power Down Logic /3 4*AGP (3V66) 66 MHz (21,22,25,26) 4*CPU 100/133 MHz (41,42,45,46) 2*CPU_DIV2 50/66 MHz (49,50) 3*APIC 16.67 MHz (53, 54, 55) /2 /3 1*PCI_F 33 MHz (8) /4 STOP PCI_STOP PWR_DOWN 37 7*PCI 33 MHz (9,11,12,14, 15,17,18) 35 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDC924 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS607A – NOVEMBER 1998 – REVISED MAY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Voltage range applied to any output in the high-impedance state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VDD + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 × IOL Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATNG DERATING FACTOR† ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DL 1558.6 mW 12.468 mW/°C 997.5 mW 810.52 mW † This is the inverse of the traditional junction-to-case thermal resistance (RθJA) and uses a board-mounted device at 80.2°C/W. recommended operating conditions (see Note 2) MIN Supply voltage voltage, VDD NOM† 3.465 2.5 V 2.375 2.625 2 VDD + 0.3 V V GND – 0.3 V 0.8 V VDD –12 V Low-level input voltage, VIL Input voltage, VI 0 CPUx, CPU_DIV2x Low level output current, Low-level current IOL APICx –12 48MHz, REFx –14 PCIx, PCI_F, 3V66x –18 CPUx, CPU_DIV2x 12 APICx 12 48MHz, REFx 9 PCIx, PCI_F, 3V66x Reference frequency, f(XIN)‡ Crystal frequency, f(XTAL)§ UNIT 3.135 High-level input voltage, VIH High level output current, High-level current IOH MAX 3.3 V Normal mode mA mA 12 Test mode Operating free-air temperature, TA V 130 13.8 0 14.318 MHz 14.8 85 MHz °C NOTE 2: Unused inputs must be held high or low to prevent them from floating. † All nominal values are measured at their respective nominal VDD values. ‡ Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven externally up to f(XIN) = 130 MHz. If XIN is driven externally, XOUT is floating. § This is a series fundamental crystal with fO = 14.31818 MHz. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC924 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS607A – NOVEMBER 1998 – REVISED MAY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK RI IIH TEST CONDITIONS Input clamp voltage Input resistance High-level input current XIN-XOUT VDD = 3.135 V, VDD = 3.465 V, II = –18 mA VI = VDD –0.5 V XOUT VDD = 3.135 V, VI = VDD –0.5 V SEL0, SEL1, CPU_STOP, PCI_STOP, SPREAD VDD = 3.465 V, SEL133/100 Low-level input current kΩ VI = VDD