CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
D
D
D
D
D
D
D
D
D
Generates Clocks for Pentium4
Microprocessors
Uses a 14.318 MHz Crystal Input to
Generate Multiple Output Frequencies
Includes Spread Spectrum Clocking (SSC),
0.6% Downspread for Reduced EMI With
Theoretical EMI Damping of 7 dB†
Power Management Control Terminals
Low Output Skew and Jitter for Clock
Distribution
Operates From Single 3.3-V Supply
Consumes Less Than 30-mA Power-Down
Current
Generates the Following Clocks:
– 4 HCLK (Host) (Different Pairs–
100/133 MHz)
– 1 3VMREF Pair (3.3 V, 180° Shifted
50/66 MHz)
– 10 PCI (3.3 V, 33.3 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 4 3V66 MHz (3.3 V, 66 MHz)
– 2 3V48 MHz (3.3 V, 48 MHz)
Packaged in 56-Pin SSOP Package
description
The CDC930 is a differential clock synthesizer/
driver that generates HCLK/HCLK, 3VMREF/
3VMREF, PCI, 3V66, 3V48, REF system clock
signals to support a computer system with a
Pentium4 microprocessor and a Direct
Rambus memory subsystem.
DL PACKAGE
(TOP VIEW)
GND
REF0/MultSel0
REF1/MultSel1
VDD3.3V
XIN
XOUT
GND
PCI0
PCI1
VDD3.3V
PCI2
PCI3
GND
PCI4
PCI5
VDD3.3V
PCI6
PCI7
GND
PCI8
PCI9
VDD3.3V
SEL100/133
GND
3V48(0)/SelA
3V48(1)/SelB
VDD3.3V
PWRDWN
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
VDD3.3V
3VMREF
3VMREF
GND
SPREAD
HCLK(1)
HCLK(1)
VDD3.3V
HCLK(2)
HCLK(2)
GND
HCLK(3)
HCLK(3)
VDD3.3V
HCLK(4)
HCLK(4)
GND
I_REF
VDD3.3V
GND
VDD3.3V
3V66(0)
3V66(1)
GND
GND
3V66(2)
3V66(3)
VDD3.3V
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies
and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external
components. The host, PCI clock and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable
clock operation. All outputs have 3-state capability, which can be selected using control inputs SEL133, SelA
and SelB.
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. When PWRDWN is set to
high, the device operates in normal mode. When PWRDWN is set low, the device transitions to a power-down
mode in which HCLK is driven at 2×IREF, HCLK is not driven, and all others are set low.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†This is system design dependant.
Intel and Pentium4 are trademarks of Intel Corporation.
Rambus is a trademark of Rambus Corporation.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
description (continued)
The HOST bus operates at 100 MHz or 133 MHz. The MREF bus operates at 50 MHz or 66 MHz. Output
frequency selection is accomplished with corresponding setting for SEL100/133 control input. The PCI bus
frequency is fixed to 33 MHz.
Since the CDC930 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up as well as changes to SEL inputs. With use of external
reference clock, this signal must be fixed-frequency and fixed-phase prior stabilization time starts.
functional block diagram
3-State/Low
SEL100/133
23
Control
Logic
Test
SEL 100/133
2
SELB
XIN
XOUT
SPREAD
PWRDWN
26
5
6
2*REF
14.318 MHz
(2,3)
Latched
48 MHz
PLL
Xtal
Oscillator
Spread
Logic
52
CPU
PLL
/3
/2
/2
/2
28
180°
Phase
Shift
MultSel0
MultSel1
I_REF
2
Sync Logic and Power Down Logic
SELA
25
2*3V48
48 MHz
(25,26)
10*PCI
33 MHz
(8,9,11,12,14,
15,17,18,20,21)
4*3V66
66 MHz
(30,31,34,35)
1*3VMREF
50/66 MHz
(55)
1*3VMREF
50/66 MHz
(54)
2
3
Latched
2
4*HCLK
100/133 MHz
(42,45,48,51)
4*HCLK
100/133 MHz
(41,44,47,50)
39
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• DALLAS, TEXAS 75265
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
Terminal Functions
TERMINAL
NAME
3V48(0)/SelA
3V48(1)/SelB
I/O
DESCRIPTION
25
I/O
Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelA during power up
NO.
26
I/O
Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelB during power up
3V66[0–3]
30, 31, 34, 35
O
3.3 V, Type 5, 66-MHz clock outputs
3VMREF
55
O
3.3 V, Type 5, 50/66-MHz memory clock output
54
O
3.3 V, Type 5, 50/66-MHz memory clock output (180° out of phase with 3VMREF)
3VMREF
GND
1, 7, 13, 19,
24, 32, 33, 37,
40, 46, 53
HCLK[1–4]
42, 45, 48, 51
O
Type X1, host clock outputs
HCLK[1–4]
41, 44, 47, 50
O
Type X1, host complementary clock outputs
39
Special
8, 9, 11, 12,
14, 15, 17, 18,
20, 21
O
3.3 V, Type 5, 33-MHz PCI clock outputs
PWRDWN
28
I
Power down for complete device with HOST at 2×IREF, HCLK not driven and all other outputs
forced low.
REF0/MultSel0
2
I/O
Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel0 is latched
during power up. MultSel0 configures the IOH amplitude (and thus the VOH swing amplitude) of
the HCLK pair outputs.
REF1/MultSel1
3
I/O
Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel1 is latched
during power up. MultSel1 configures the IOH amplitude (and thus the VOH swing amplitude) of
the HCLK pair outputs.
SEL100/133
23
I
Active low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low=100
MHz, high=133 MHz
SPREAD
52
I
LVTTL level logic select. SPREAD pin enables/disables the spread spectrum for the
HCLK/HCLK, 3VMREF/3VMREF, 3V66 and PCI outputs.
VDD3.3V
4, 10, 16, 22,
27, 29, 36, 38,
43, 49, 56
I
3.3-V power for core and the HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66, and PCI outputs.
I_REF
PCI[0–9]
Ground for core and HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66 and PCI outputs
Current reference pin for the host clock pairs. I_REF uses a fixed precision resistor tied to ground
to establish the appropriate current.
XIN
5
I
Crystal input – 14.318 MHz
XOUT
6
O
Crystal output – 14.318 MHz
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• DALLAS, TEXAS 75265
3
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
Function Tables
SELECT FUNCTIONS
INPUTS
OUTPUTS
FUNCTION
SEL100/133
SelA
SelB
HOST, HCLK
3VMREF, 3VMREF
PCI
3V66
3V48
REF
0
0
0
100 MHz
50 MHz
33 MHz
66 MHz
48 MHz
14.318 MHz
0
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
0
133 MHz
66 MHz
33 MHz
66 MHz
48 MHz
14.318 MHz
1
1
1
TCLK/2
TCLK/4
TCLK/8
TCLK/4
TCLK/2
TCLK
PCI
3V66
Active 100 MHz
All outputs 3-stated
Active 133 MHz
Test Mode
ENABLE FUNCTION
OUTPUTS
INPUT
SEL100/133
HCLK
HCLK
0
2×IREF
On
Not driven
L
L
L
L
L
On
On
On
On
On
On
1
3VMREF, 3VMREF
3V48
REF
SPREAD SPECTRUM FUNCTION
OUTPUTS
INPUT
SPREAD
0
Spread spectrum clocking active, –0.6% at HCLK/HCLK, 3VMREF/3VMREF, 3V66, PCI
1
Spread spectrum clocking nonactive
OUTPUT BUFFER SPECIFICATIONS
BUFFER NAME
VDD RANGE
(V)
IMPEDANCE
(Ω)
BUFFER TYPE
3V48, REF
3.135 – 3.465
20–60
TYPE 3
PCI, 3V66
3.135 – 3.465
12–65
TYPE 5
3VMREF/3VMREF
3.135 – 3.465
12–55
HCLK/HCLK
TYPE 5
TYPE X1
OUTPUT BUFFER SPECIFICATIONS
INPUTS
MultSel0
MultSel1
BOARD TARGET
TRACE/TERM Z
REFERENCE R,
IREF = VDD/3×Rr)
OUTPUT CURRENT
VOH AT Z
IREF = 2.32 mA
0
0
60 Ω
Rr = 475 1%, IREF = 2.32 mA
0
50 Ω
0
1
60 Ω
Rr = 475 1%, IREF = 2.32 mA
Rr = 475 1%, IREF = 2.32 mA
IOH = 5×IREF
IOH = 5×IREF
0.71 V at 60 Ω
0
0
1
50 Ω
Rr = 475 1%, IREF = 2.32 mA
IOH = 6×IREF
IOH = 6×IREF
1
0
60 Ω
0
50 Ω
IOH = 4×IREF
IOH = 4×IREF
0.56 V at 60 Ω
1
Rr = 475 1%, IREF = 2.32 mA
Rr = 475 1%, IREF = 2.32 mA
1
1
60 Ω
1
50 Ω
IOH = 7×IREF
IOH = 7×IREF
0.99 V at 60 Ω
1
Rr = 475 1%, IREF = 2.32 mA
Rr = 475 1%, IREF = 2.32 mA
0.59 V at 50 Ω
0.85 V at 60 Ω
0.71 V at 50 Ω
0.47 V at 50 Ω
0.82 V at 50 Ω
NOTE: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Voltage range applied to any output in the high-impedance state or power-off state,
VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 × rated IOL
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
(VI < VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current , IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(VO < VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Maximum power dissipation at TA = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
which use a trace length of zero. The absolute maximum power dissipation allowed at TA = 55°C (in still air) is 1.3 W.
3. The maximum package power dissipation is calculated using a junction temperature of 1505C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DL
1558.6 mW
12.468 mW/°C
997.5 mW
810.52 mW
‡ This is the inverse of the traditional junction-to-case thermal resistance (RθJA) and uses a board-mounted device
at 74°C/W.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
recommended operating conditions (see Note 2)
MIN
Supply voltage, VDD
High-level input voltage, VIH
Low-level input voltage, VIL
Input voltage, VI
NOM†
MAX
UNIT
3.135
3.465
V
2
VDD +
0.3 V
V
GND –
0.3 V
0.8
V
VDD
–20
V
0
HCLK/HCLK
High level output current,
High-level
current IOH
3VMREF/3VMREF
–15
48MHz, REFx
–16
PCIx, 3V66x
–15
HCLK/HCLK
Low level output current
Low-level
current, IOL
5
3VMREF/3VMREF
10
48MHz, REFx
10
PCIx, 3V66x
Reference frequency, f(XIN)‡
Crystal frequency, f(XTAL)§
µA
mA
10
Test mode
Normal mode
mA
14
13.8
14.318
MHz
14.8
MHz
Operating free-air temperature, TA
0
85
°C
† All nominal values are measured at their respective nominal VDD values.
‡ Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven
externally up to f(XIN) = 16 MHz. If XIN is driven externally, XOUT is floating.
§ This is a series fundamental crystal with fO = 14.31818 MHz.
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
5. VIH, VIL: All input levels referenced to VDD = 3.30 V.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
RI
IIH
IIL
TEST CONDITIONS
Input clamp voltage
Input resistance
High-level input current
Low level input current
Low-level
MIN
TYP†
MAX
UNIT
–1.2
V
XIN-XOUT
VDD = 3.135 V,
VDD = 3.465 V,
II = –18 mA
VI = VDD –0.5 V
XOUT
VDD = 3.135 V,
VI = VDD –0.5 V
50
mA
MultSel0, MultSel1,
SelA, SelB
VDD = 3.465 V,
VI = VDD
10
µA
SEL100/133
SPREAD, PWRDWN
VDD = 3.465 V,
VI = VDD
5
µA
XOUT
VDD = 3.135 V,
VO = 0 V
–5
mA
MultSel0, MultSel1,
SelA, SelB,
VDD = 3.465 V,
VI = GND
–10
µA
SEL100/133
SPREAD, PWRDWN
VDD = 3.465 V,
VI = GND
–5
µA
I_REF
VDD = 3.465 V,
Rr = 221
–5.5
mA
±10
µA
100
kΩ
IOZ
High-impedance-state output current
VDD = 3.465 V
SELA, SELB = H,
SEL100/133 H → L
VO = VDD or GND
PWRDWN = H
IDD(Z)
High-impedance-state supply current
VDD = 3.465 V
SELA, SELB = H,
SEL100/133 H → L
PWRDWN = H
40
mA
IDD(PD)
PWRDWN state supply current
VDD = 3.465 V,
PWRDWN = L
30
mA
250
mA
5
pF
IDD
Dynamic supply current
CI
Input capacitance‡
VDD = 3.465 V
PWRDWN = H,
HCLK = 133 MHz,
SSC = ON/OFF,
CL = MAX
Rref = 475 Ω,
IOUT = 6 × Iref
VI = VDD or GND
VDD = 3.3 V,
C(XTAL) Crystal terminal capacitance
VDD = 3.3 V,
VI = 0.3 V
† All typical values are measured at their respective nominal VDD values.
‡ These parameters are ensured by design and lab characterization, not 100% production tested.
Control SELx, PWRDWN, SPREAD threshold levels during FUNC w/c level tests.
CL = MAX = 5 pF, Rs = 33.2 Ω, Rp = 49.9 Ω at HCLK/HCLK (Type X1)
CL = MAX = 20 pF, RL = 500 Ω at 48 MHz, REF (Type 3)
CL = MAX = 30 pF, RL = 500 Ω at PCIx, 3V66, 3VMREF, 3VMREF (Type 5)
POST OFFICE BOX 655303
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2
18
pF
7
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
HCLK/HCLK (Type X1)
PARAMETER
IOH
TEST CONDITIONS
MIN
Ireff = 2
2.32
32 mA × 4
VDD = 3.135 V
VDD = 3.465 V
–8.1
Ireff = 2
2.32
32 mA × 5
VDD = 3.135 V
VDD = 3.465 V
–10.1
High level output current
High-level
32 mA × 6
Ireff = 2
2.32
VDD = 3.135 V
VDD = 3.465 V
Ireff = 2
2.32
32 mA × 7
VDD = 3.135 V
VDD = 3.465 V
TYP†
MAX
–10.5
VOH at Z = 50 Ω
–13.1
–12.1
–15.7
–14.1
–18.4
CO
Output capacitance‡
VO = VDD or GND
† All typical values are measured at their respective nominal VDD values.
‡ These parameters are ensured by design and lab characterization, not 100% production tested.
3.5
UNIT
mA
mA
mA
mA
pF
48MHz, REFx (Type 3), CL = 20 pF, RL = 500 Ω
PARAMETER
VOH
High-level
g
output voltage
g
VOL
Low level output voltage
Low-level
IOH
High-level output current
IOL
Low-level output current
TEST CONDITIONS
VDD = min to max,
IOH = – 1 mA
VDD = 3.135 V,
VDD = min to max,
IOH = –14 mA
IOL = 1 mA
VDD = 3.135 V,
VDD = 3.135 V,
IOL = 9 mA
VO = 1 V
VDD = 3.3 V,
VDD = 3.465 V,
VO = 1.65 V
VO = 3.135 V
VDD = 3.135 V,
VDD = 3.3 V,
VO = 1.95 V
VO = 1.65 V
VDD = 3.465 V,
VO = 0.4 V
CO
Output capacitance‡
VDD = 3.3 V,
VO = VDD or GND
† All typical values are measured at their respective nominal VDD values.
‡ These parameters are ensured by design and lab characterization, not 100% production tested.
MIN
TYP†
MAX
VDD –
0.1 V
UNIT
V
2.4
0.1
0.4
V
–29
mA
–41
–23
29
mA
53
27
2
5
pF
PCIx, 3V66x, MREF/MREF (Type 5), CL = 20 pF, RL = 500 Ω
PARAMETER
VOH
g
g
High-level
output voltage
VOL
Low level output voltage
Low-level
IOH
High-level output current
IOL
Low-level output current
TEST CONDITIONS
VDD = min to max,
IOH = – 1 mA
VDD = 3.135 V,
VDD = min to max,
IOH = –18 mA
IOL = 1 mA
VDD = 3.135 V,
VDD = 3.135 V,
IOL = 12 mA
VO = 1 V
VDD = 3.3 V,
VDD = 3.465 V,
VO = 1.65 V
VO = 3.135 V
VDD = 3.135 V,
VDD = 3.3 V,
VDD = 3.465 V,
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
VO = VDD or GND
CO
Output capacitance‡
VDD = 3.3 V,
† All typical values are measured at their respective nominal VDD values.
‡ These parameters are ensured by design and lab characterization, not 100% production tested.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP†
MAX
VDD –
0.1 V
UNIT
V
2.4
0.1
0.4
V
–33
mA
–53
–33
30
mA
70
38
2
5
pF
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
switching characteristics, VDD = MIN to MAX, TA = 0°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Overshoot‡
Undershoot‡
HCLK/HCLK 0.7 V amplitude
vunder
Overshoot‡
Undershoot‡
Other clocks,, CL = Worst
case
tPZL
Output enable time to low
level
100
ns
tPZH
Output enable time to high
level
f(HCL) = 100 or 133 MHz,
SELA,, SELB = H,,
SEL100/133 L → H,
Rref = 475 Ω
100
ns
f(HCL) = 100 or 133 MHz,
SELA,, SELB = H,,
SEL100/133 H → L,
Rref = 475 Ω
10
ns
10
ns
f(HCL) = 100 or 133 MHz,
SELA,, SELB = H,,
SEL100/133 L → H,
Rref = 475 Ω
10
ns
10
ns
f(HCL) = 100 or 133 MHz,
SELA,, SELB = H,,
SEL100/133 H → L,
Rref = 475 Ω
10
ns
10
ns
vover
vunder
vover
tPHZ
Output disable time from
high level
tPLZ
Output disable time from low
level
tPZL
Output enable time to low
level
tPZH
Output enable time to high
level
tPHZ
Output disable time from
high level
tPLZ
Output disable time from low
level
SEL100/133
SEL100/133
HCLK/
HCLK
REF, 3V48
3VMREF,,
3VMREF,
3V66, PCI
VOH+200
VOL–200
GND–0.7
VDD+0.7
mV
V
tstab
Stabilization time†
After power up
3
ms
† Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present a XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.
‡ These parameters are ensured by design and lab characterization, not 100% production tested.
HCLK/HCLK (Type X1) CL = 2 pF, RL > 500 kΩ
PARAMETER
tc
HCLK clock period†
tjit(cc)
Cycle to cycle jitter
tdc
Duty cycle
tsk(o)
HCLK bus skew
tw
Pulse duration width
tr
tf
Rise time‡
tr, tf
Rise and fall time matching‡
vcross
Fall time‡
Cross point voltages‡
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
f(HCLK) = 100 MHz
f(HCLK) = 133 MHz
f(HCLK = 100 or 133 MHz
f(HCLK) = 100 or 133 MHz crossing
point
HCLKx
HCLKx
MIN
TYP
MAX
10
10.2
7.5
7.65
200
45%
f(HCLK) = 100 or 133 MHz crossing
point
UNIT
ns
ps
55%
150
ps
f(HCLK = 100 MHz
f(HCLK = 133 MHz
4.41
VO = 0.14 V to 0.56 V
VO = 0.14 V to 0.56 V
175
700
ps
0.7
0
7V
am
litude
amplitude
175
700
ps
0.7 V
amplitude
f(HCLK) = 100 or 133 MHz
HCLK and HCLK
ns
3.29
2 × (tr – tf)/(tr + tf)
20%
40%
VOH
55%
VOH
V
† The average over any 1–µs period of time is greater than the minimum specified period.
‡ These parameters are ensured by design and lab characterization, not 100% production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued)
3VMREF/3VMREF (Type 5) CL = 30 pF, RL = 500 Ω
PARAMETER
tc
FROM
(INPUT)
TO
(OUTPUT)
f(3VMREF/3VMREF) = 50 MHz
f(3VMREF/3VMREF) = 66 MHz
3VMREF/3VMREF clock
period†
tjit(cc)
Cycle to cycle jitter
tdc
Duty cycle
TEST CONDITIONS
f(3VMREF/3VMREF) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3VMREF/3VMREF) = 66 MHz
tsk(o)
3VMREF/3VMREF output
skew
3VMREF/
3VMREF
3VMREF/
3VMREF
t(off)
3VMREF/3VMREF clock
to PCI offset
3VMREF/
3VMREF
PCIx
MIN
TYP
MAX
UNIT
20
20.4
ns
15
15.3
ns
250
ps
45%
55%
f(3VMREF/3VMREF) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3VMREF/3VMREF) = 66 MHz,
Measured points at 1.5 V,
Measured at rising edges
tr
Rise time
VO = 0.4 V to 2.4 V
tf
Fall time
VO = 0.4 V to 2.4 V
† The average over any 1–µs period of time is greater than the minimum specified period.
250
ps
3
ns
0.5
2
ns
0.5
2
ns
3V66 (Type 5, No SSC), CL = 30 pF, RL = 500 Ω
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tc
3V66 clock period†
tjit(cc)
Cycle to cycle jitter
tdc
Duty cycle
tsk(o)
3V66 output skew
3V66x
3V66x
t(off)
3V66 clock to PCI
3V66x
PCIx
TEST CONDITIONS
MIN
f(3V66)= 66 MHz
f(3V66) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3V66) = 66 MHz
f(3V66) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3V66) = 66 MHz,
Measured points at 1.5 V,
Measured at rising edges
tr
Rise time
VO = 0.4 V to 2.4 V
tf
Fall time
VO = 0.4 V to 2.4 V
† The average over any 1–µs period of time is greater than the minimum specified period.
TYP
MAX
15.03
ns
300
45%
UNIT
ps
55%
250
ps
1.5
3.5
ns
0.5
2
ns
0.5
2
ns
PCI (Type 5), CL = 30 pF, RL = 500 Ω
PARAMETER
tc
tjit(cc)
PCI clock period†
tdc
tsk(o)
Duty cycle
FROM
(INPUT)
TO
(OUTPUT)
PCIx
PCIx
f(PCI) = 33.3 MHz
f(PCI) = 33.3 MHz
tr
Rise time
VO = 0.4 V to 2.4 V
tf
Fall time
VO = 0.4 V to 2.4 V
† The average over any 1–µs period of time is greater than the minimum specified period.
10
MIN
f(PCI)= 33.3 MHz
f(HCLK) = 100 or 133 MHz
Cycle to cycle jitter
PCI output skew
TEST CONDITIONS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
MAX
30.06
ns
500
45%
UNIT
ps
55%
500
ps
0.5
2
ns
0.5
2
ns
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued)
3V48 (Type 3), CL = 20 pF, RL = 500 Ω
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tc
3V48 clock period†
tjit(cc)
Cycle to cycle jitter
tdc
Duty cycle
tsk(o)
3V48 output skew
3V48x
3V48x
t(off)
3V48 clock to PCI
3V48x
PCIx
TEST CONDITIONS
MIN
f(3V48)= 48 MHz
f(3V48) = 48 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3V48) = 48 MHz
f(3V48) = 48 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3V48) = 48 MHz,
Measured points at 1.5 V,
Measured at rising edges
tr
Rise time
VO = 0.4 V to 2.4 V
tf
Fall time
VO = 0.4 V to 2.4 V
† The average over any 1–µs period of time is greater than the minimum specified period.
TYP
MAX
15.03
ns
350
45%
UNIT
ps
55%
250
ps
1.5
3.5
ns
1
4
ns
1
4
ns
REF (Type 3), CL = 20 pF, RL = 500 Ω
PARAMETER
tc
tjit(cc)
REF clock period†
tdc
tr
Duty cycle
Cycle to cycle jitter
Rise time
TEST CONDITIONS
MIN
f(REF)= 14.318 MHz
f(HCLK) = 100 or 133 MHz
MAX
69.84
tf
Fall time
VO = 0.4 V to 2.4 V
† The average over any 1–µs period of time is greater than the minimum specified period.
• DALLAS, TEXAS 75265
UNIT
ns
1
f(REF) = 14.318 MHz
VO = 0.4 V to 2.4 V
POST OFFICE BOX 655303
TYP
ps
52%
62%
1
4
ns
1
4
ns
11
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 500 Ω
From Output
Under Test
CL
(see Note A)
Vref(O)
OPEN
GND
S1
RL = 500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vref(OFF)
GND
LOAD CIRCUIT of single-ended outputs for tpd and tsk
ÎÎ
tw
From Output
Under Test
Test
Point
3V
Vref(IH)
Vref(T)
0V
Vref(IL)
Input
CL
(see Note A)
VOLTAGE WAVEFORMS
LOAD CIRCUIT of single-ended outputs for tr and tf
3V
Input
Vref(T)
Vref(T)
0V
tPLH
Output
Output
Enable
(high-level
enabling)
VDD
Vref(T)
0V
tPZL
tPHL
tPLZ
VOH
Vref(IH)
Vref(T)
Vref(IL)
VOL
tf
tr
Vref(T)
≈3 V
Output
Waveform 1
S1 at 6 V
(see Note B)
Vref(T)
tPZH
tw(L)
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
tw(H)
VOL + 0.3 V
VOH – 0.3 V
VOH
Vref(T)
≈0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. CL = 2 pF (HCLK, HCLK), CL = 20 pF (48MHZ, REF), CL = 30 pF (PCIx, 3VMREF, 3V66).
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
14.318 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
v
PARAMETER
3.3-V INTERFACE
2.5-V INTERFACE
UNIT
Vref(IH)
High-level reference voltage
2.4
2
V
Vref(IL)
Low-level reference voltage
0.4
0.4
V
Vref(T)
Input threshold reference voltage
1.5
1.25
V
Vref(OFF)
Off-state reference voltage
6
4.6
V
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
VT_REF
PCIx, 3V48x, 3V66x
tc
VT_REF
PCIx, 3V48x, 3V66x
tsk(o)
t(low)
t dc
+
t
t(high)
(low or high)
100
tc
t
c
HCLKx
HCLKx
tW
HCLKx
HCLKx
t
sk(o)
t
t
dc
=
W
t
x 100
c
3V66
VT_REF
VT_REF
PCIx
t(off) [3V66 to PCIx]
PARAMETER
VT_REF
3.3-V INTERFACE
UNIT
1.5
V
Input threshold reference voltage
Figure 2. Waveforms for Calculation of Output Skew, Duty Cycle, and Offset
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
HCLK
HCLK
t c (n)
t
t
jit(cc)
= t
c(n)
– t
c (n+1)
c(n+1)
VT_REF
t c(n)
t c(n+1)
t jit(cc) = t c(n) – t c(n+1)
PARAMETER
VT_REF
3.3-V INTERFACE
UNIT
1.5
V
Input threshold reference voltage
Figure 3. Waveforms for Calculation of Cycle-Cycle Jitter
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
0 ns
50 ns
100 ns
150 ns
200 ns
PWRDWN
HOST 100 MHz
HOST 100 MHz
3VMREF
3VMREF
3V66 MHz
PCI 33MHz
3V48 MHz
REF 14.318 MHz
Figure 4. Power DOWN Timing
VDD
RS1 = 33 Ω
HCLK
TLA
Clock
MultSel0
CDC930
MultiSel1
RS1 = 33 Ω
RIREF = 475 Ω
Clock
TLB
HCLK
RT1 = 49.9 Ω
RT1 = 49.9 Ω
CL = 2 pF
CL = 2 pF
NOTE A: Z(TLA) = Z(TLB) = 50 Ω, L(TLA) = L(TLB) = 3.5’’, CL represents probe and jig capacitance.
Figure 5. Load Circuit for 0.7 V Amplitude HCLK/HCLK Bus
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
MECHANICAL DATA
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48-PIN SHOWN
0.025 (0,635)
0.012 (0,305)
0.008 (0,203)
48
0.005 (0,13) M
25
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°– 8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / D 08/97
NOTES: A.
B.
C.
D.
16
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
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