CDCDLP223PW

CDCDLP223 www.ti.com SCAS836 – DECEMBER 2006 3.3 V Clock Synthesizer for DLP™ Systems FEATURES • • • • • • • • • • • • • High-Performance Clock Synthesizer Uses a 20 MHz Crystal Input to Generate Multiple Output Frequencies Integrated Load Capacitance for 20 MHz Oscillator Reducing System Cost All PLL Loop Filter Components are Integrated Generates the Following Clocks: – REF CLK 20 MHz (Buffered) – XCG CLK 100 MHz With SSC – DMD CLK 200-400 MHz With Selectable SSC Very Low Period Jitter Characteristic: – ±100 ps at 20 MHz Output – ±75 ps at 100 MHz and 200–400 MHz Outputs Includes Spread-Spectrum Clocking (SSC), With Down Spread for 100 MHz and Center Spread for 200–400 MHz HCLK Differential Outputs for the 100 MHz and the 200–400 MHz Clock Operates From Single 3.3-V Supply Packaged in TSSOP20 Characterized for the Industrial Temperature Range -40°C to 85°C ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-C) – MIL-STD-883, Method 3015 TYPICAL APPLICATIONS • Central Clock Generator for DLP™ Systems DESCRIPTION The CDCDLP223 is a PLL-based high performance clock synthesizer that is optimized for use in DLP™ systems. It uses a 20 MHz crystal to generate the fundamental frequency and derives the frequencies for the 100 MHz HCLK and the 300 MHz HCLK output. Further, the CDCDLP223 generates a buffered copy of the 20 MHz Crystal Oscillator Frequency at the 20 MHz output terminal. CDCDLP223 PIN ASSIGNMENTS XIN 1 XOUT TSSOP 20 20 IREF 2 19 VDD VSS 3 18 100MHZ VDD 4 17 100MHZ 20MHZ 5 16 VSS VSS 6 15 VSS EN 7 14 300MHZ IDO 8 13 300MHZ SDATA 9 12 VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which reduces Electro Magnetic Interference (EMI), is applied in the default configuration. The spread-spectrum clocking (SSC) is turned on and off via the serial control interface. The 300 MHz HCLK output provides a 200-400 MHz clock signal for the DMD Control Logic of the DLP™ Control ASIC. Frequency selection in 20 MHz steps is possible via the serial control interface. Spread-spectrum clocking with ±1.0% or ±1.5% center spread is applied, which can be disabled via the serial control interface The CDCDLP223 features a fail safe start-up circuit, which enables the PLLs only if a sufficient supply voltage is applied and a stable oscillation is delivered from the crystal oscillator. After the crystal start-up time and the PLL stabilization time, all outputs are ready for use. The CDCDLP223 works from a single 3.3-V supply and is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated CDCDLP223 www.ti.com SCAS836 – DECEMBER 2006 FUNCTIONAL BLOCK DIAGRAM XOUT 20 Mhz Crystal Oscillator 20 Mhz XIN LVTTL 100 Mhz SSC PLL 1 OUT = 100 Mhz –0.5% SSC HCLK out VDD 300 Mhz SSC PLL 2 OUT = 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN TERMINAL 1 I Crystal oscillator input for 20-MHz crystal in parallel resonance XOUT 2 O Crystal oscillator output for 20-MHz crystal in parallel resonance SDATA 9 I/O Open drain Data I/O, 2-wire serial interface controller, internal 1-MΩ pullup SCLK 10 20 MHz 5 O LVTTL Clock output, 20 MHz (buffered output from crystal oscillator) 100 MHz 18 O HCLK Clock output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 MHz 14 O HCLK Clock output for DMD system Clock output for DMD system 300 MHz DESCRIPTION I Interface Clock Clock input, 2-wire serial interface controller, internal 1-MΩ pullup 13 O HCLK VDD 4,11,19 Power 3.3 V Power supply VSS 3,6,12,15,16 Ground Ground IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200–400 MHz outputs, 150 kΩ pullup, default = logic high IDO 8 I LVTTL Sets 2-wire serial interface ID address bit A0, 150 kΩ pull-up resistor, default = logic high O RREF to GND IREF pin for HCLK output drive-current biasing Table 1. EN Pin (20 MHz, 100 MHz and 300 MHz Clocks) EN PIN 2 DESCRIPTION 1 All HCLK outputs, and 20-MHz outputs enabled, detailed device configurations are determined by 2-wire serial interface settings. 0 All HCLK = true Hi-Z, both PLLs are powered down and 20-MHz output in Hi-Z and Crystal Oscillator disabled, EN overrides 2-wire serial interface settings. Submit Documentation Feedback CDCDLP223 www.ti.com SCAS836 – DECEMBER 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VDD Supply voltage range –0.5 to 4.6 V VI Input voltage range (2) –0.5 to VDD + 0.5 V VO Output voltage range (2) Input current (VI < 0, VI > VDD) –0.5 to VDD + 0.5 V ±20 mA IO Continuous output current ±17.5 mA Tstg Storage temperature range –65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. PACKAGE THERMAL IMPEDANCE FOR TSSOP20 PACKAGE (1) (1) Airflow (lfm) θJA (°C/W) θJC (°C/W) θJB (°C/W) ΨJT (°C/W) 0 83.0 32 54 0.25 150 77.9 – – 250 75.4 – – 500 71.4 – – The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT 85 °C 3.6 V 0.7 × VDD VDD V –0.15 0.3 × VDD V 0.8 V TA Operating free-air temperature -40 VDD Supply voltage 3.0 VIH High level input voltage SDATA and SCLK 3.3 VIL Low level input voltage SDATA and SCLK VIL Low level input voltage LVTTL VI thresh Input Voltage threshold LVTTL VIH High level input voltage LVTTL IOH High-level output current LVTTL IOL Low-level output current LVTTL IOH High-level output current HCLK/HCLK IOL Low-level output current HCLK/HCLK 0 mA tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 500 ms 1.40 V 2.0 V 0.05 –8 mA 8 mA –20 mA RECOMMENDED CRYSTAL SPECIFICATION (1) MIN fxtal Crystal input frequency (fundamental) ESR Effective series resistance Pdrive Maximum power handling (drive level) CL Load capacitance (1) NOM MAX 20 UNIT MHz 100 Ω µW 100 20 pF See DLP™ Control ASIC DDP2230 datasheet for additional requirements. Submit Documentation Feedback 3 CDCDLP223 www.ti.com SCAS836 – DECEMBER 2006 TIMING REQUIREMENTS (1) over recommended ranges of supply voltage, load and operating free air temperature PARAMETER MIN TYP MAX UNIT XIN, XOUT REQUIREMENTS Frequency of crystal attached to XIN, XOUT, with CL = 20 pF (2 × 40 pF) on-die capacitance fXIN 20 MHz 2 WIRE SERIAL INTERFACE REQUIREMENTS STANDARD MODE fSCLK SCLK frequency 0 th(START) START hold time (see Figure 1) 4.0 µs tw(SCLL) SCLK low-pulse duration (see Figure 1) 4.7 µs tw(SCLH) SCLK high-pulse duration (see Figure 1) 4.0 µs tsu(START) START setup time (see Figure 1) 4.7 µs th(SDATA) SDATA hold time (see Figure 1) tsu(SDATA) SDATA setup time (see Figure 1) tr(SDATA) SCLK / SDATA input rise time (see Figure 1) tf(SDATA) SCLK / SDATA input fall time (see Figure 1) tsu(STOP) STOP setup time (see Figure 1) 4.0 µs tBUS Bus free time 4.7 µs 0 100 3.45 250 kHz µs ns 1000 300 ns ns 2 WIRE SERIAL INTERFACE REQUIREMENTS FAST MODE fSCLK SCLK frequency th(START) START hold time (see Figure 1) 0.6 µs tw(SCLL) SCLK low-pulse duration (see Figure 1) 1.3 µs tw(SCLH) SCLK high-pulse duration (see Figure 1) 0.6 µs tsu(START) START setup time (see Figure 1) 0.6 th(SDATA) SDATA hold time (see Figure 1) tsu(DATA) SDATA setup time (see Figure 1) tr(SDATA) SCLK / SDATA input rise time (see Figure 1) 20 300 ns tf(SDATA) SCLK / SDATA input fall time (see Figure 1) 20 300 ns tsu(STOP) STOP setup time (see Figure 1) 0.6 µs tBUS Bus free time 1.3 µs (1) 4 0 0 400 µs 0.9 100 µs ns The CDCDLP223 2-wire serial interface in Send-Mode meets both I2C and SMBus set up time tsu and hold time th requirements. Submit Documentation Feedback kHz CDCDLP223 www.ti.com SCAS836 – DECEMBER 2006 APPLICATION INFORMATION Figure 1. Timing Diagram, Serial Control Interface 3.3V 20MHz SCLK SDATA IREF ID0 EN 100MHz 3.3V 2 Spread CDCD5704 CDCDLP223 320MHz 20MHz 2 ISET ID1 ID0 400MHz 2 Spread Spread No Spread X? Div by A XDR DRAM Clock Distribution DMD Control Logic PLL xN X? Div by B X? Div by C ClockA ClockB ClockC . . . DLPTM Processor Chip Figure 2. Typical CDCDLP223 Application Submit Documentation Feedback 5 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CDCDLP223PW PW TSSOP 20 70 530 10.2 3600 3.5 Pack Materials-Page 1 PACKAGE OUTLINE PW0020A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE A SEATING PLANE C 6.6 TYP 6.2 0.1 C PIN 1 INDEX AREA 18X 0.65 20 1 2X 5.85 6.6 6.4 NOTE 3 10 11 B 20X 4.5 4.3 NOTE 4 0.30 0.19 0.1 1.2 MAX C A B (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A A 20 TYPICAL 4220206/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT PW0020A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE SYMM 20X (1.5) (R0.05) TYP 1 20 20X (0.45) SYMM 18X (0.65) 11 10 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4220206/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0020A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 20X (1.5) SYMM (R0.05) TYP 1 20 20X (0.45) SYMM 18X (0.65) 10 11 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220206/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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