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CDCEL824
SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015
CDCEL824 Programmable 2-PLL Clock Synthesizer
1 Features
•
1
•
•
•
•
•
•
•
2 Applications
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2]: for example, Frequency Switching,
Output Enable, or Power Down
– Enables 0-PPM Clock Generation
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Settings
Flexible Input Clocking Concept
– External Crystal: 20 MHz to 30 MHz
– Single-Ended LVCMOS up to 130 MHz
Selectable Output Frequency up to 201 MHz
Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 80 ps)
1.8-V Device Power Supply
Temperature Range –40°C to 85°C
Packaged in TSSOP
Laser Distance Measurement Applications
3 Description
The CDCEL824 is a modular PLL-based low-cost,
high-performance, programmable clock synthesizer,
multiplier, and divider. It generates up to four output
clocks from a single input frequency. Each output can
be programmed in-system for any clock frequency up
to 201 MHz, using up to two independent
configurable PLLs.
The CDCEL824 has a separate output supply pins,
VDDOUT, which are 1.8 V.
The input accepts an external crystal or LVCMOS
clock signal. In case of a crystal input, an on-chip
load capacitor is adequate for most applications. The
value of the load capacitor is programmable from
0 pF to 20 pF.
Device Information(1)
PART NUMBER
CDCEL824
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Schematic
Ethernet PHY
CDCEL824
WiFi
25 MHz
USB Controller
FPGA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCEL824
SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
4
5
6
7
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
CLK_IN Timing Requirements ..................................
SDA/SCL Timing Requirements ..............................
EEPROM Specification .............................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2
9.3
9.4
9.5
9.6
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 12
Programming........................................................... 13
Register Maps ......................................................... 15
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application ............................................... 22
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 25
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2015) to Revision A
Page
•
Changed custom to catalog data sheet ................................................................................................................................. 1
•
Changed order of pin function rows to be by number per format rules ................................................................................. 3
•
Changed Thermal Information table format; move EEPROM Spec table per format rules ................................................... 5
5 Description (continued)
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth,
Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for
example.
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It
is preset to a factory default configuration and can be reprogrammed to a different application configuration
before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable
through the SDA/SCL bus, a 2-wire serial interface.
Three free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or other
control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so
forth.
The CDCx824 operates in a 1.8-V environment in a temperature range of –40°C to 85°C.
2
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SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015
6 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
Xin/Clk
S0
Vdd
Vctr
GND
Vddout
Y3
Y4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Xout
S1/SDA
S2/SCL
DNC
GND
Y1
Y2
Vddout
Pin Functions
PIN
NUMBER
NAME
I/O
DESCRIPTION
1
Xin/CLK
I
Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus).
2
S0
I
User-programmable control input S0; LVCMOS inputs; internal pullup.
3
VDD
Power
4
VCtrl
I
5, 12
GND
Ground
Ground
6, 9
1.8-V supply for all outputs
1.8-V power supply for the device
VCXO control voltage (leave open or pull up when not used).
VDDOUT
Power
7
Y3
O
LVCMOS outputs
8
Y4
O
LVCMOS outputs
10
Y2
O
LVCMOS outputs
11
Y1
O
LVCMOS outputs
13
DNC
O
Reserved pin, do not connect
14
SCL/S2
I
SCL: Serial clock input (default configuration), LVCMOS; internal pullup.
S2: User-programmable control input; LVCMOS inputs; internal pullup.
15
SDA/S1
I/O or I
16
Xout
O
SDA: Bidirectional serial data input/output (default configuration), LVCMOS; internal pullup
S1: User-programmable control input; LVCMOS inputs; internal pullup.
Crystal oscillator output (leave open or pull up when not used).
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage range
(2) (3)
MIN
MAX
UNIT
–0.5
2.5
V
–0.5
VDD + 0.5
V
–0.5
VDD + 0.5
V
20
mA
VI
Input voltage range
VO
Output voltage range (2)
II
Input current (VI < 0, VI > VDD)
IO
Continuous output current
50
mA
TJ
Maximum junction temperature
125
°C
Tstg
Storage temperature range
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
VDD
Device supply voltage
1.7
1.8
1.9
V
VDDOUT
Output Yx supply voltage for CDCEL824
1.7
1.9
V
VIL
Low-level input voltage LVCMOS
0.3 VDD
V
VIH
High-level input voltage LVCMOS
VI(thresh)
Input voltage threshold LVCMOS
0.7 VDD
UNIT
V
0.5 VDD
V
Input voltage range S0
0
1.9
Input voltage range S1, S2, SDA, SCL; V(Ithresh) = 0.5 VDD
0
3.6
VI(CLK)
Input voltage range CLK
0
1.9
V
IOH /IOL
Output current (VDDOUT = 1.8 V)
±8
mA
CL
Output load LVCMOS
15
pF
TA
Operating free-air temperature
85
°C
30
MHz
VI(S)
–40
V
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1)
fXtal
Crystal input frequency range (fundamental mode)
ESR
Effective series resistance
fPR
Pulling range (0 V ≤ VCtrl ≤ 1.8 V) (2)
VCtrl
Frequency control voltage
C0/C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
4
10
100
±120
0
±150
Ω
ppm
VDD
V
220
0
20
pF
For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).
Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in the application report (SCAA085).
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7.4 Thermal Information
CDCEL824
AIRFLOW
(lfm)
THERMAL METRIC (1) (2)
PW (TSSOP)
UNIT
30 PINS
RθJA
Junction-to-ambient thermal resistance
0
101
°C/W
150
85
°C/W
200
84
°C/W
250
82
°C/W
500
74
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42
°C/W
RθJB
Junction-to-board thermal resistance
58
°C/W
ψJB
Junction-to-board characterization parameter
64
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
OVERALL PARAMETER
All PLLS on
IDD
Supply current (see Figure 1)
All outputs off, fCLK = 27 MHz,
fVCO = 135 MHz; fOUT = 27 MHz
IDDOUT
Supply current (see Figure 2)
No load, all outputs on,
fOUT = 27 MHz
VDDOUT = 1.8 V
IDDPD
Power-down current. Every circuit
powered down except SDA/SCL
fIN = 0 MHz,
VDD = 1.9 V
VPUC
Supply voltage VDD threshold for powerup control circuit
fVCO
VCO frequency range of PLL
fOUT
LVCMOS output frequency
20
Per PLL
VDDOUT = 1.8 V
mA
9
1
mA
μA
30
0.85
1.45
V
80
201
MHz
201
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V; IS = –18 mA
II
LVCMOS input current
VI = 0 V or VDD; VDD = 1.9 V
IIH
LVCMOS input current for S0/S1/S2
VI = VDD; VDD = 1.9 V
IIL
LVCMOS Input current for S0/S1/S2
VI = 0 V; VDD = 1.9 V
Input capacitance at Xin/Clk
VIClk = 0 V or VDD
6
Input capacitance at Xout
VIXout = 0 V or VDD
2
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
3
CI
–1.2
V
±5
μA
5
μA
–4
μA
pF
LVCMOS PARAMETER for VDDOUT = 1.8 V – MODE
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
VDDOUT = 1.7 V, IOH = –4 mA
1.4
VDDOUT = 1.7 V, IOH = –8 mA
1.1
V
VDDOUT = 1.7 V, IOL = 0.1 mA
0.1
VDDOUT = 1.7 V, IOL = 4 mA
0.3
VDDOUT = 1.7 V, IOL = 8 mA
0.6
tPLH, tPHL
Propagation delay
All PLL bypass
2.6
tr/tf
Rise and fall time
VDDOUT = 1.8 V (20%–80%)
0.7
1 PLL switching, Y1-to-Y2
80
110
2 PLL switching, Y1-to-Y4
130
200
1 PLL switching, Y1-to-Y2
100
130
2 PLL switching, Y1-to-Y4
150
220
(2) (3)
tjit(cc)
Cycle-to-cycle jitter
tjit(per)
Peak-to-peak period jitter
tsk(o)
Output skew (4)
odc
Output duty cycle (5)
(3)
ns
ns
fOUT = 50 MHz; Y1-to-Y2
50
fOUT = 50 MHz; Y1-to-Y4
110
fVCO = 100 MHz; Pdiv = 1
45%
V
ps
ps
ps
55%
SDA/SCL PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD; VDD = 1.9 V
±10
μA
VIH
SDA/SCL input high voltage (6)
VIL
SDA/SCL input low voltage (6)
VOL
SDA low-level output voltage
IOL = 3 mA VDD = 1.7 V
CI
SCL/SDA Input capacitance
VI = 0 V or VDD
(1)
(2)
(3)
(4)
(5)
(6)
6
0.7 VDD
V
0.3 VDD
3
V
0.2 VDD
V
10
pF
All typical values are at respective nominal VDD.
10,000 cycles
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input
frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,
data sampled on rising edge (tr).
odc depends on output rise- and fall time (tr/tf).
SDA and SCL pins are 3.3-V tolerant.
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7.6 CLK_IN Timing Requirements
over recommended ranges of supply voltage, load, and operating free-air temperature
MIN
NOM
MAX
PLL bypass mode
0
130
PLL mode
8
130
40%
60%
fCLK
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
dutyCLK
Duty cycle CLK at VDD / 2
UNIT
MHz
3
ns
7.7 SDA/SCL Timing Requirements
STANDARD MODE
(SeeFigure 5)
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
MIN
MAX
0
100
FAST MODE
MIN
MAX
0
400
UNIT
kHz
4.7
0.6
μs
4
0.6
μs
4.7
1.3
μs
SCL high-pulse duration
4
0.6
th(SDA)
SDA hold time (SDA valid after SCL low)
0
tsu(SDA)
SDA setup time
tr
SCL/SDA input rise time
1000
300
ns
tf
SCL/SDA input fall time
300
300
ns
tsu(STOP)
STOP setup time
tBUS
Bus free time between a STOP and START condition
3.45
μs
0
250
μs
0.9
100
ns
4
0.6
μs
4.7
1.3
μs
7.8 EEPROM Specification
EEcyc
Programming cycles of EEPROM
EEret
Data retention
MIN
TYP
100
1000
MAX
UNIT
cycles
10
years
7.9 Typical Characteristics
60
6
IDD - Supply Current (mA)
50
IDDOUT - Output Current (mA)
All PLL Off
1 PLL On
2 PLL On
40
30
20
10
0
10
50
90
130
f - Frequency (MHz)
170
200
All Outputs Off
1 Output On
3 Outputs On
5
4
3
2
1
0
10
50
D001
Figure 1. Supply Current vs PLL Frequency
90
130
fOUT - Output Frequency (MHz)
170
200
D002
Figure 2. Output Current vs Output Frequency
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8 Parameter Measurement Information
CDCEL824
1 kW
LVCMOS
1 kW
10 pF
Figure 3. Test Load
CDCEL824
LVCMOS
Typical Driver
Impedance
~ 32 W
LVCMOS
Series
Termination
~ 18 W
Line Impedance
Zo = 50 W
Figure 4. Test Load for 50-Ω Board Environment
8
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9 Detailed Description
9.1 Overview
The CDCEL824 is a modular PLL-based low-cost, high-performance, programmable clock synthesizer, multiplier,
and divider. It generates up to four output clocks from a single input frequency. Each output can be programmed
in-system for any clock frequency up to 201 MHz, using up to two independent configurable PLLs.
The CDCEL824 has a separate output supply pins, VDDOUT, which are 1.8 V.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth,
Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for
example.
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It
is preset to a factory default configuration and can be reprogrammed to a different application configuration
before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable
through the SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or other
control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so
forth.
The CDCx824 operates in a 1.8-V environment. It operates in a temperature range of –40°C to 85°C.
9.2 Functional Block Diagram
V DD
V DDOUT
GND
Vctr
Xin/CLK
Pdiv4
PLL 2
PLL Bypass
M2
Programming
and
SDA/SCL
Register
7-Bit
MUX2
S0
S1/SDA
S2/SCL
PLL Bypass
Y1
LV
CMOS
Y2
LV
CMOS
Y3
LV
CMOS
Y4
7-Bit
Pdiv3
EEPROM
LV
CMOS
M3
Xout
MUX1
Pdiv2
PLL 1
M4
XO
LVCMOS
M5
VCXO
7-Bit
Pdiv5
7-Bit
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9.3 Feature Description
9.3.1 Control Pins Settings
The CDCEL824 has three user-definable control pins (S0, S1, and S2) which allow external control of device
settings. They can be programmed to any of the following settings:
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power-down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Pin Definition
EXTERNAL
CONTROL
BITS
Control
function
PLL1 SETTING
PLL frequency
selection
Reserved
PLL2 SETTING
Output Y1/Y2
selection
PLL frequency
selection
RSVD SETTING
Output Y3/Y4
selection
Reserved
Reserved
Table 2. PLL Setting (Can Be Selected for Each PLL Individual) (1)
FREQUENCY SELECTION (2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION (3) (Y1 ... Y4)
(1)
(2)
(3)
YxYx
FUNCTION
0
State0
1
State1
Center/down-spread, Frequency0/1 and State0/1 are user-definable in the PLLx configuration register.
Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
high-impedance state, low, or active
SDA/S1 and SCL/S2 pins of the CDCEL824 are dual-function pins. In the default configuration, they are
predefined as the SDA/SCL serial programming interface. They can be programmed to control pins (S1/S2) by
setting the relevant bits in the EEPROM. Note that the changes of the bits in the control register (bit [6] of byte
02h) have no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin; it is a control pin only.
10
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9.3.2 SDA/SCL Serial Interface
This section describes the SDA/SCL interface of the CDCEL824 device. The CDCEL824 operates as a slave
device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I2C specification. It operates in
the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer (up to 400 kbit/s) and supports 7-bit
addressing.
The SDA/S1 and SCL/S2 pins of the CDCEL824 are dual-function pins. In the default configuration they are used
as SDA/SCL serial programming interface. They can be reprogrammed as general-purpose control pins, S1 and
S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].
P
S
Bit 7 (MSB)
tw(SCLH)
tw(SCLL)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tsu(STOP)
tf
tr
VIH
SDA
VIL
Figure 5. Timing Diagram for SDA/SCL Serial Control Interface
9.3.3 SDA/SCL Hardware Interface
Figure 6 shows how the CDCEL824 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple
devices can be connected to the bus, but the speed may need to be reduced (400 kHz is the maximum) if many
devices are connected.
Note that the pullup resistors (RP) depend on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at VOLmax =
0.4 V for the output stages (for more details see the SMBus or I2C Bus specification).
CDCEL824
RP
RP
Master
Slave
SDA
SCL
CBUS
CBUS
Figure 6. SDA/SCL Hardware Interface
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9.4 Device Functional Modes
9.4.1 Default Device Setting
The internal EEPROM of CDCEL824 is preconfigured as shown in Figure 7. The input frequency is passed
through the output as a default. This allows the device to operate in default mode without the extra production
step of programming it. The default setting appears after power is supplied or after a power-down/up sequence
until it is reprogrammed by the user to a different application configuration. A new register setting is programmed
via the serial SDA/SCL interface.
V DD
V DDOUT
GND
S0
0 = Outputs Disabled
(High-Impedance)
SDA
Programming Bus
SCL
EEPROM
Programming
and
SDA/SCL
Register
Pdiv3 = 1
PLL Bypass
PLL 2
Power Down
Y1 = 27 MHz
LV
CMOS
Y2 = 27 MHz
Pdiv4 = 1
LV
CMOS
Y3 = 27 MHz
LV
CMOS
Y4 = 27 MHz
MUX2
1 = Outputs Enabled
LV
CMOS
MUX1
Xout
Pdiv2 = 1
M2
PLL 1
Power Down
M3
Xtal
M4
27-MHz
Crystal
M5
Xin
Pdiv5 = 1
PLL Bypass
Figure 7. Preconfiguration of CDCEL824 Internal EEPROM
Table 3 shows the factory default setting for the control terminal register (external control pins). Note that even
though eight different register settings are possible, in default configuration, only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 are configured as programming pins in the default mode.
Table 3. Factory Default Settings for Control Terminal Register (1)
PLL1 SETTINGS
FREQUENCY
SELECTION
EXTERNAL CONTROL PINS
S2
(1)
12
S1
S0
PLL2 SETTINGS
OUTPUT
SELECTION
FREQUENCY
SELECTION
FS1
Y1Y2
FS2
Y2Y3
fVCO2_0
High-impedance
state
fVCO2_0
Enabled
SCL (I2C)
SDA (I2C)
0
fVCO1_0
High-impedance
state
SCL (I2C)
SDA (I2C)
1
fVCO1_0
Enabled
OUTPUT
SELECTION
S1 is SDA and S2 is SCL in default mode or when programmed (SPICON bit 6 of register 2 set to 0). They do not have any control-pin
function but they are internally interpreted as if S1 = 0 and S2 = 0. S0, however, is a control pin which in the default mode switches all
outputs ON or OFF (as previously predefined).
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9.5 Programming
9.5.1 Data Protocol
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
bytes read out are defined by byte count in the generic configuration register. At the Block Read instruction, all
bytes defined in the byte count must be read out to finish the read cycle correctly.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.
If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write
cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read out
during the programming sequence (Byte Read or Block Read). The programming status can be monitored by
EEPIP, byte 01h–bit 6.
The offset of the indexed byte is encoded in the command code, as described in Table 4.
Table 4. Slave Receiver Address (7 Bits)
DEVICE
CDCEL824
(1)
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
1
1
0
0
1
0
0
1/0
Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to four devices connected
to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.
9.5.2 Command Code Definition
Table 5. Command Code Definition
BIT
7
(6:0)
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte offset for Byte Read, Block Read, Byte Write and Block Write operations.
9.5.3 Generic Programming Sequence
1
S
7
Slave Address
1
R/W
MSB
LSB
S
Start Condition
Sr
Repeated Start Condition
R/W
1
A
8
Data Byte
MSB
1
A
1
P
LSB
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
A
Acknowledge (ACK = 0 and NACK =1)
P
Stop Condition
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 8. Generic Programming Sequence
9.5.4 Byte Write Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
Figure 9. Byte Write Protocol
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9.5.5 Byte Read Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
Sr
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 10. Byte Read Protocol
9.5.6 Block Write Programming Sequence
1
S
(1)
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
8
Data Byte N-1
…
1
A
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and should not be overwritten.
Figure 11. Block Write Protocol
9.5.7 Block Read Programming Sequence
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 12. Block Read Protocol
14
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9.6 Register Maps
9.6.1 SDA/SCL Configuration Registers
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCEL824. All settings can be manually written into
the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software.
Table 6. SDA/SCL Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
TABLE
00h
Generic configuration register
Table 8
10h
PLL1 configuration register
Table 9
20h
PLL2 configuration register
Table 10
The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings then can
be selected by the external control pins, S0, S1, and S2. Table 7 explains the corresponding bit assignment
between the Control Terminal Register and the Configuration Registers.
Table 7. Configuration Register, External Control Terminals
PLL1 SETTINGS
EXTERNAL CONTROL PINS
PLL2 SETTINGS
OUTPUT
SELECTION
FREQUENCY
SELECTION
OUTPUT
SELECTION
S2
S1
S0
FS1
Y1Y2
FS2
Y3Y4
0
0
0
0
FS1_0
Y1Y2_0
FS2_0
Y3Y4_0
1
0
0
1
FS1_1
Y1Y2_1
FS2_1
Y3Y4_1
2
0
1
0
FS1_2
Y1Y2_2
FS2_2
Y3Y4_2
3
0
1
1
FS1_3
Y1Y2_3
FS2_3Reserved
Reserved
4
1
0
0
FS1_4
Y1Y2_4
FS2_4Reserved
Reserved
5
1
0
1
FS1_5
Y1Y2_5
FS2_5
Y3Y4_5
6
1
1
0
FS1_6
Y1Y2_6
FS2_6
Y3Y4_6
7
1
1
1
FS1_7
Y1Y2_7
FS2_7
Y3Y4_7
13h
15h
23h
25h
Address offset (1)
(1)
FREQUENCY
SELECTION
Address offset refers to the byte address in the configuration register in Table 8, Table 9, and Table 10.
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Table 8. Generic Configuration Register
OFFSET
00h
(1)
BIT
(2)
ACRONYM
DEFAULT
E_EL
0b
Device identification (read-only): 0 is CDCEL824 (1.8 V out)
6:4
RID
Xb
Revision identification number (read-only)
3:0
VID
1h
Vendor identification number (read-only)
7
–
0b
Reserved – always write 0
6
EEPIP
0b
5
EELOCK
0b
4
PWDN
0b
Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – Device active (all PLLs and all outputs are enabled)
1 – Device power down (all PLLs in power down and all outputs in high-impedance state)
3:2
INCLK
00b
Input clock selection:
1:0
SLAVE_ADR
00b
Address bits A0 and A1 of the slave receiver address
7
M1
0b
RSVD
Operation mode selection for pins 14/15 (6)
0 – Serial programming interface SDA (pin 15) and SCL (pin 14)
1 – Control pins S1 (pin 15) and S2 (pin 14)
6
SPICON
0b
5:4
RSVD
01b
3:2
RSVD
01b
1:0
RSVD
7:0
RSVD
7
Reserved
0b
6
Reserved
0b
5
Reserved
0b
4
Reserved
0b
3
Reserved
0b
2
Reserved
0b
1
Reserved
0b
02h
001h
04h
(1)
(2)
(3)
(4)
(5)
(6)
16
DESCRIPTION
7
01h
03h
(3)
EEPROM programming Status4: (4) (read-only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
Permanently lock EEPROM data (5)
0 – EEPROM is not locked
1 – EEPROM is permanently locked
00 – Xtal
01 – VCXO
10 – LVCMOS
0 – Input clock
RSVD
Reserved
RSVD
Reserved
RSVD
Reserved
1 – Reserved
1 – PLL1 clock
Writing data beyond 30h may affect device function.
All data transferred with the MSB first
Unless customer-specific setting
During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is completed. Data, however, can be read out during the
programming sequence (Byte Read or Block Read).
If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible. Data, however can still be written via the SDA/SCL bus
to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.
Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to
GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
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Table 8. Generic Configuration Register (continued)
OFFSET (1)
BIT (2)
ACRONYM
DEFAULT (3)
7:3
07h-0Fh
(7)
(8)
00h – 0 pF
01h – 1 pF
02h – 2 pF
:
14h to 1Fh – 20 pF
XCSEL
0Ah
0b
Reserved – do not write other than 0.
7:1
BCOUNT
30h
7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes must be read out to correctly finish the read
cycle.
0
EEWRITE
0b
Initiate EEPROM write cycle (8)
—
0h
Reserved – do not write other than 0
2:0
06h
DESCRIPTION
Crystal load-capacitor selection (7)
05h
0 – No EEPROM write cycle
1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)
The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to finely adjust CL by a few picofarads. The value of CL
can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance
has to be considered which always adds 1.5 pF (6 pF/2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see application report
SCAA085.
Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of
the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The EEWRITE bit must be reset to low after the programming is completed. The programming status can
be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
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Table 9. PLL1 Configuration Register
OFFSET (1)
BIT (2)
ACRONYM
DEFAULT (3)
10h
7:0
Reserved
00000000b
Reserved
11h
7:0
Reserved
00000000b
Reserved
12h
7:0
Reserved
00000000b
Reserved
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
PLL1 multiplexer:
0 – PLL1
1 – PLL1 bypass (PLL1 is in power down)
6
M2
1b
Output Y1 multiplexer:
0 – bypass
1 – Pdiv2
5:4
M3
10b
Output Y2 multiplexer:
00 –
01 –
10 –
11 –
bypass
Pdiv2-divider
Pdiv3-divider
Reserved
3:2
Y1Y2_ST1
11b
Y1, Y2-state0/1definition:
00 –
01 –
10 –
11 –
Y1/Y2
Y1/Y2
Y1/Y2
Y1/Y2
13h
14h
1:0
(1)
(2)
(3)
18
Y1Y2_ST0
01b
DESCRIPTION
FS1_x: PLL1 frequency selection(4)
0 – fVCO1_0 (predefined by PLL1_0 – multiplier/divider value)
1 – fVCO1_1 (predefined by PLL1_1 – multiplier/divider value)
disabled to high-impedance state (PLL1 is in power down)
disabled to high-impedance state (PLL1 on)
disabled to low (PLL1 on)
enabled (normal operation, PLL1 on)
Writing data beyond 30h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
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Table 9. PLL1 Configuration Register (continued)
OFFSET (1)
15h
16h
17h
18h
19h
1Ah
BIT (2)
ACRONYM
DEFAULT (3)
7
Y1Y2_7
0b
6
Y1Y2_6
0b
5
Y1Y2_5
0b
4
Y1Y2_4
0b
3
Y1Y2_3
0b
2
Y1Y2_2
0b
1
Y1Y2_1
1b
0
Y1Y2_0
0b
7
Reserved
0b
DESCRIPTION
(4)
Y1Y2_x output state selection
0 – state0 (predefined by Y1Y2_ST0)
1 – state1 (predefined by Y1Y2_ST1)
RSVD
Reserved
7-bit Y1-output-divider Pdiv2:
Pdiv2
01h
7
—
0b
6:0
Pdiv3
01h
7:0
PLL1_0N [11:4
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
fVCO1_0 range selection:
7:0
PLL1_1N [11:4]
7:4
PLL1_1N [3:0]
004h
PLL1_1 (4): 30-bit multiplier/divider value for frequency fVCO1_1
(for more information see the PLL Multiplier/Divider Definition paragraph)
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
Reserved – do not write others than 0
7-bit Y2-output-divider Pdiv3:
1Dh
1Eh
000h
PLL1_0 (4): 30-bit multiplier/divider value for frequency fVCO1_0
(for more information, see the PLL Multiplier/Divider Definition paragraph).
10h
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
000h
10h
1Fh
(4)
0 – Reset and in standby
1 to 127 – Divider value
004h
1Bh
1Ch
0 – Reset and in standby
1 to 127 – Divider value
6:0
fVCO1_1 range selection:
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
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Table 10. PLL2 Configuration Register
OFFSET (1)
BIT (2)
ACRONYM
DEFAULT (3)
20h
7:0
Reserved
0000000b
Reserved
21h
7:0
Reserved
0000000b
Reserved
22h
7:0
Reserved
0000000b
Reserved
23h
7
FS2_7
0b
6
FS2_6
0b
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
7
MUX2
1b
6
M4
1b
5:4
M5
10b
3:2
Y3Y4_ST1
11b
1:0
Y3Y4_ST0
01b
24h
(1)
(2)
(3)
20
DESCRIPTION
FS2_x: PLL2 frequency selection(4)
0 – fVCO2_0 (predefined by PLL2_0 – multiplier/divider value)
1 – fVCO2_1 (predefined by PLL2_1 – multiplier/divider value)
PLL2 multiplexer:
0 – PLL2
1 – PLL2 bypass (PLL2 is in power down)
Output Y3 multiplexer:
0 – Pdiv2
1 – Pdiv4
Output Y4 multiplexer:
00 –
01 –
10 –
11 –
Y3, Y4-State0/1definition:
00 – Y3/Y4 disabled to high-impedance state (PLL2 is in power down)
01 – Y3/Y4 disabled to high-impedance state (PLL2 on)
10–Y3/Y4 disabled to low (PLL2 on)
11 – Y3/Y4 enabled (normal operation, PLL2 on)
Pdiv2-divider
Pdiv4-divider
Pdiv5-divider
Reserved
Writing data beyond 30h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
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Table 10. PLL2 Configuration Register (continued)
OFFSET (1)
BIT (2)
ACRONYM
DEFAULT (3)
25h
7
Y3Y4_7
0b
6
Y3Y4_6
0b
5
Y3Y4_5
0b
4
Y3Y4_4
0b
3
Y3Y4_3
0b
2
Y3Y4_2
0b
1
Y3Y4_1
1b
0
Y3Y4_0
0b
7
Reserved
0b
6:0
Pdiv4
01h
7
—
0b
6:0
Pdiv5
01h
28h
7:0
PLL2_0N [11:4
29h
7:4
PLL2_0N [3:0]
3:0
PLL2_0R [8:5]
7:3
PLL2_0R[4:0]
2:0
PLL2_0Q [5:3]
7:5
PLL2_0Q [2:0]
4:2
PLL2_0P [2:0]
010b
1:0
VCO2_0_RANGE
00b
2Ch
7:0
PLL2_1N [11:4]
2Dh
7:4
PLL2_1N [3:0]
3:0
PLL2_1R [8:5]
7:3
PLL2_1R[4:0]
2:0
PLL2_1Q [5:3]
7:5
PLL2_1Q [2:0]
4:2
PLL2_1P [2:0]
010b
1:0
VCO2_1_RANGE
00b
26h
27h
2Ah
2Bh
004h
DESCRIPTION
(4)
Y3Y4_x output state selection
0 – state0 (predefined by Y3Y4_ST0)
1 – state1 (predefined by Y3Y4_ST1)
Reserved
0 – Down
1 – Center
7-Bit Y3-output-divider Pdiv4:
0 – Reset and in standby
1 to 127 – Divider value
Reserved – do not write others than 0
7-bit Y4-output-divider Pdiv5:
PLL2_0 (4): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see the PLL Multiplier/Divider Definition paragraph)
000h
10h
fVCO2_0 range selection:
2Eh
2Fh
004h
00 –
01 –
10 –
11 –
fVCO2_0 < 125 MHz
125 MHz ≤ fVCO2_0 < 150 MHz
150 MHz ≤ fVCO2_0 < 175 MHz
fVCO2_0 ≥ 175 MHz
PLL2_1 (4): 30-bit multiplier/divider value for frequency fVCO2_1
(for more information see the PLL Multiplier/Divider Definition paragraph)
000h
10h
fVCO2_1 range selection:
(4)
0 – Reset and in standby
1 to 127 – Divider value
00 –
01 –
10 –
11 –
fVCO2_1 < 125 MHz
125 MHz ≤ fVCO2_1 < 150 MHz
150 MHz ≤ fVCO2_1 < 175 MHz
fVCO2_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
CDCEL824 is an easy to use low-cost, programmable CMOS clock synthesizer. it can be used as a crystal
buffer, clock synthesizer with separate output supply pin. CDCEL824 features on-chip loop filter. Programming
can be done through SPI, pin-mode, or using on-chip EEPROM. This section shows some examples of using
CDCEL824 in various applications.
10.2 Typical Application
CDCEL824 is ideal clock generator for medium-range phase-shift laser distance meter. Having two separate
PLLs allows for achieving as low intermediate frequency as required as well as high maximum modulation
frequency, hence increasing the accuracy of the measurement device. Moreover, a fast settling PLL supports
faster switching between multiple modulation frequencies required by a single measurement. this results in
higher measurement rates for the device. Low power consumption and low cost position CDCEL824 as an ideal
device for commercial laser distance metering equipment.
Figure 13 shows a typical application concept for the CDCEL824, where the outputs of the PLL1, Y1 and Y2 are
used to generate the modulation and the counter frequency respectively. Y3 coming out of the PLL2 is carrying
the shifted modulation frequency for down mixing. all three frequencies are programmable and dynamically
switchable.
Laser
Diode
Example:
f0 :modulation freq. 200 MHz
fI :intermediate freq. 10 kHz
fC :counter frequency. 2 MHz
APD
Mixer
Y1
f0
Y3
f0-fI
fI
CDCEL824
Digital
Processor
fI
Y2
fC
Figure 13. Heterodyne Phase-Shift Laser Distance Meter Concept
22
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Typical Application (continued)
10.2.1 Design Requirements
For Laser distance meter applications, if heterodyne technique is used as mentioned in Typical Application , it is
shown that:
c
R =
2
fo
Maximum Measurement Range equals:
(1)
c fI 1
Dd =
2 fo fc
And best error achievable in measurement:
(2)
fI
That means lower RF frequency allows for longer range, while lower ratio fo ( higher RF frequency and lower IF
frequency) gives lower error.
The values of intermediate, RF, and counter frequency should be chosen according to design targets of the
maximum range and maximum tolerable error. Typically multiple consecutive measurements with multiple RF
frequencies are carried on to resolve the trade-off between the accuracy and the maximum range.
10.2.2 Detailed Design Procedure
10.2.2.1 PLL Multiplier/Divider Definition
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCEL824 can be calculated:
ƒ
N
ƒ OUT + IN
Pdiv M
where
•
•
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL
Pdiv (1 to 127) is the output divider.
(3)
The target VCO frequency (ƒVCO) of each PLL can be calculated:
N
ƒ VCO + ƒIN
M
(4)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
NP = 4 – int
ǒlog MN Ǔ [if P t 0 then P + 0] Q = int ǒNȀM Ǔ R = N′ – M × Q
2
where
N′ = N × 2P
N≥M
80 MHz ≤ ƒVCO ≤ 200 MHz
16 ≤ q ≤ 63
0≤p≤4
0 ≤ r ≤ 511
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N′’ = 4 × 2 = 16
→ N′’ = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
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Typical Application (continued)
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
10.2.3 Application Curves
1.625 MHz to 3.25 MHz
1.5 MHz to 2.5 MHz
Figure 14. Phase Noise and RMS Jitter
Figure 15. Phase Noise and RMS Jitter
11 Power Supply Recommendations
There is no restriction on the power-up sequence. In case VDDOUT is applied first, it is recommended to ground
VDD. In case VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT.
The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled
until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,
including the outputs. If there is a VDDOUT available before the VDD supply, the outputs will stay disabled until
the VDD supply has reached a certain level.
12 Layout
12.1 Layout Guidelines
When the CDCEL824 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the
VCXO. Therefore, care must be taken in placing the crystal units on the board. Crystals should be placed as
close to the device as possible, ensuring that the routing lines from the crystal terminals to XIN and XOUT have the
same length.
If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the
device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise
coupling.
Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For
example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can
range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an
internal 10 pF.
To minimize the inductive influence of the trace, it is recommended to place this small capacitor as close to the
device as possible and symmetrically with respect to XIN and XOUT.
Figure 16 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
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12.2 Layout Example
Figure 16. Board Layout
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13 Device and Documentation Support
13.1 Documentation Support
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
Pro-Clock, E2E are trademarks of Texas Instruments.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCEL824PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKEL824
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
