CDCL6010RGZT

CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer Check for Samples: CDCL6010 FEATURES • 1 • • 2 • • • • • • • • • • Single 1.8V Supply High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11 Outputs Low Output Jitter: 400fs RMS Output Group Phase Adjustment Low-Voltage Differential Signaling (LVDS) Input, 100Ω Differential On-Chip Termination, 30MHz to 319MHz Frequency Range Differential Current Mode Logic (CML) Outputs, 50Ω Single-Ended On-Chip Termination, 15MHz to 1.25GHz Frequency Range One Dedicated Differential CML Output, Straight PLL and Frequency Divider Bypass Two Groups of Five Outputs Each with Independent Frequency Division Ratios; Optional PLL Bypass Fully Integrated Voltage Controlled Oscillator (VCO); Supports Wide Output Frequency Range Output Frequency Derived From VCO Frequency with Divide Ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80 Meets OBSAI RP1 v1.0 Standard and CPRI v2.0 Requirements Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements • • • • • • Integrated LC Oscillator Allows External Bandwidth Adjustment PLL Lock Indication Power Consumption: 640mW Typical Output Enable Control for Each Output SDA/SCL Device Management Interface 48-pin QFN (RGZ) Package Industrial Temperature Range: –40°C to +85°C APPLICATIONS • • • Low Jitter Clocking for High-Speed SERDES Jitter Cleaning of SERDES Reference Clocks for 1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel, PCI Express, Serial ATA, SONET, CPRI, OBSAI, etc. Up to 1-to-11 Clock Buffering and Fan-out 1 Bypass CML Output PLL Differential LVDS Input 30MHz-319MHz DIVIDER 5 Differential CML Outputs 15MHz-1.25GHz DIVIDER 5 Differential CML Outputs 15MHz-1.25GHz VCO SDA/SCL 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2011, Texas Instruments Incorporated CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION The CDCL6010 is a high-performance, low phase noise clock multiplier, distributor, jitter cleaner, and low skew buffer. It effectively cleans a noisy system clock with a fully-integrated low noise Voltage Controlled Oscillator (VCO) that operates in the 1.2GHz–1.275GHz range. (Note that the LC oscillator oscillates in the 2.4GHz–2.55GHz range. The frequency is predivided by 2 before the post-dividers P0 and P1.) The output frequency (FOUT) is synchronized to the frequency of the input clock (FIN). The programmable pre-dividers, M and N, and the post-dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN × N/(M × P) Where: P (P0, P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80 M = 1, 2, 4, 8 N = 32, 40 provided that: 30MHz < (FIN /M) < 40MHz 1200MHz < (FOUT × P) < 1275MHz The PLL loop bandwidth is user-selectable by external filter components or by using the internal loop filter. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. The CDCL6010 supports one differential LVDS clock input and a total of 11 differential CML outputs. One output is a straight bypass with no support for jitter cleaning or clock multiplication. The remaining 10 outputs are available in two groups of five outputs each with independent frequency division ratios. Those 10 outputs can be optionally setup to bypass the PLL when no jitter cleaning is needed. The CML outputs are compatible with LVDS receivers if ac-coupled. With careful observation of the input voltage swing and common-mode voltage limits, the CDCL6010 can support a single-ended clock input as outlined in the Pin Description Table The CDCL6010 can operate as a multi-output clock buffer in a PLL bypass mode. All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only. The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (n) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (n) is the same as the post-divide ratio. The phase adjustment step (ΔΦ) in time units is given as: ΔΦ = 1/(n × FOUT) where FOUT is the respective output frequency. The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL6010 is available in a 48-pin QFN (RGZ) package. Table 1. AVAILABLE OPTIONS (1) (1) 2 TA PACKAGED DEVICES –40°C to +85°C CDCL6010RGZT 48-pin QFN (RGZ) Package, small tape and reel FEATURES –40°C to +85°C CDCL6010RGZR 48-pin QFN (RGZ) Package, tape and reel For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at www.ti.com. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted). (1) (2) VALUE UNIT VDD, AVDD Supply voltage –0.3 to 2.5 V VLVDS Voltage range at LVDS input pins (2) –0.3 to VDD + 0.6 V VI Voltage range at all non-LVDS input pins (2) –0.3 to VDD + 0.6 V ESD Electrostatic discharge (HBM) 2 kV TJ Junction temperature +125 °C TSTG Storage temperature range –65 to +150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX VDD Digital supply voltage 1.7 1.8 1.9 UNIT V AVDD Analog supply voltage 1.7 1.8 1.9 V TA Ambient temperature (no airflow, no heatsink) –40 +85 °C TJ Junction temperature +105 °C THERMAL INFORMATION RGZ (48 Pins) UNITS airflow = 0 lfm 28.3 °C/W airflow = 50 lfm THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance (2): 22.4 °C/W θJC(TOP) Junction-to-case (top) thermal resistance 20.5 °C/W θJC(BOTTOM) Junction-to-case (Bottom) thermal resistance 5.3 °C/W (1) (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. No heatsink; power uniformly distributed; 36 ground vias (6 x 6 array) tied to the thermal exposed pad; 4-layer high-K board. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD Total current from digital 1.8V supply All outputs enabled; VDD = VDD,typ 30.72MHz input; 61.44MHz output 270 mA IAVDD Total current from analog 1.8V supply All outputs enabled; AVDD = VDD,typ 30.72MHz input; 61.44MHz output 85 mA VIL,CMOS Low level CMOS input voltage VDD = 1.8V –0.2 0.6 VIH,CMOS High level CMOS input voltage VDD = 1.8V VDD – 0.6 VDD V IIL,CMOS Low level CMOS input current VDD = VDD,max, VIL = 0.0V –120 μA IIH,CMOS High level CMOS input current VDD = VDD,max, VIH = 1.9V 65 μA VOL,SDA Low level CMOS output voltage for the SDA pin Sink current = 3mA 0.2VDD V IOL,CMOS Low level CMOS output current 0 8 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 V mA 3 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com AC ELECTRICAL CHARACTERISTICS Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 132 Ω ZD,IN Differential input impedance for the LVDS input terminals VCM,IN Common-mode voltage, LVDS input 1375 mV VS,IN Single-ended LVDS input voltage swing 100 600 mVPP VD,IN Differential LVDS input voltage swing 200 1200 mVPP tR,OUT, tF,OUT Output signal rise/fall time VCM,OUT Common-mode voltage, CML outputs VDD –0.31 VDD –0.23 VDD –0.19 VS,OUT Single-ended CML output voltage swing ac-coupled 180 230 280 mVPP VD,OUT Differential CML output voltage swing Measured in a 50Ω scope; The CML output incorporates 50Ω resistors to VDD 360 460 560 mVPP FIN Clock input frequency 30 319 MHz FOUT Clock output frequency 15 1250 MHz LOUT Residual clock output phase noise JOUT Residual clock output jitter TP Input-to-output delay TSOUT Clock output skew DCycleOUT (1) 4 90 1125 1200 20%–80% 100 ps V FIN = 30.72MHz , FOUT = 61.44MHz 400kHz PLL bandwidth at 10Hz offset –103 dBc/Hz at 100Hz offset –114 dBc/Hz at 1kHz offset –123 dBc/Hz at 10kHz offset –121 dBc/Hz at 100kHz offset –119 dBc/Hz at 1MHz offset –138 dBc/Hz at 10MHz offset –152 dBc/Hz at 20MHz offset –152 dBc/Hz 10Hz–1MHz offset 2.01 ps RMS 1MHz–20MHz offset 0.45 ps RMS 12kHz–20MHz offset 2.11 ps RMS FIN = 30.72MHz, FOUT = 61.44MHz 400kHz PLL bandwidth FIN = 30.72MHz, FOUT = 30.72MHz YP[9:0] outputs, PLL bypass mode 3 ns FIN = 30.72MHz, FOUT = 61.44MHz YP[9:0] outputs, PLL mode 150 ps FIN = 30.72MHz, FOUT = 61.44MHz YP[9:0] outputs relative to YP[0] –64 64 ps FIN = 122.88MHz, FOUT (Y0 to Y4) = 61.44MHz, FOUT (Y5 to Y9) = 122.88MHz (Y0 to Y4) lag (Y5 to Y9) 1.46 2.52 ns 45% 55% Clock output duty cycle (1) Output duty cycle of the bypass output and for post-divide ratio = 1 is just as good as the input duty cycle. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com AC ELECTRICAL CHARACTERISTICS FOR THE SDA/SCL INTERFACE (1) PARAMETER MIN TYP MAX UNIT 400 kHz fSCL SCL frequency th(START) START hold time 0.6 μs tw(SCLL) SCL low-pulse duration 1.3 μs tw(SCLH) SCL high-pulse duration 0.6 μs tsu(START) START setup time 0.6 μs th(SDATA) SDA hold time 0 μs tsu(DATA) SDA setup time tr(SDATA) SCL / SDA input rise time 0.3 μs tf(SDATA) SCL / SDA input fall time 0.3 μs tsu(STOP) STOP setup time 0.6 μs tBUS Bus free time 1.3 μs (1) μs 0.6 See Figure 4 for the timing behavior. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 5 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com DEVICE INFORMATION VCN AVDD YP10 YN10 AVDD YP9 YN9 VDD YP8 YN8 VDD ADD1 48 47 46 45 44 43 42 41 40 39 38 37 48-PIN QFN (RGZ) (TOP VIEW) VCP 1 36 ADD0 AVDD 2 35 VDD CLKP 3 34 YN7 CLKN 4 33 YP7 AVDD 5 32 VDD YP0 6 31 YN6 30 YP6 CDCL6010 24 VDD SCL SDA 22 25 23 12 YN4 VSS 21 VDD YP4 26 20 11 VDD VDD 19 YP5 YN3 27 18 10 YP3 YN1 17 YN5 VDD 28 16 9 YN2 YP1 15 VDD YP2 29 14 8 VDD VDD 13 7 STATUS YN0 NOTE: Exposed thermal pad must be soldered to VSS. The CDCL6010 is available in a 48-pin QFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal pad serves both thermal and electrical grounding purposes. NOTE The device must be soldered to ground (VSS) using as many ground vias as possible. The device performance will be severely impacted if the exposed thermal pad is not grounded appropriately. 6 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com PIN FUNCTIONS PIN NAME PIN NO. TYPE VDD 8, 11, 14,17, 20, 23, 26, 29, 32, 35, 38, 41 Power 1.8V digital power supply. AVDD 2, 5, 44, 47 Power 1.8V analog power supply. VSS Exposed thermal pad and pin 12 Power Ground reference. VCP, VCN 1, 48 I External loop filter terminals. CLKP, CLKN 3, 4 I Differential LVDS input. Single-ended 1.8V input can be dc-coupled to pin 3 with pin 4 either tied to pin 3 (recommended) or left open. YP0, YN0 YP1, YN1 YP2, YN2 YP3, YN3 YP4, YN4 YP5, YN5 YP6, YN6 YP7, YN7 YP8, YN8 YP9, YN9 6, 7 9, 10 15, 16 18, 19 21, 22 27, 28 30, 31 33, 34 40, 39 43, 42 O 10 differential CML outputs with support for jitter cleaning and clock multiplication. Support optional PLL bypass mode when jitter cleaning is not needed. YP10, YN10 46, 45 O Differential CML output. Straight bypass with no jitter cleaning and no clock multiplication. SCL 24 I SCL serial clock pin. Open drain. Always connect to a pull-up resistor. SCL tolerated 1.8V on the input only. SDA 25 I/O SDA bidirectional serial data pin. Open drain. Always connect to a pull-up resistor. SDA tolerates 1.8V on the input only STATUS 13 O LVCMOS status signaling. High status indicates PLL lock. 37, 36 I Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed most significant bits (ADD[6:2]) of the 7-bit device address are 11010. ADD1, ADD0 DESCRIPTION Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 7 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM External Low-Pass Filter C2 R C1 AVDD VDD VCP VCN PLL Bypass YP10 CML YN10 CLKP LVDS Divider M PFD CP VCO ¸2 CLKN MUX Divider P1 YP[9:5] CML CML Divider N YN[9:5] I Internal LPF LPF MUX Divider P0 YP[4:0] CML CML YN[4:0] PLL Setting SDA/SCL SDA/SCL Control Control Post Divider Setting See Note 1 PLL_LOCK STATUS VSS (1) 8 Outputs can be disabled to floating. When outputs are left floating, internal 50Ω termination to VDD pulls both YN and YP to VDD. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS Typical operating conditions are at VDD = 1.8V and TA = +25°C, VD,IN = 200mVPP (unless otherwise noted). TRANSIENT PERFORMANCE: FIN = 30.72MHz, FOUT = 61.44MHz TRANSIENT PERFORMANCE: FIN = 250MHz, FOUT = 1.25GHz 250 300 Differential Output Voltage - mV Differential Output Voltage - mV 200 200 100 0 -100 -200 150 100 50 0 -50 -100 -150 -200 -300 0 -250 10 20 30 t - Time - ns 40 0 50 0.5 1 t - Time - ns Figure 1. 1.5 2 Figure 2. PHASE NOISE: FIN = 30.72MHz, FOUT = 61.44MHz -80 Phase Noise - dBc/Hz -90 -100 -110 -120 -130 -140 -150 -160 10 100 1k 10 k 100 k 1M Offset Frequency - Hz 10 M 100 M Figure 3. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 9 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com SDA/SCL INTERFACE This section describes the SDA/SCL interface of the CDCL6010 device. The CDCL6010 operates as a slave device of the industry standard 2-pin SDA/SCL bus. It operates in the fast-mode at a bit-rate of up to 400kbit/s and supports 7-bit addressing compatible with the popular two-pin serial interface standard. The device address is made up of the fixed internal address, 11010 (A6:A2), and configurable external pins ADD1 (A1) and ADD0 (A0). Four different devices with addresses 1101000, 1101001, 1101010 and 1101011, can be addressed via the same SDA/SCL bus interface. The least significant bit of the address byte designates a write or read operation. SDA/SCL Bus Slave Device Address A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 ADD1 ADD0 0/1 R/W Bit: 0 = Write to CDCL6010 device 1 = Read from CDCL6010 device Command Code Definition BIT DESCRIPTION C7 1 = Byte Write / Read or Word Write / Read operation (C6:C0) Byte Offset for Byte Write / Read and Word Write / Read operation. Command Code for Byte Write / Read Operation Hex Code C7 C6 C5 C4 C3 C2 C1 C0 Byte 0 80h 1 0 0 0 0 0 0 0 Byte 1 81h 1 0 0 0 0 0 0 1 Byte 2 82h 1 0 0 0 0 0 1 0 Byte 3 83h 1 0 0 0 0 0 1 1 Byte 4 84h 1 0 0 0 0 1 0 0 Byte 5 85h 1 0 0 0 0 1 0 1 Byte 6 86h 1 0 0 0 0 1 1 0 Byte 7 87h 1 0 0 0 0 1 1 1 Hex Code C7 C6 C5 C4 C3 C2 C1 C0 Word 0: Byte 0 and byte 1 80h 1 0 0 0 0 0 0 0 Word 1: Byte 1 and byte 2 81h 1 0 0 0 0 0 0 1 Word 2: Byte 2 and byte 3 82h 1 0 0 0 0 0 1 0 Word 3: Byte 3 and byte 4 83h 1 0 0 0 0 0 1 1 Word 4: Byte 4 and byte 5 84h 1 0 0 0 0 1 0 0 Word 5: Byte 5 and byte 6 85h 1 0 0 0 0 1 0 1 Word 6: Byte 6 and byte 7 86h 1 0 0 0 0 1 1 0 Word 7: Byte 7 87h 1 0 0 0 0 1 1 1 Command Code for Word Write / Read Operation 10 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com SDA/SCL Timing Characteristics S P tw(SCLL) Bit 6 Bit 7 (MSB) tw(SCLH) A Bit 0 (LSB) tr(SM) P tf(SM) VIH(SM) SCL VIL(SM) tSU(START) th(SDATA) tSU(SDATA) th(START) t(BUS) tSU(STOP) tf(SM) tr(SM) VIH(SM) SDA VIL(SM) Figure 4. Timing Diagram for the SDA/SCL Serial Control Interface SDA/SCL Programming Sequence LEGEND FOR PROGRAMMING SEQUENCE 1 7 S Slave Address 1 1 Wr A S Start condition Sr Repeated start condition Rd Read (bit value = 1) Wr Write (bit value = 0) A Acknowledge (bit value = 0) N Not acknowledge (bit value = 1) P Stop condition 8 Data Byte 1 1 A P Master to Slave transmission Slave to Master transmission Byte Write Programming Sequence: 1 7 1 1 8 1 8 1 1 S Slave Address Wr A Command Code A Data Byte A P Byte Read Programming Sequence: 1 S 7 Slave Address 1 Wr 1 8 1 1 7 1 1 8 1 1 A Command Code A S Slave Address Rd A Data Byte N P Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 11 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Word Write Programming Sequence: 1 7 1 1 8 1 8 1 8 1 1 S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A P Word Read Programming Sequence: 1 7 1 1 8 1 1 7 1 1 8 1 8 1 1 S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte A Data Byte N P SDA/SCL Connections Recommendations The serial interface inputs don’t have glitch suppression circuit. So, any noises or glitches at serial input lines may cause programming error. The serial interface lines should be routed in such a way that the lines would have minimum noise impact from the surroundings. Figure 5 is recommended to improve the interconnections. RP SCL CF Master CDCL6010 (Slave) RP SDA Figure 5. Serial Interface Connections Lower RP resistor value (around 1 kΩ) should be chosen so that signals will have faster rise time. A capacitor can be connected to SCL line to ground which will act as a filter. An I2C level translator will help to overcome the noises issue. 12 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com SDA/SCL Bus Configuration Command Bitmap Byte 0: Bit Bit Name Description/Function Type Power Up Condition 0 7 PLL-LOCK 1 if PLL has achieved lock, otherwise 0 R 6 MANF[6] Manufacturer reserved R 5 MANF[5] Manufacturer reserved R 4 MANF[4] Manufacturer reserved R 3 MANF[3] Manufacturer reserved R 2 MANF[2] Manufacturer reserved R 1 MANF[1] Manufacturer reserved R 0 MANF[0] Manufacturer reserved R Reference To Byte 1: Bit Bit Name Description/Function Type Power Up Condition Reference To 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 ENPH Phase select enable R/W 1 4 PH1[4] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5, Table 6 3 PH1[3] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5, Table 6 2 PH1[2] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5, Table 6 1 PH1[1] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5, Table 6 0 PH1[0] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5, Table 6 Type Power Up Condition Reference To Byte 2: Bit Bit Name Description/Function 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 ENP1 Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are disabled R/W 1 4 ENBP1 Bypass PLL for post-divider P1: If 1 input is CLKP/CLKN, if 0 input is PLL clock R/W 0 3 SELP1[3] Divide ratio select for post-divider P1 R/W 0 Table 2 2 SELP1[2] Divide ratio select for post-divider P1 R/W 1 Table 2 1 SELP1[1] Divide ratio select for post-divider P1 R/W 1 Table 2 0 SELP1[0] Divide ratio select for post-divider P1 R/W 1 Table 2 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 13 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Byte 3: Bit Name Bit Description/Function Type Power Up Condition Reference To 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 PLLLOC K OW PLL Lock Overwrite: If 1 output not gated by PLL Lock status. R/W 0 4 PH0[4] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5, Table 6 3 PH0[3] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5, Table 6 2 PH0[2] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5, Table 6 1 PH0[1] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5, Table 6 0 PH0[0] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5, Table 6 Type Power Up Condition Reference To Byte 4: Bit Bit Name Description/Function 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 ENP0 Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are disabled R/W 1 4 ENBP0 Bypass PLL for post-divider P0. If 1, input is CLKP/CLKN; if 0 input is PLL clock R/W 0 3 SELP0[3] Divide ratio select for post-divider P0 R/W 0 Table 2 2 SELP0[2] Divide ratio select for post-divider P0 R/W 1 Table 2 1 SELP0[1] Divide ratio select for post-divider P0 R/W 1 Table 2 0 SELP0[0] Divide ratio select for post-divider P0 R/W 1 Table 2 Type Power Up Condition Reference To Byte 5: Bit 14 Bit Name Description/Function 7 EN Chip enable; if 0 chip is in Iddq mode R/W 1 6 ENDRV10 YP10, YN10 enable; if 0 output is disabled R/W 1 5 ENDRV9 YP[9], YN[9] enable; if 0 output is disabled R/W 1 4 ENDRV8 YP[8], YN[8] enable; if 0 output is disabled R/W 1 3 ENDRV7 YP[7], YN[7] enable; if 0 output is disabled R/W 1 2 ENDRV6 YP[6], YN[6] enable; if 0 output is disabled R/W 1 1 ENDRV5 YP[5], YN[5] enable; if 0 output is disabled R/W 1 0 ENDRV4 YP[4], YN[4] enable; if 0 output is disabled R/W 1 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Byte 6: Bit Bit Name Description/Function Type Power Up Condition Reference To 7 ENDRV3 YP[3], YN[3] enable; if 0 output is disabled R/W 1 6 ENDRV2 YP[2], YN[2] enable; if 0 output is disabled R/W 1 5 ENDRV1 YP[1], YN[1] enable; if 0 output is disabled R/W 1 4 ENDRV0 YP[0], YN[0] enable; if 0 output is disabled R/W 1 3 SELBW[3] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7 2 SELBW[2] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7 1 SELBW[1] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7 0 SELBW[0] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7 Type Power Up Condition Reference To Byte 7: Bit Bit Name Description/Function 7 ENPLL PLL enable; if 0 PLL is switched off R/W 1 6 RES Reserved R/W 0 5 SELM[1] Divide ratio select for input clock CLKP and CLKN R/W 0 Table 4 4 SELM[0] Divide ratio select for input clock CLKP and CLKN R/W 0 Table 4 3 SELN[3] Divide ratio select for pre-divider N (PLL clock) R/W 1 Table 3 2 SELN[2] Divide ratio select for pre-divider N (PLL clock) R/W 0 Table 3 1 SELN[1] Divide ratio select for pre-divider N (PLL clock) R/W 0 Table 3 0 SELN[0] Divide ratio select for pre-divider N (PLL clock) R/W 1 Table 3 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 15 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Table 2. Divide Ratio Settings for Post-Divider P0 or P1 Divide Ratio SELP1[3] or SELP0[3] SELP1[2] or SELP0[2] SELP1[1] or SELP0[1] SELP1[0] or SELP0[0] 1 0 0 0 0 2 0 0 0 1 4 0 0 1 0 5 0 0 1 1 8 0 1 0 0 10 0 1 0 1 16 0 1 1 0 20 0 1 1 1 32 1 0 0 0 40 1 0 0 1 80 1 0 1 0 Notes Default Table 3. Divide Ratio Settings for Divider N Divide Ratio SELN[3] SELN[2] SELN[1] SELN[0] 32 1 0 0 0 40 1 0 0 1 Notes Default Table 4. Divide Ratio Settings for Divider M 16 Divide Ratio SELM[1] SELM[0] Notes 1 0 0 Default 2 0 1 4 1 0 8 1 1 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Table 5. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80 With PH0[4:0] = 00000 PH1 Divide Ratio [4] [3] [2] [1] [0] 5 X X X X X 0 10 X X X 0 X 0 X X X 1 X (2π/2) X X 0 0 X 0 X X 0 1 X (2π/4) X X 1 0 X 2(2π/4) X X 1 1 X 3(2π/4) X 0 0 0 X 0 X 0 0 1 X (2π/8) X 0 1 0 X 2(2π/8) X 0 1 1 X 3(2π/8) X 1 0 0 X 4(2π/8) X 1 0 1 X 5(2π/8) X 1 1 0 X 6(2π/8) X 1 1 1 X 7(2π/8) 0 0 0 0 X 0 0 0 0 1 X (2π/16) 0 0 1 0 X 2(2π/16) 0 0 1 1 X 3(2π/16) 0 1 0 0 X 4(2π/16) 0 1 0 1 X 5(2π/16) 0 1 1 0 X 6(2π/16) 0 1 1 1 X 7(2π/16) 1 0 0 0 X 8(2π/16) 1 0 0 1 X 9(2π/16) 1 0 1 0 X 10(2π/16) 1 0 1 1 X 11(2π/16) 1 1 0 0 X 12(2π/16) 1 1 0 1 X 13(2π/16) 1 1 1 0 X 14(2π/16) 1 1 1 1 X 15(2π/16) 20 40 80 Phase Lead (radian) Notes Phase setting not available 00000:Default Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 17 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Table 6. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32 With PH0[4:0] = 00000 PH1 Divide Ratio [4] [3] [2] [1] [0] 1 X X X X X 0 2 X X X X 0 0 X X X X 1 (2π/2) X X X 0 0 0 X X X 0 1 (2π/4) X X X 1 0 2(2π/4) X X X 1 1 3(2π/4) X X 0 0 0 0 X X 0 0 1 (2π/8) X X 0 1 0 2(2π/8) X X 0 1 1 3(2π/8) X X 1 0 0 4(2π/8) X X 1 0 1 5(2π/8) X X 1 1 0 6(2π/8) X X 1 1 1 7(2π/8) X 0 0 0 0 0 X 0 0 0 1 (2π/16) X 0 0 1 0 2(2π/16) X 0 0 1 1 3(2π/16) X 0 1 0 0 4(2π/16) X 0 1 0 1 5(2π/16) X 0 1 1 0 6(2π/16) X 0 1 1 1 7(2π/16) X 1 0 0 0 8(2π/16) X 1 0 0 1 9(2π/16) X 1 0 1 0 10(2π/16) X 1 0 1 1 11(2π/16) X 1 1 0 0 12(2π/16) X 1 1 0 1 13(2π/16) X 1 1 1 0 14(2π/16) X 1 1 1 1 15(2π/16) 4 8 16 18 Phase Lead (radian) Notes Phase setting not available Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Table 6. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32 (continued) With PH0[4:0] = 00000 PH1 Divide Ratio [4] [3] [2] [1] [0] Phase Lead (radian) 32 0 0 0 0 0 0 0 0 0 0 1 (2π/32) 0 0 0 1 0 2(2π/32) 0 0 0 1 1 3(2π/32) 0 0 1 0 0 4(2π/32) 0 0 1 0 1 5(2π/32) 0 0 1 1 0 6(2π/32) 0 0 1 1 1 7(2π/32) 0 1 0 0 0 8(2π/32) 0 1 0 0 1 9(2π/32) 0 1 0 1 0 10(2π/32) 0 1 0 1 1 11(2π/32) 0 1 1 0 0 12(2π/32) 0 1 1 0 1 13(2π/32) 0 1 1 1 0 14(2π/32) 0 1 1 1 1 15(2π/32) 1 0 0 0 0 16(2π/32) 1 0 0 0 1 17(2π/32) 1 0 0 1 0 18(2π/32) 1 0 0 1 1 19(2π/32) 1 0 1 0 0 20(2π/32) 1 0 1 0 1 21(2π/32) 1 0 1 1 0 22(2π/32) 1 0 1 1 1 23(2π/32) 1 1 0 0 0 24(2π/32) 1 1 0 0 1 25(2π/32) 1 1 0 1 0 26(2π/32) 1 1 0 1 1 27(2π/32) 1 1 1 0 0 28(2π/32) 1 1 1 0 1 29(2π/32) 1 1 1 1 0 30(2π/32) 1 1 1 1 1 31(2π/32) Notes Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 19 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com Table 7. PLL Bandwidth Setting (1) PLL Bandwidth (1) (kHz) SELBW [3] [2] [1] [0] C1 (nF) 400 0 0 0 0 350 0 0 1 0 300 0 0 1 250 0 1 200 0 1 175 1 150 125 R (Ω) C2 (nF) On-Chip Loop Filter ON/OFF N/A N/A N/A ON 2.2 8660 0 OFF 1 3.3 7500 0 OFF 0 0 4.7 6200 0 OFF 1 0 8.2 4990 0 OFF 0 0 0 10 4300 0 OFF 1 0 1 0 15 3740 0 OFF 1 1 1 1 22 3090 0 OFF 100 1 1 1 1 33 2490 0.24 OFF 75 1 1 1 1 56 1870 0.82 OFF 50 1 1 1 1 150 1210 2.70 OFF 20 1 1 1 1 680 470 18 OFF 10 1 1 1 1 3300 220 68 OFF Notes Default Refer to Functional Block Diagram for the external low pass filter architecture. FREQUENCY SETTINGS FOR SOME APPLICATIONS APPLICATION PROTOCOL Output Clock MHz Output Divider P0, P1 VCO Freq GHz PLL Divider N (max f) Ref Clock Divider M (max f) Ref Clock Max Freq MHz PLL Divider N (min f) Ref Clock Divider M (min f) Ref Clock Min Freq MHz 10G Ethernet 312.5 4 1.250 32 8 312.5 40 1 31.25 (XAUI) 156.25 8 1.250 32 8 312.5 40 1 31.25 78.125 16 1.250 32 8 312.5 40 1 31.25 62.5 20 1.250 32 8 312.5 40 1 31.25 1G Ethernet 250 5 1.250 40 8 250 40 1 31.25 Serial ATA 125 10 1.250 40 8 250 40 1 31.25 62.5 20 1.250 40 8 250 40 1 31.25 10X FIBRE CHANNEL 159.375 8 1.275 32 8 318.75 40 1 31.875 63.75 20 1.275 32 8 318.75 40 1 31.875 CPRI 245.76 5 1.229 40 8 245.78 40 1 30.72 122.88 10 1.229 40 8 245.78 40 1 30.72 61.44 20 1.229 40 8 245.78 40 1 30.72 30.72 40 1.229 40 8 245.78 40 1 30.72 153.6 8 1.229 32 8 307.2 32 1 38.4 76.8 16 1.229 32 8 307.2 32 1 38.4 PCI Express 250 5 1.250 40 8 250 40 1 31.25 Serial ATA 150 8 1.200 32 8 300 32 1 37.5 75 16 1.200 32 8 300 32 1 37.5 622.08 2 1.244 32 8 311.04 40 1 31.104 311.04 4 1.244 32 8 311.04 40 1 31.104 155.52 8 1.244 32 8 311.04 40 1 31.104 62.208 20 1.244 32 8 311.04 40 1 31.104 OBSAI SONET 20 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 CDCL6010 SLLS780B – FEBRUARY 2007 – REVISED MARCH 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (February 2007) to Revision A • Page Added second specification condition for clock output skew parameter. ............................................................................. 4 Changes from Revision A (March 2008) to Revision B Page • Added Sentence to the Description: The serial interface is 1.8V tolerant only. ................................................................... 2 • Changed VILVDS From: -0.3 to 4.0 To: -0.3 to VDD + 0.6 in the Abs Max table ..................................................................... 3 • Changed VI From: -0.3 to 3.0 To: -0.3 to VDD + 0.6 in the Abs Max table ............................................................................ 3 • Added the THERMAL INFORMATION table ........................................................................................................................ 3 • Changed the Test Conditions of VD,OUT in the AC Electrical Characteristics table ............................................................... 4 • Changed the description of SCL and SDA in the PIn Functions table ................................................................................. 7 • Added Note 1 to the FUNCTIONAL BLOCK DIAGRAM ....................................................................................................... 8 • Added the SDA/SCL Connections Recommendations section .......................................................................................... 12 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): CDCL6010 21 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CDCL6010RGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCL 6010 Samples CDCL6010RGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCL 6010 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of