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CDCLVC1102, CDCLVC1103, CDCLVC1104
CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family
1 Features
3 Description
•
The CDCLVC11xx is a modular, high-performance,
low-skew, general-purpose clock buffer family from
Texas Instruments.
1
•
•
•
•
•
•
High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10,
1:12 LVCMOS Clock Buffer Family
Very Low Pin-to-Pin Skew < 50 ps
Very Low Additive Jitter < 100 fs
Supply Voltage: 3.3 V or 2.5 V
fmax = 250 MHz for 3.3 V
fmax = 180 MHz for 2.5 V
Operating Temperature Range: –40°C to 85°C
Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP
Package (All Pin-Compatible)
2 Applications
General-Purpose Communication, Industrial, and
Consumer Applications
The entire family is designed with a modular
approach in mind. It is intended to round up TI's
series of LVCMOS clock generators.
Seven different fan-out variations, 1:2 to 1:12, are
available. All of the devices are pin-compatible to
each other for easy handling.
All family members share the same high performing
characteristics such as low additive jitter, low skew,
and wide operating temperature range.
The CDCLVC11xx supports an asynchronous output
enable control (1G) which switches the outputs into a
low state when 1G is low.
The CDCLVC11xx family operates in a 2.5-V and
3.3-V environment and are characterized for
operation from –40°C to 85°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCLVC1102
CDCLVC1103
TSSOP (8)
3.00 mm × 4.40 mm
CDCLVC1104
CDCLVC1106
TSSOP (14)
CDCLVC1108
TSSOP (16)
CDCLVC1110
TSSOP (20)
6.50 mm × 4.40 mm
CDCLVC1112
TSSOP (24)
7.80 mm × 4.40 mm
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
CLKIN
LV
CMOS
LV
CMOS
Y0
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
•
•
•
LV
CMOS
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y9 10
GND 11
Y11 12
CDCLVC
CDCLVC
CDCLVC
1102
1103
1104
CDCLVC
1106
CDCLVC
1108
CDCLVC
1110
CDCLVC
1112
24
23
22
21
20
19
18
17
16
15
14
13
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
Y8
GND
Y 10
VDD
Yn
1G
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCLVC1102, CDCLVC1103, CDCLVC1104
CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
10.1 Power Considerations ........................................... 13
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
Changes from Revision A (October 2014) to Revision B
Page
•
Changed Packaging name from TTSOP to TSSOP in Device Information Table ................................................................. 1
•
Changed CDCLVC1110 Y8 pin number from: 10 to: 12 ........................................................................................................ 3
•
Changed CDCLVC1110 Y9 pin number from: — to: 10......................................................................................................... 3
•
Moved Tstg from ESD Ratings to Absolute Maximum Ratings .............................................................................................. 5
•
Added Receiving Notification of Documentation Updates and Community Resources sections ......................................... 15
Changes from Original (May 2010) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
5 Pin Configuration and Functions
PW Package
8-, 14-, 16-, 20, 24-Pin TSSOP
Top View
CLKIN
1G
Y0
GND
1
2
3
4
CLKIN
1G
Y0
GND
1
2
3
4
CDCLVC1103
CLKIN
1G
Y0
GND
1
2
3
4
CDCLVC1104
CDCLVC1102
8
7
6
5
Y1
NC
VDD
NC
8
7
6
5
Y1
NC
VDD
Y2
8
7
6
5
Y1
Y3
VDD
Y2
CLKIN
1G
Y0
GND
VDD
Y4
GND
1
2
3
4
5
6
7
CLKIN
1G
Y0
GND
VDD
Y4
GND
Y6
1
2
3
4
5
6
7
8
CDCLVC1106
CDCLVC1108
14
13
12
11
10
9
8
Y1
Y3
VDD
Y2
GND
Y5
VDD
16
15
14
13
12
11
10
9
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y 9 10
CDCLVC 1110
20
19
18
17
16
15
14
13
12
11
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
Y8
GND
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y 9 10
GND 11
Y 11 12
CDCLVC 1112
24
23
22
21
20
19
18
17
16
15
14
13
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
Y8
GND
Y 10
VDD
Pin Functions
PIN
NAME
CDCLVC
1102
CDCLVC
1103
CDCLVC
1104
CDCLVC
1106
CDCLVC
1108
CDCLVC
1110
CDCLVC
1112
TYPE
DESCRIPTION
1
1
1
1
1
Input
Input Pin
2
2
2
2
2
Input
Output Enable
LVCMOS CLOCK INPUT
CLKIN
1
1
CLOCK OUTPUT ENABLE
1G
2
2
LVCMOS CLOCK OUTPUT
Y0
3
3
3
3
3
3
3
Y1
8
8
8
14
16
20
24
Y2
—
5
5
11
13
17
21
Y3
—
—
7
13
15
19
23
Y4
—
—
—
6
6
6
6
Y5
—
—
—
9
11
15
19
Y6
—
—
—
—
8
8
8
Y7
—
—
—
—
9
13
17
Y8
—
—
—
—
—
12
16
Y9
—
—
—
—
—
10
10
Y10
—
—
—
—
—
—
14
Y11
—
—
—
—
—
—
12
5
5
9
13
8
10
14
18
12
14
18
22
Output
LVCMOS output. Unused
outputs can be left floating.
Power
2.5-V or device supply
SUPPLY VOLTAGE
VDD
6
6
6
5
5
9
GROUND
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3
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
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Pin Functions (continued)
PIN
NAME
GND
4
CDCLVC
1102
4
CDCLVC
1103
4
CDCLVC
1104
CDCLVC
1106
CDCLVC
1108
4
4
7
11
7
7
11
15
10
12
16
20
4
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CDCLVC
1110
4
CDCLVC
1112
TYPE
DESCRIPTION
GND
Device ground
4
7
Copyright © 2010–2017, Texas Instruments Incorporated
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CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VDD
(1)
MIN
MAX
UNIT
Supply voltage
–0.5
4.6
V
(2)
V
VIN
Input voltage
–0.5
VDD + 0.5
VO
Output voltage (2)
–0.5
VDD + 0.5
V
IIN
Input current
–20
20
mA
IO
Continuous output current
–50
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
–65
50
mA
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 4.6 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3.3-V supply
3.0
3.3
3.6
2.5-V supply
2.3
2.5
2.7
VDD
Supply voltage
VIL
Low-level input voltage
VIH
High-level input voltage
Vth
Input threshold voltage
tr / tf
Input slew rate
tw
Minimum pulse width at
CLKIN
VDD = 3.0 V to 3.6 V
1.8
VDD = 2.3 V to 2.7 V
2.75
fCLK
LVCMOS clock Input
Frequency
VDD = 3.0 V to 3.6 V
DC
250
VDD = 2.3 V to 2.7 V
DC
180
TA
Operating free-air temperature
–40
85
VDD = 3.0 V to 3.6 V
VDD/2 – 600
VDD = 2.3 V to 2.7 V
VDD/2 – 400
VDD = 3.0 V to 3.6 V
VDD/2 + 600
VDD = 2.3 V to 2.7 V
VDD/2 + 400
VDD = 2.3 V to 3.6 V
V
mV
mV
VDD/2
1
Copyright © 2010–2017, Texas Instruments Incorporated
UNIT
mV
4
V/ns
ns
MHz
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°C
5
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CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
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6.4 Thermal Information
CDCLVC1102
CDCLVC1103
CDCLVC1104
THERMAL METRIC (1)
CDCLVC1106
CDCLVC1108
CDCLVC11010
CDCLVC1112
UNIT
PW (TSSOP)
8 PINS
14 PINS
16 PINS
20 PINS
24 PINS
RθJA
Junction-to-ambient thermal
resistance (2)
149.4
112.6
108.4
83.0
87.9
°C/W
RθJC(top)
Junction-to-case(top) thermal
resistance (3)
69.4
48.0
33.6
32.3
26.5
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
MIN TYP (1)
MAX
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V
6
10
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 2.7 V
3
6
PARAMETER
TEST CONDITIONS
UNIT
OVERALL PARAMETERS FOR ALL VERSIONS
IDD
Static device current (2)
IPD
Power-down current
1G = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V or 2.7 V
CPD
Power dissipation capacitance
per output (3)
VDD = 3.3 V; f = 10 MHz
6
VDD = 2.5 V; f = 10 MHz
4.5
II
Input leakage current at 1G
Input leakage current at CLKIN
ROUT Output impedance
fOUT
Output frequency
VI = 0 V or VDD, VDD = 3.6 V or 2.7 V
60
8
25
25
45
VDD = 2.5 V
60
µA
pF
8
VDD = 3.3 V
mA
µA
Ω
VDD = 3 V to 3.6 V
DC
250
VDD = 2.3 V to 2.7 V
DC
180
MHz
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
VOH
VOL
High-level output voltage
Low-level output voltage
VDD = 3 V, IOH = –0.1 mA
2.9
VDD = 3 V, IOH = –8 mA
2.5
VDD = 3 V, IOH = –12 mA
2.2
V
VDD = 3 V, IOL = 0.1 mA
0.1
VDD = 3 V, IOL = 8 mA
0.5
VDD = 3 V, IOL = 12 mA
0.8
V
OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V
VOH
High-level output voltage
VOL
Low-level output voltage
(1)
(2)
(3)
6
VDD = 2.3 V, IOH = –0.1 mA
2.2
VDD = 2.3 V, IOH = –8 mA
1.7
V
VDD = 2.3 V, IOL = 0.1 mA
0.1
VDD = 2.3 V, IOL = 8 mA
0.5
V
All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 Ω to VDD/2 (see Figure 3).
For dynamic IDD over frequency see and Figure 1.
This is the formula for the power dissipation calculation (see and the Power Considerations section).
Ptot = Pstat + Pdyn + PCload [W]
Pstat = VDD × IDD [W]
Pdyn = CPD × VDD2 × ƒ [W]
PCload = Cload × VDD2 × ƒ × n [W]
n = Number of switching output pins
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
tPLH, tPHL
Propagation delay
CLKIN to Yn
tsk(o)
Output skew
Equal load of each output
2.0
ns
50
tr/tf
Rise and fall time
20%–80% (VOH - VOL)
ps
0.8
ns
tDIS
Output disable time
tEN
Output enable time
1G to Yn
6
ns
1G to Yn
6
tsk(p)
Pulse skew ;
tPLH(Yn) – tPHL(Yn)
ns
To be measured with input duty
cycle of 50%
180
ps
tsk(pp)
Part-to-part skew
Under equal operating conditions for
two parts
0.5
ns
tjitter
Additive jitter rms (2)
12 kHz to 20 MHz, fOUT = 250 MHz
100
fs
2.6
ns
50
ps
(1)
0.8
0.3
OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V
tPLH, tPHL
Propagation delay
CLKIN to Yn
tsk(o)
Output skew
Equal load of each output
tr/tf
Rise and fall time
20%–80% reference point
1.2
ns
tDIS
Output disable time
1G to Yn
10
ns
tEN
Output enable time
1G to Yn
10
ns
tsk(p)
Pulse skew ;
tPLH(Yn) – tPHL(Yn)
To be measured with input duty
cycle of 50%
220
ps
tsk(pp)
Part-to-part skew
Under equal operating conditions for
two parts
1.2
ns
tjitter
Additive jitter rms (2)
12 kHz to 20 MHz, fOUT = 180 MHz
350
fs
(1)
(2)
(1)
1
0.3
tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is pulsewidth of output waveform and tperiod is 1/fOUT.
Parameter is specified by characterization. Not tested in production.
6.7 Typical Characteristics
15
3
Pdyn + PCload8pF
VDD = 2.5 V
Pdyn + PCload50/2
10
5
Pdyn + PCload2pF
0
0
20
40
60
80 100 120 140
f - Clock Frequency - MHz
160 180
Figure 1. Device Power Consumption vs Clock Frequency
(Load 50 Ω into VDD/2; 2 pF, 8 pF; Per Output)
Copyright © 2010–2017, Texas Instruments Incorporated
Idyn - Dynamic Supply Current - mA
Device Power Consumption - mW
VDD = 2.5 V
2
Idyn = CPD * VDD * f
1
0
0
20
40
60
80 100 120 140
f - Clock Frequency - MHz
160 180
Figure 2. Dynamic Supply Current vs Clock Frequency
(CPD = 4.5 pF, No Load; Per Output)
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7 Parameter Measurement Information
VDD = 3.3 V or 2.5 V
LVCMOS
Output
ZO = 50 W
R = 50 W
C = 2 pF
parasitic capasitance
from Measurement Equipment
VDD/2
Figure 3. Test Load Circuit
VDD
VDD = 3.3 V or 2.5 V
R= 100 W
LVCMOS
Output
ZO = 50 W
parasitic input capacitance
R= 100 W
Figure 4. Application Load With 50-Ω Line Termination
VDD = 3.3 V or 2.5 V
RS = 10 W (VDD = 3.3 V)
RS = 0 W (VDD = 2.5 V)
LVCMOS
Output
ZO = 50 W
parasitic input capacitance
Figure 5. Application Load With Series Line Termination
VDD / 2
VIN / 2
Yn
1G
VIN / 2
Yn
tDIS
tEN
Figure 6. tDIS and tEN for Disable Low
8
VDD / 2
Yn+1
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tsk(o)
tsk(o)
Figure 7. Output Skew tsk(o)
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
Parameter Measurement Information (continued)
V DD / 2
CLKIN
CLKIN
VOH
V DD / 2
Yn
80 % V OH -V OL
Yn
20 % V OH -V OL
V OL
t PLH
tr
tf
t PHL
Note: tsk (p) = | tPLH – t PHL |
Figure 8. Pulse Skew tsk(p) and Propagation Delay
tPLH/tPHL
Copyright © 2010–2017, Texas Instruments Incorporated
Figure 9. Rise/Fall Times tr/tf
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8 Detailed Description
8.1 Overview
The CDCLVC11xx family of devices is a low-jitter and low-skew LVCMOS fan-out buffer solution. For best signal
integrity, it is important to match the characteristic impedance of the CDCLVC11xx's output driver with that of the
transmission line. Figure 5 and Figure 6 show the proper configuration per configuration for both VDD = 3.3 V and
VDD = 2.5 V. TI recommends placing the series resistor close to the driver to minimize signal reflection.
8.2 Functional Block Diagram
CLKIN
LV
CMOS
LV
CMOS
Y0
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y9 10
GND 11
Y11 12
•
•
•
LV
CMOS
CDCLVC
CDCLVC
CDCLVC
1102
1103
1104
CDCLVC
1106
CDCLVC
1108
CDCLVC
1110
CDCLVC
1112
24
23
22
21
20
19
18
17
16
15
14
13
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
Y8
GND
Y 10
VDD
Yn
1G
Table 1. Output Logic Table
INPUTS
OUTPUTS
CLKIN
1G
Yn
X
L
L
L
H
L
H
H
H
8.3 Feature Description
The outputs of the CDCLVC11xx can be disabled by driving the asynchronous output enable pin (1G) low.
Unused output can be left floating to reduce overall system component cost. All supply and ground pins must be
connected to VDD and GND, respectively.
8.4 Device Functional Modes
The CDCLVC11xx operates from supplies between 2.5 V and 3.3 V.
10
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CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCLVC11xx family is a low additive jitter LVCMOS buffer solution that can operate up to 250 MHz at and
180 MHz at VDD = 2.5 V. Low output skew as well as the ability for asynchronous output enable is featured to
simultaneously enable or disable buffered clock outputs as necessary in the application.
9.2 Typical Application
Figure 10. Example System Configuration
9.2.1 Design Requirements
The CDCLVC11xx shown in Figure 10 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator.
The CPU is configured to control the output state through 1G.
The configuration example is driving three LVCMOS receivers in a backplane application with the following
properties:
• The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the
CDCLVC11xx to closely match the characteristic impedance of the trace to minimize reflections.
• The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the CDCLVC11xx.
• The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.
The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage is
mismatched.
9.2.2 Detailed Design Procedure
Refer to Figure 5 and the Electrical Characteristics table to determine the appropriate series resistance needed
for matching the output impedance of the CDCLVC11xx to that of the characteristic impedance of the
transmission line.
Unused outputs can be left floating. See the Power Supply Recommendations section for recommended filtering
techniques.
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CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
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Typical Application (continued)
9.2.3 Application Curves
Figure 11. CDCLVC11xx Reference Phase Noise 26 fs
(12 kHz to 20 MHz)
Figure 12. CDCLVC11xx Output Phase Noise 86 fs
(12 kHz to 20 MHz)
The low additive jitter of the CDCLVC11xx can be shown in the previous application example. The low-noise
100-MHz XO with 26-fs RMS jitter drives the CDCLVC11xx, resulting in 86-fs RMS jitter when integrated from 12
kHz to 20 MHz. The resultant additive jitter is a low 82-fs RMS for this configuration.
10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
the jitter and phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guards the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. TI
recommends adding as many high-frequency (for example, 0.1 µF) bypass capacitors, as there are supply
terminals in the package. TI recommends, but does not require, inserting a ferrite bead between the board power
supply and the chip power supply that isolates the high-frequency switching noises generated by the clock buffer;
these beads prevent the switching noise from leaking into the board supply. It is imperative to choose an
appropriate ferrite bead with very low DC resistance to provide adequate isolation between the board supply and
the chip supply, as well as to maintain a voltage at the supply terminals that is greater than the minimum voltage
required for proper operation.
12
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CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
Figure 13 shows this recommended power supply decoupling method.
Figure 13. Power Supply Decoupling
10.1 Power Considerations
The following power consideration refers to the device-consumed power consumption only. The device power
consumption is the sum of static power and dynamic power. The dynamic power usage consists of two
components:
• Power used by the device as it switches states.
• Power required to charge any output load.
The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs in
and Figure 1 can be used to obtain the power consumption of the device:
Pdev = Pstat + n (Pdyn + PCload)
Pstat = VDD × IDD
Pdyn + PCload = see and Figure 1
where:
VDD = Supply voltage ( or 2.5 V)
IDD = Static device current (typical 6 mA for VDD = 3.3 V; typical 3 mA for VDD = 2.5 V)
n = Number of switching output pins
Example for device power consumption for CDCLVC1104: four outputs are switching, f = 120 MHz, VDD = 3.3 V,
and Cload = 2 pF per output:
Pdev = Pstat + n (Pdyn + PCload) = 19.8 mW + 40 mW = 59.8 mW
Pstat = VDD × IDD = 6 mA × 3.3 V = 19.8 mW
n (Pdyn + PCload) = 4 × 10 mW = 40 mW
NOTE
For dimensioning the power supply, the total power consumption must be considered. The
total power consumption is the sum of the device power consumption and the power
consumption of the load.
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13
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CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
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11 Layout
11.1 Layout Guidelines
Figure 14 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
11.2 Layout Example
Figure 14. PCB Conceptual Layout
14
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CDCLVC1112
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CDCLVC1106, CDCLVC1108, CDCLVC1110, CDCLVC1112
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SCAS895B – MAY 2010 – REVISED FEBRUARY 2017
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CDCLVC1102
Click here
Click here
Click here
Click here
Click here
CDCLVC1103
Click here
Click here
Click here
Click here
Click here
CDCLVC1104
Click here
Click here
Click here
Click here
Click here
CDCLVC1106
Click here
Click here
Click here
Click here
Click here
CDCLVC1108
Click here
Click here
Click here
Click here
Click here
CDCLVC1110
Click here
Click here
Click here
Click here
Click here
CDCLVC1112
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2017, Texas Instruments Incorporated
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15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCLVC1102PW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C2
CDCLVC1102PWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C2
CDCLVC1103PW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C3
CDCLVC1103PWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C3
CDCLVC1104PW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C4
CDCLVC1104PWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C4
CDCLVC1106PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C6
CDCLVC1106PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C6
CDCLVC1108PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C8
CDCLVC1108PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9C8
CDCLVC1110PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9CA
CDCLVC1110PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9CA
CDCLVC1112PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9CC
CDCLVC1112PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C9CC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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