CDCLVD110AVF

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CDCLVD110A SCAS841D – FEBRUARY 2007 – REVISED DECEMBER 2016 CDCLVD110A Programmable Low-Voltage 1:10 LVDS Clock Driver 1 Features 3 Description • The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines. 1 • • • • • • • • Low-Output Skew