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CDCLVD1208
SCAS899A – AUGUST 2010 – REVISED OCTOBER 2016
CDCLVD1208 2:8 Low Additive Jitter LVDS Buffer
1 Features
3 Description
•
•
The CDCLVD1208 clock buffer distributes one of two
selectable clock inputs (IN0 and IN1) to 8 pairs of
differential LVDS clock outputs (OUT0 through OUT7)
with minimum skew for clock distribution. The
CDCLVD1208 can accept two clock sources into an
input multiplexer. The inputs can either be LVDS,
LVPECL, or LVCMOS.
1
•
•
•
•
•
•
•
•
•
•
2:8 Differential Buffer
Low Additive Jitter: < 300-fs RMS in 10-kHz to
20-MHz
Low Output Skew of 45 ps (Maximum)
Universal Inputs Accept LVDS, LVPECL, and
LVCMOS
Selectable Clock Inputs Through Control Pin
8 LVDS Outputs, ANSI EIA/TIA-644A Standard
Compatible
Clock Frequency: Up to 800 MHz
Device Power Supply: 2.375 V to 2.625 V
LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Packaged in 5-mm × 5-mm, 28-Pin VQFN (RHD)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
2 Applications
•
•
•
•
•
Telecommunications and Networking
Medical Imaging
Test and Measurement Equipment
Wireless Communications
General-Purpose Clocking
The CDCLVD1208 is specifically designed for driving
50-Ω transmission lines. In case of driving the inputs
in single-ended mode, the appropriate bias voltage,
VAC_REF, must be applied to the unused negative
input pin.
The IN_SEL pin selects the input which is routed to
the outputs. If this pin is left open, it disables the
outputs (static). The part supports a fail-safe function.
The device incorporates an input hysteresis which
prevents random oscillation of the outputs in the
absence of an input signal.
The device operates in 2.5-V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD1208 is packaged in
small, 28-pin, 5-mm × 5-mm VQFN package.
Device Information(1)
PART NUMBER
CDCLVD1208
PACKAGE
VQFN (28)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Example
125 MHz
125 MHz
Oscillator
CDCLVD1208
LVDS Buffer
PHY2
PHY2
PHY2
PHY2
PHY2
PHY2
PHY 7
IN_ SEL
FPGA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCLVD1208
SCAS899A – AUGUST 2010 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
11.3 Thermal Considerations ........................................ 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2010) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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SCAS899A – AUGUST 2010 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
OUTP 4
OUTN 3
OUTP 3
OUTN 2
OUTP 2
OUTN 1
OUTP 1
VCC
RHD Package
28-Pin VQFN
Top View
21
20
19
18
17
16
15
22
5mm x5mm
28 pin QFN
14
GND
13
OUTN0
OUTP0
OUTN 4
23
OUTP 5
24
12
OUTN 5
25
11
OUTP 6
26
10
INN 0
OUTN 6
27
9
INP 0
8
VCC
5
6
7
INN1
VAC_REF1
4
INP1
3
IN_SEL
2
OUTN 7
1
OUTP 7
28
GND
VCC
Thermal Pad
VAC_REF0
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1, 14
GND
G
Device ground
2, 3
OUTP7, OUTN7
O
Differential LVDS output pair number 7
IN_SEL
I
Input Selection with an internal 200-kΩ pullup and pulldown, selects input port; (See Table 1)
INP1, INN1
I
Differential redundant input pair or single-ended input
VAC_REF1
O
Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF
capacitor to GND on this pin.
VCC
P
2.5-V supplies for the device
INP0, INN0
I
Differential input pair or single-ended input
VAC_REF0
O
Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF
capacitor to GND on this pin.
12, 13
OUTP0, OUTN0
O
Differential LVDS output pair number 0
16, 17
OUTP1, OUTN1
O
Differential LVDS output pair number 1
18, 19
OUTP2, OUTN2
O
Differential LVDS output pair number 2
20, 21
OUTP3, OUTN3
O
Differential LVDS output pair number 3
22, 23
OUTP4, OUTN4
O
Differential LVDS output pair number 4
24, 25
OUTP5, OUTN5
O
Differential LVDS output pair number 5
26, 27
OUTP6, OUTN6
O
Differential LVDS output pair number 6
4
5, 6
7
8, 15, 28
9, 10
11
(1)
G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VCC
–0.3
2.8
V
Input voltage, VI
–0.2
VCC + 0.2
V
Output voltage, VO
–0.2
VCC + 0.2
V
150
°C
Driver short-circuit current, IOSD
Storage temperature, Tstg
(1)
(2)
(2)
See
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The output can handle the permanent short.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
>3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
>1000
UNIT
V
Human Body Model, 1.5-kΩ, 100-pF
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Device supply voltage
TA
Ambient temperature
MIN
TYP
MAX
2.375
2.5
2.625
V
85
°C
–40
UNIT
6.4 Thermal Information
CDCLVD1208
THERMAL METRIC (1)
RHD (VQFN)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
34
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27
°C/W
RθJB
Junction-to-board thermal resistance
9
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IN_SEL CONTROL INPUT CHARACTERISTICS
VdI3
3-state input
VdIH
Input high voltage
Open
VdIL
Input low voltage
IdIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IdIL
Input low current
VCC = 2.625 V, VIL = 0 V
0.5 × VCC
V
0.7 × VCC
Rpull(IN_SEL) Input pullup and pulldown resistors
V
0.2 × VCC
V
30
µA
-30
µA
200
kΩ
2.5-V LVCMOS (SEE Figure 5) INPUT CHARACTERISTICS
fIN
Input frequency
External threshold voltage applied to
complementary input
Vth
Input threshold voltage
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IIL
Input low current
VCC = 2.625 V, VIL = 0 V
ΔV/ΔT
Input edge rate
20% to 80%
CIN
Input capacitance
200
MHz
1.5
V
Vth + 0.1
VCC
V
0
Vth – 0.1
V
10
µA
1.1
–10
1.5
µA
V/ns
2.5
pF
DIFFERENTIAL INPUT CHARACTERISTICS
fIN
Input frequency
Clock input
VIN,
Differential input voltage peak-to-peak
VICM = 1.25 V
VICM
Input common-mode voltage
VIN, DIFF, PP > 0.4 V
IIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IIL
Input low current
VCC = 2.625, VIL = 0 V
ΔV/ΔT
Input edge rate
20% to 80%
CIN
Input capacitance
DIFF
800
MHz
0.3
1.6
VPP
1
VCC – 0.3
V
10
µA
–10
0.75
µA
V/ns
2.5
pF
LVDS OUTPUT CHARACTERISTICS
|VOD|
Differential output voltage magnitude
VIN, DIFF, PP = 0.3 V, RL = 100 Ω
250
450
mV
ΔVOD
Change in differential output
voltage magnitude
VIN, DIFF, PP = 0.3 V, RL = 100 Ω
–15
15
mV
VOC(SS)
Steady-state common-mode output voltage
VIN, DIFF, PP = 0.3 V, RL = 100 Ω
1.1
1.375
ΔVOC(SS)
Steady-state common-mode output voltage
VIN, DIFF, PP = 0.6 V, RL = 100 Ω
–15
15
Vring
Output overshoot and undershoot
Percentage of output amplitude VOD
VOS
Output AC common mode
VIN, DIFF, PP = 0.6 V, RL = 100 Ω
IOS
Short-circuit output current
VOD = 0 V
tPD
Propagation delay
VIN, DIFF, PP = 0.3 V
tSK, PP
Part-to-part Skew
tSK, O
Output skew
tSK,P
Pulse skew (with 50% duty cycle input)
Crossing-point-to-crossing-point
distortion
tRJIT
Random additive jitter
(with 50% duty cycle input)
Edge speed 0.75 V/ns,
10 kHz to 20 MHz
tR/tF
Output rise and fall time
20% to 80%, 100 Ω, 5 pF
300
ps
ICCSTAT
Static supply current
Outputs unterminated, f = 0 Hz
17
28
mA
ICC100
Supply current
All outputs, RL = 100 Ω, f = 100 MHz
62
84
mA
ICC800
Supply current
All outputs, RL = 100 Ω, f = 800 MHz
87
111
mA
1.25
1.35
V
V
mV
10%
40
1.5
–50
50
70
mVPP
±24
mA
2.5
ns
600
ps
45
ps
50
ps
0.3
ps,
RMS
VAC_REF CHARACTERISTICS
VAC_REF
Reference output voltage
VCC = 2.5 V Iload = 100 µA
1.1
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
ADDITIVE PHASE NOISE FOR 100-MHZ CLOCK
phn100
Phase noise at 100-Hz offset
–132.9
dBc/Hz
phn1k
Phase noise at 1-kHz offset
–138.8
dBc/Hz
phn10k
Phase noise at 10-kHz offset
–147.4
dBc/Hz
phn100k
Phase noise at 100-kHz offset
–153.6
dBc/Hz
phn1M
Phase noise at 1-MHz offset
–155.2
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–156.2
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–156.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
171
fs, RMS
ADDITIVE PHASE NOISE FOR 737.27-MHZ CLOCK
phn100
Phase noise at 100-Hz offset
phn1k
Phase noise at 1-kHz offset
–80.2
dBc/Hz
–114.3
phn10k
Phase noise at 10-kHz offset
dBc/Hz
–138
dBc/Hz
phn100k
phn1M
Phase noise at 100-kHz offset
–143.9
dBc/Hz
Phase noise at 1-MHz offset
–145.2
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–146.5
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–146.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
65
fs, RMS
6
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6.7 Typical Characteristics
VOD − Differential Output Voltage − mV
350
TA = 25oC
340
2.625V
330
320
2.5V
310
300
2.375V
290
280
270
260
250
0
100
200
300
400
500
600
700
800
Frequency − MHz
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive
RMS jitter is 152 fs, TA = 25°C, and VCC = 2.5 V
Figure 1. 100-MHz Input and Output Phase Noise Plot
Figure 2. Differential Output Voltage vs Frequency
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7 Parameter Measurement Information
Oscilloscope
100 W
LVDS
Figure 3. LVDS Output DC Configuration During Device Test
Phase Noise
Analyzer
LVDS
50 W
Figure 4. LVDS Output AC Configuration During Device Test
VIH
Vth
IN
VIL
IN
Vth
Figure 5. DC-Coupled LVCMOS Input During Device Test
VOH
OUTNx
VOD
OUTPx
VOL
80%
VOUT,DIFF,PP (= 2 x VOD)
20%
0V
tr
tf
Figure 6. Output Voltage and Rise/Fall Time
8
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INNx
INPx
tPLH0
tPHL0
tPLH1
tPHL1
OUTN0
OUTP0
OUTN1
OUTP1
tPLH2
tPHL2
OUTN2
OUTP2
OUTN7
tPHL7
tPLH7
OUTP7
A.
Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or
the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B.
Part to part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn
or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
Figure 7. Output Skew and Part-to-Part Skew
Vring
OUTNx
VOD
0 V Differential
OUTPx
Figure 8. Output Overshoot and Undershoot
VOS
GND
Figure 9. Output AC Common Mode
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8 Detailed Description
8.1 Overview
The CDCLVD1208 LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing
and termination are required to ensure correct operation of the device and to maximize signal integrity.
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI
recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage
different than the output common-mode voltage of the CDCLVD1208, AC-coupling must be used. If the LVDS
receiver has internal 100-Ω termination, external termination must be omitted.
8.2 Functional Block Diagram
VCC
VAC_REF0
VCC
VCC
Reference
Generator
VAC_REF1
IN_MUX
INP0
INN0
INP1
OUTP [0..7]
LVDS
OUTN [0..7]
INN1
200 kW
IN_SEL
200 kW
GND GND
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8.3 Feature Description
The CDCLVD1208 is a low additive jitter LVDS fan-out buffer that can generate eight copies of two selectable
LVPECL, LVDS, or LVCMOS inputs. The CDCLVD1208 can accept reference clock frequencies up to 800 MHz
while providing low output skew.
8.4 Device Functional Modes
The two inputs of the CDCLVD1208 are internally muxed together and can be selected through the control pin
(see Table 1). Unused inputs and outputs can be left floating to reduce overall component cost. Both AC- and
DC-coupling schemes can be used with the CDCLVD1208 to provide greater system flexibility.
10
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Table 1. Input Selection Table
IN_SEL
ACTIVE CLOCK INPUT
0
INP0, INN0
1
INP1, INN1
Open
(1)
None
(1)
The input buffers are disabled and the outputs are static.
8.4.1 LVDS Output Termination
Unused outputs can be left open without connecting any trace to the output pins.
The CDCLVD1208 can be connected to LVDS receiver inputs with DC- and AC-coupling as shown in Figure 10
and Figure 11 (respectively).
Z = 50 W
100 W
CDCLVD1208
LVDS
Z = 50 W
Figure 10. Output DC Termination
100 nF
Z = 50 W
100 W
CDCLVD1208
LVDS
Z = 50 W
100 nF
Figure 11. Output AC Termination (With the Receiver Internally Biased)
8.4.2 Input Termination
The CDCLVD1208 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.
LVDS drivers can be connected to CDCLVD1208 inputs with DC- and AC-coupling as shown Figure 12 and
Figure 13 (respectively).
Z = 50 W
100 W
LVDS
CDCLVD1208
Z = 50 W
Figure 12. LVDS Clock Driver Connected to CDCLVD1208 Input (DC-Coupled)
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100 nF
Z = 50 W
LVDS
CDCLVD1208
Z = 50 W
100 nF
50 W
50 W
VAC_REF
Figure 13. LVDS Clock Driver Connected to CDCLVD1208 Input (AC-Coupled)
Figure 14 shows how to connect LVPECL inputs to the CDCLVD1208. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP.
75 W
100 nF
Z = 50 W
CDCLVD1208
LVPECL
Z = 50 W
100 nF
75 W
150 W
150 W
50 W
50 W
VAC_REF
Figure 14. LVPECL Clock Driver Connected to CDCLVD1208 Input
Figure 15 illustrates how to couple a 2.5-V LVCMOS clock input to the CDCLVD1208 directly. The series
resistance, RS, must be placed close to the LVCMOS driver if required. 3.3-V LVCMOS clock input swing must
be limited to VIH ≤ VCC.
RS
LVCMOS
(2.5V)
Z = 50 W
CDCLVD1208
V
V
Vth = IH + IL
2
Figure 15. 2.5-V LVCMOS Clock Driver Connected to CDCLVD1208 Input
For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCLVD1208 is a low additive jitter universal to LVDS fan-out buffer with 2 selectable inputs. The small
package, low output skew, and low additive jitter make for a flexible device in demanding applications.
9.2 Typical Application
2.5 V
PHY
PRIREF_P
156.25 MHz LVDS
From Backplane
100
PRIREF_N
50
50
VAC_REF
ASIC
100
156.25 MHz LVCMOS
Oscillator
SECREF_P
FPGA
100
2.5 V
1k
SECREF_N
CPU
1k
100
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Figure 16. Fan-Out Buffer for Line Card Application
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Typical Application (continued)
9.2.1 Design Requirements
The CDCLVD1208 shown in Figure 16 is configured to select two inputs: a 156.25-MHz LVDS clock from the
backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. The LVDS clock is AC-coupled and biased
using the integrated reference voltage generator. A resistor divider is used to set the threshold voltage correctly
for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both VAC_REF and SECREF_N. Either input
signal can be then fanned out to desired devices, as shown. The configuration example is driving 4 LVDS
receivers in a line card application with the following properties:
• The PHY device is capable of DC-coupling with an LVDS driver such as the CDCLVD1208. This PHY device
features internal termination so no additional components are required for proper operation.
• The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as
the CDCLVD1208. Again, no additional components are required.
• The FPGA requires external AC-coupling, but has internal termination. 0.1-µF capacitors are placed to
provide AC-coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling
capacitors.
• The unused outputs of the CDCLVD1208 are left floating.
9.2.2 Detailed Design Procedure
See Input Termination for proper input terminations, dependent on single-ended or differential inputs.
See LVDS Output Termination for output termination schemes depending on the receiver application.
Unused outputs can be left floating.
In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power supply filtering and
bypassing is critical for low-noise applications.
See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in
Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043).
9.2.3 Application Curves
The CDCLVD12xx's low additive noise is shown in this line card application. The low noise 156.25-MHz source
with 67-fs RMS jitter drives the CDCLVD12xx, resulting in 80-fs RMS when integrated from 12 kHz to 20 MHz.
The resultant additive jitter is a low 44-fs RMS for this configuration.
Reference signal is low-noise Rohde and Schwarz SMA100A
Figure 17. CDCLVD12xx Reference Phase Noise,
67-fs RMS (12 kHz to 20 MHz)
14
Figure 18. CDCLVD12xx Output Phase Noise,
80-fs RMS (12 kHz to 20 MHz)
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10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must
be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends
adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.
TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip
power supply that isolates the high-frequency switching noises generated by the clock driver; these beads
prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DCresistance because it is imperative to provide adequate isolation between the board supply and the chip supply,
as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper
operation.
Figure 19 shows this recommended power-supply decoupling method.
Board
Supply
Chip
Supply
Ferrite Bead
1 µF
10µF
0.1 µF (x3)
Figure 19. Power Supply Decoupling
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11 Layout
11.1 Layout Guidelines
For reliability and performance reasons, the die temperature must be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed-circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. Figure 20 shows a recommended land
and via pattern.
11.2 Layout Example
3,0 mm (min)
0,33 mm (typ)
0,75 mm (typ)
Figure 20. Recommended PCB Layout
11.3 Thermal Considerations
The CDCLVD1208 supports high temperatures on the printed-circuit board (PCB) measured at the thermal pad.
The system designer must ensure that the maximum junction temperature is not exceeded. ΨJB can allow the
system designer to measure the board temperature with a fine gauge thermocouple and back calculate the
junction temperature using Equation 1. Note that ΨJB is close to RθJB as 75% to 95% of a device's heat is
dissipated by the PCB.
TJ = TPCB + ( ΨJB × Power)
(1)
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TPCB = 105°C
ΨJB = 8°C/W
PowerinclTerm = Imax × Vmax = 111 mA × 2.625 V = 291.4 mW (maximum power consumption including
termination resistors)
PowerexclTerm = 275.2 mW (maximum power consumption excluding termination resistors, see Power
Consumption of LVPECL and LVDS (SLYT127) for further details)
ΔTJ = ΨJB × PowerexclTerm = 8°C/W × 275.2 mW = 2.2°C
TJ = ΔTJ + TChassis = 2.2°C + 105°C = 107.2°C (maximum junction temperature of 125°C is not
violated)
Further information can be found at Semiconductor and IC Package Thermal Metrics (SPRA953) and Using
Thermal Calculation Tools for Analog Components (SLUA566).
16
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043)
• Power Consumption of LVPECL and LVDS (SLYT127)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
• Using Thermal Calculation Tools for Analog Components (SLUA556)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCLVD1208RHDR
ACTIVE
VQFN
RHD
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCLVD
1208
CDCLVD1208RHDT
ACTIVE
VQFN
RHD
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCLVD
1208
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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